a Dual Channel, Gain-Ranging ADC with RSSI AD6600 two input channels, each with 1 GHz input amplifiers and 30 dB of automatic gain-ranging circuitry. Both channels are sampled with a 450 MHz track-and-hold followed by an 11-bit, 20 MSPS analog-to-digital converter. Digital RSSI outputs, an A/B channel indicator, a 2× Clock output, references, and control circuitry are all on-chip. Digital output signals are two’s complement, CMOS-compatible and interface directly to 3.3 V or 5 V digital processing chips. FEATURES Dual IF Inputs, 70 MHz–250 MHz Diversity or Two Independent IF Signals Separate Attenuation Paths Oversample RF Channels 20 MSPS on a Single Carrier 10 MSPS/Channel in Diversity Mode Total Signal Range 90+ dB 30 dB from Automatic Gain-Ranging (AGC) 60 dB from A/D Converter Range >100 dB After Processing Gain Digital Outputs 11-Bit ADC Word 3-Bit RSSI Word 2 Clock, A/B Indicator Single 5 V Power Supply Output DVCC 3.3 V or 5 V 775 mW Power Dissipation The primary use for the dual analog input structure is sampling both antennas in a two-antenna diversity receiver. However, Channels A and B may also be used to sample two independent IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS per channel. In single-channel mode, the full clock rate of 20 MSPS may be applied to a single carrier. The AD6600 may be used as a stand-alone sampling chip, or it may be combined with the AD6620 Digital Receive Signal Processor. The AD6620 provides 10 dB–25 dB of additional processing gain before passing data to a fixed- or floating-point DSP. APPLICATIONS Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA Wireless Local Loop, Fixed Access Driving the AD6600 is simplified by using the AD6630 differential IF amplifier. The AD6630 is easily matched to inexpensive SAW filters from 70 MHz to 250 MHz. Designed specifically for cellular/PCS receivers, the AD6600 supports GSM, IS-136, CDMA and Wireless LANs, as well as proprietary air interfaces used in WLL/fixed-access systems. PRODUCT DESCRIPTION Units are available in plastic, surface-mount packages (44-lead LQFP) and specified over the industrial temperature range (–40°C to +85°C). The AD6600 mixed-signal receiver chip directly samples signals at analog input frequencies up to 250 MHz. The device includes FUNCTIONAL BLOCK DIAGRAM NOISE FILTER FLT FLT 0dB, –12dB, –24dB 630 RESONANT PORT AIN ATTEN AIN DETECT PEAK 3 SET RSSI RSSI GAIN ANALOG MUX AB_OUT GAIN ENCODE +12, +18dB A/D CONVERTER GAIN TWO'S COMPLEMENT 3 RSSI SELECT GAIN D10–D0 11 RSSI [2:0] ENCODE BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL B_SEL AVCC CLK2 TIMING AD6600 GND ENC ENC DVCC REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD6600–SPECIFICATIONS DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; T MIN = –40C, TMAX = +85C unless otherwise noted.) Parameter Temp Test Level ANALOG INPUTS (AIN, AIN/BIN, BIN) Differential Analog Input Voltage Range1 Differential Analog Input Resistance2 Differential Analog Input Capacitance Full Full 25°C V IV V PEAK DETECTOR (Internal), RSSI Resolution RSSI Gain Step RSSI Hysteresis3 Full Full V V 3 6 6 Bits dB dB RESONANT PORT (FLT, FLT) Differential Port Resistance Differential Port Capacitance Full Full V V 630 1.75 Ω pF A/D CONVERTER Resolution Full IV 11 Bits ENCODE INPUTS (ENC, ENC) Differential Input Voltage (AC-Coupled)4 Differential Input Resistance Differential Input Capacitance Full 25°C 25°C IV V V 0.4 11 2.5 V p-p kΩ pF A/B MODE INPUTS (A_SEL, B_SEL)5 Input High Voltage Range Input Low Voltage Range Full Full IV IV 4.75 0.0 Full Full II IV 4.75 3.0 Full Full Full POWER SUPPLY Supply Voltages AVCC DVCC Supply Current IAVCC (AVCC = 5.0 V) IDVCC (DVCC = 3.3 V) POWER CONSUMPTION6 Min 160 AD6600AST Typ 2.0 200 1.5 Max Unit 240 V p-p Ω pF 5.25 0.5 V V 5.0 3.3 5.25 5.25 V V II II 145 15 182 20 mA mA II 775 976 mW NOTES 1 Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs. 2 Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs. 3 Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations. 4 Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details. 5 A_SEL and B_SEL should be tied directly to ground or AVCC. 6 Maximum power consumption is computed as maximum current at nominal supplies. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; T Parameter Temp MIN = –40C, TMAX = +85C unless otherwise noted.) Test Level Min AD6600AST Typ Max Unit 1 LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0) Logic Compatibility Logic “1” Voltage (DVCC = 3.3 V) Full Logic “0” Voltage (DVCC = 3.3 V) Full Logic “1” Voltage (DVCC = 5.0 V) Full Logic “0” Voltage (DVCC = 5.0 V) Full Output Coding (D10–D0) CLK2× OUTPUT1, 2 Logic “1” Voltage (DVCC = 3.3 V) Logic “0” Voltage (DVCC = 3.3 V) Logic “1” Voltage (DVCC = 5.0 V) Logic “0” Voltage (DVCC = 5.0 V) Full Full Full Full II II IV IV 2.8 II II IV IV 2.8 4.0 4.0 CMOS DVCC – 0.2 0.2 DVCC – 0.35 0.35 Two’s Complement DVCC – 0.2 0.2 DVCC – 0.3 0.35 0.5 0.5 0.5 0.5 V V V V V V V V NOTES 1 Digital output load is one LCX gate. 2 CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz. Specifications subject to change without notice. –2– REV. 0 AD6600 1 TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS; TMIN = –40C, TMAX = +85C unless otherwise noted.) Parameter A/D CONVERTER Conversion Rate Maximum Conversion Rate Minimum Conversion Rate Aperture Uncertainty ENCODE INPUTS (ENC, ENC)2 Period Pulsewidth High3 Pulsewidth Low4 2× CLOCK OUTPUT (CLK2×)5 Output Frequency Output Period6 CLK2× Pulsewidth Low6 Output Risetime7 Output Falltime7 OUTPUT RISE/FALL TIMES8 Output Risetime (D10:D0, RSSI2:0) Output Falltime (D10:D0, RSSI2:0) Output Risetime (AB_OUT) Output Falltime (AB_OUT) Temp Test Level II IV V 20 tj Full Full 25°C tENC tENCH tENCL Full Full Full II IV IV 50 20 20 tCLK2×_1 tCLK2×_2 tCLK2×L Full Full Full Full Full V V V V V 2× fENC tENCL tENCH tENCH/2 3 2.6 MSPS ns ns ns ns ns Full Full Full Full V V V V 8 8.4 6 6.2 ns ns ns ns Name Min AD6600AST Typ Max 1/(tENC) fENC 6 0.3 Unit MSPS MSPS MSPS ps rms ns ns ns NOTES 1 See AD6600 Timing Diagrams. 2 All switching specifications tested by driving ENC and ENC differentially. 3 Several timing specifications are a function of Encode high time, t ENCH; these specifications are shown in the data tables and timing diagrams. Encode duty cycle should be kept as close to 50% as possible. 4 Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details. 5 The 2× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2 × are referenced to 2.0 V crossing. 6 This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8. 7 Output rise time is measured from 20% point to 80% point of total CLK2 × voltage swing; output fall time is measured from 80% point to 20% point of total CLK2 × voltage swing. 8 Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage swing. All outputs specified with 10 pF load. Specifications subject to change without notice. REV. 0 –3– AD6600–SPECIFICATIONS TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1, 2 (AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40C, TMAX = +85C unless otherwise noted.) Parameter ENCODE/CLK2× Encode Rising to CLK2× Falling3 Encode Rising to CLK2× Rising4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle CLK2×/DATA (D10:0, RSSI2:0)5 CLK2× to DATA Rising Low Delay3 CLK2× to DATA Hold Time3 CLK2× to DATA Falling Low3, 6 CLK2× to DATA Setup Time4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle6 CLK2×/AB_OUT5 CLK2× to AB_OUT Rising Low Delay3 CLK2× to AB_OUT Hold Time3 CLK2× to AB_OUT Falling Low Delay3, 6 CLK2× to AB_OUT Setup Time4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle6 ENCODE/DATA (D10:0, RSSI2:0) ENCODE to DATA Rising Low Delay4 ENCODE to DATA Hold Time4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle ENCODE to DATA Falling Low Delay4 ENCODE to DATA Delay (Setup)4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle6 ENCODE/AB_OUT ENCODE to AB_OUT Rising Low Delay4 ENCODE to AB_OUT Delay (Hold)4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle ENCODE to AB_OUT Falling Low Delay4 ENCODE to AB_OUT Delay (Setup)4 @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle6 Name Temp Test Level tCF tCR Full Full Full Full IV IV IV IV 6.5 Full Full 25°C Full Full Full 25°C Full IV IV IV IV IV IV IV IV 3.0 3.0 10.0 11.0 Full Full 25°C Full Full Full 25°C Full IV IV IV IV IV IV IV IV 7.0 7.0 12.0 10.7 Full Full Full Full Full Full Full 25°C Full IV IV IV IV IV IV IV IV IV Full Full Full Full Full Full Full 25°C Full IV IV IV IV IV IV IV IV IV t2×_DRL tH_D2× t2×_DFL tS_D2× t2×_ARL tH_A2× t2×_AFL tS_A2× tEN_DRL tH_DEN tEN_DFL tS_DEN tEN_ARL tH_AEN tEN_AFL tS_AEN Min 25.7 19.0 16.5 5.0 3.0 12.5 2.0 –1.0 28.7 22.0 26.2 8.0 6.0 32.7 26.0 22.2 5.0 2.0 AD6600AST Typ 8.0 tCF + (tENCH)/2 27.2 20.5 6.5 6.5 15.0 15.5 tENCH – t2×_DFL 23.0 10.0 9.5 11.0 11.0 18.0 19.0 tENCH – t2×_AFL 19.5 7.0 6.0 Max Unit 9.5 ns ns ns ns 28.7 22.0 20.0 22.0 23.0 26.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCR + t2×_DRL tEN_DRL 33.7 27.0 tCR + t2×_DFL tENC – tEN_DFL 34.2 14.5 14.0 ns ns ns ns ns ns ns ns ns tCR + t2×_ARL tEN_ARL 38.2 31.5 tCR + t2×_AFL tENC – tEN_AFL 30.7 11.5 10.5 ns ns ns ns ns ns ns ns ns NOTES 1 See AD6600 Timing Diagrams. 2 All switching specifications tested by driving ENC and ENC differentially. 3 This specification IS NOT a function of Encode period and duty cycle. 4 This specification IS a function of Encode period and duty cycle. 5 CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load. 6 For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and covers the entire range, –40°C to +85°C. Specifications subject to change without notice. –4– REV. 0 AD6600 AC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40C, TMAX = +85C unless otherwise noted.) Parameter Temp Test Level Full V 450 MHz Full Full Full Full V V V V 2.45 2.57 2.62 2.86 V p-p V p-p V p-p V p-p 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C V V V V V V V V 197–j24 188–j48 175–j57 161–j67 151–j73 140–j80 141–j75 173–j107 Ω Ω Ω Ω Ω Ω Ω Ω Full Full Full Full V V V V 5.8 6.3 6.7 7.7 dBm dBm dBm dBm Full 25°C V I –1.0 25°C I –1.5 Full Full V II –0.5 Full V ± 0.1 dB Full Full V V 0.2 0.5 Degree Degree Full IV 50 dB Full Full Full V V V 34 869 +33 µV rms µV rms dBm 25°C 25°C 25°C 25°C 25°C IV V IV IV IV 59 54.5 49 48 ± 6 34 dB dB dB dB dB 25°C 25°C 25°C 25°C 25°C IV V IV IV IV 58 54 49 48 ± 6 34 dB dB dB dB dB Min AD6600AST Typ Max Unit 1 ANALOG INPUTS Analog Input 3 dB Bandwidth2 Differential Analog Input Voltage Range 70 MHz 150 MHz 200 MHz 250 MHz Differential Analog Input Impedance3 70 MHz 150 MHz 200 MHz 250 MHz 300 MHz 350 MHz 400 MHz 450 MHz Full-Scale Input Power 70 MHz 150 MHz 200 MHz 250 MHz Full-Scale Gain Tolerance4 70 MHz–250 MHz 200 MHz5 Gain Error AIN = 200 MHz @ –76 dBFS Gain Matching (Input A:B) 70 MHz–250 MHz 200 MHz Range-to-Range Gain Tolerance 70 MHz–250 MHz Range-to-Range Phase Tolerance 70 MHz 250 MHz Channel Isolation6 70 MHz–250 MHz Noise7 Minimum Attenuation Level Maximum Attenuation Level Attenuator 3OIP8 Signal-to-Noise Ratio (SNR)9, 10, 11 AIN = 70 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS AIN = 150 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS REV. 0 –5– 45 55 45 41 31 55 45 41 31 ± 0.5 ± 0.1 ± 0.1 ± 0.05 +1.0 dB dB +1.5 dB +0.5 dB dB AD6600–SPECIFICATIONS AC SPECIFICATIONS (continued) Parameter ANALOG INPUTS (Continued) Signal-to-Noise Ratio (Continued) AIN = 200 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS AIN = 250 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS SECOND HARMONIC AIN = 70 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 150 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 200 MHz9, 10, 11 @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS AIN = 250 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS THIRD HARMONIC AIN = 70 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 150 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 200 MHz9, 10, 11 @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS AIN = 250 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 70 MHz–250 MHz @ –75 dBFS Temp Test Level 25°C 25°C 25°C 25°C 25°C I V I I I 25°C 25°C 25°C 25°C 25°C IV V IV IV IV Full Full Full Min Max Unit 57.5 53.5 49 48 ± 6 34 dB dB dB dB dB 56 53.5 49 48 ± 6 34 dB dB dB dB dB V V V 69 68 68 ± 6 dBc dBc dBc Full Full Full V V V 60 59 67 ± 6 dBc dBc dBc 25°C Full 25°C Full Full I V I V V 60 56 55 65 ± 6 50 dBc dBc dBc dBc dBc Full Full Full V V V 54 62 65 ± 6 dBc dBc dBc Full Full Full V V V 77 76 67 ± 6 dBc dBc dBc Full Full Full V V V 65 70 66 ± 6 dBc dBc dBc 25°C Full 25°C Full Full I V I V V 55 58 66 65 ± 6 62 dBc dBc dBc dBc dBc Full Full Full V V V 50 56 65 ± 6 dBc dBc dBc Full IV 35 dBc –6– 55 AD6600AST Typ 45 40.5 31 52 43 40 30 50 48 50 55 28 REV. 0 AD6600 AC SPECIFICATIONS (continued) Parameter WORST OTHER SPUR (4th or Higher) AIN = 70 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 150 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 200 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS AIN = 250 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS Temp Test Level Full Full Full V V V 74.5 71 68 ± 6 dBc dBc dBc Full Full Full V V V 67 65 67 ± 6 dBc dBc dBc 25°C Full 25°C Full I V I V 67 66 66 65 ± 6 dBc dBc dBc dBc Full Full Full V V V 66.5 65 65 ± 6 dBc dBc dBc Min 60 55 AD6600AST Typ Max Unit NOTES 1 AIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 MHz–250 MHz specified operating range. Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results. 2 Analog Input 3 dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1 GHz. 3 Measured real and imaginary values using Network Analyzer. 4 Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for full-scale input power is a function of frequency as shown in previous specification. 5 Full-scale gain tolerance measured at 200 MHz analog input referenced to 6.7 dBm nominal full-scale input power. For the gain measurement test, the input signal level is set to –6 dBFS. Tuning port bandwidth is set to 50 MHz. 6 Main channel set to full-scale input power. Diversity channel swept from –20 dBFS to –90 dBFS. 7 Measurement includes thermal and quantization noise at 70 MHz analog input. Tuning port bandwidth is set to 50 MHz. 8 Test tones at 160.05 MHz and 170.05 MHz. 9 Measurements at –1 dFBS, –6 dBFS, and –10 dBFS are in highest attenuation mode, RSSI = 101. 10 Each gain-range is checked at ~3 dB from RSSI trip point (not in hysteresis); nominally –16 dBFS (RSSI = 100), –22 dBFS (RSSI = 011), –28 dBFS (RSSI = 010), –35 dBFS (RSSI = 001). 11 Measurement at –54 dBFS is in the lowest attenuation mode, RSSI = 000. Specifications subject to change without notice. REV. 0 –7– AD6600 ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage2 Analog Input Current2 Digital Input Voltage3 Output Current4 Resonant Port Voltage5 Min Max Unit 0 0 0 V V V mA V mA V 0 0 7 7 AVCC 25 AVCC 4 AVCC EXPLANATION OF TEST LEVELS Test Level I. 100% Production Tested. II. 100% Production Tested at 25°C and guaranteed by design and characterization at temperature extremes. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. ORDERING GUIDE 6 ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) –40 +85 150 300 –65 +150 Model °C °C °C °C AD6600AST Temperature Package Range Description –40°C to +85°C (Ambient) AD6600ST/PCB NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Pins AIN, AIN, BIN, BIN. 3 Pins ENC, ENC, A_SEL, B_SEL. 4 Pins D10:0, RSSI2:0, AB_OUT, CLK2×. 5 Pins FLT, FLT. 6 Typical thermal impedance (44-lead LQFP); θJC = 16°C/W, θJA = 55°C/W. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –8– Package Option 44-Terminal LQFP ST-44 (Low-Profile Quad Plastic Flatpack) Evaluation Board with AD6600AST WARNING! ESD SENSITIVE DEVICE REV. 0 AD6600 PIN FUNCTION DESCRIPTIONS Pin Number Name Function 1, 33 2, 5, 13, 19, 21, 24, 30, 32 3 4, 14, 15, 18, 20, 25, 31 6–8 9, 10 11 12 16, 17 22 23 26 27 28 29 34 35–43 44 DVCC GND C1 AVCC RSSI[2:0] B_SEL, A_SEL AIN AIN FLT, FLT BIN BIN ENC ENC CLK2× AB_OUT D0 D1–D9 D10 Digital VCC for Digital Outputs. Can be 3.3 V. Ground. Internal Bias Point. Bypass by 0.01 µF to GND. 5 V Power Supply. RSSI Digital Output Bits. Mode Select Pins for Analog Input Channel A and B Sampling. True Analog Input Channel A. Complementary Analog Input Channel A. Resonant Filter Pins for External LC Noise Filter. Complementary Analog Input Channel B. True Analog Input Channel B. Complementary Encode Input. True Encode Input. 2× Clock Output Used for Clocking Digital Filter Chips. Digital Output Flag Indicating Whether Output Is Input A (High) or B (Low). Digital Data Output Bit (Least Significant Bit)*. Digital Data Output Bits*. Digital Data Output Bit (Most Significant Bit)*. *Digital Outputs (D10:D0) in Two’s Complement Format. D1 D0 (LSB) D2 D4 D3 D6 D5 D8 D7 D10 (MSB) D9 PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 33 DVCC DVCC 1 GND 2 PIN 1 IDENTIFIER 32 GND 31 AVCC C1 3 AVCC 4 30 GND GND 5 29 AB_OUT AD6600 RSSI2 6 28 CLK2 TOP VIEW (Not to Scale) RSSI1 7 27 ENC 26 ENC RSSI0 8 B_SEL 9 25 AVCC A_SEL 10 24 GND AIN 11 23 BIN –9– BIN GND AVCC GND AVCC FLT FLT AVCC AVCC AIN REV. 0 GND 12 13 14 15 16 17 18 19 20 21 22 AD6600 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Full-Scale Gain Tolerance Unit-to-unit variation in full-scale input power. The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. The bandwidth is determined by the internal track-and-hold when the filter node is resonated. Full-Scale Input Power Expressed in dBm. Computed using the following equation: Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog inputis sampled. PowerFULL SCALE Aperture Uncertainty (Jitter) V 2FULL SCALE rms Z INPUT = 10 log 0.001 Gain Matching (Input A:B) The sample-to-sample variation in aperture delay. Variation in full-scale power between A and B inputs. Attenuator 3OIP The third order intercept point of the front end of the AD6600. It is the point at which the third order products would theoretically intercept the input signal level if the input level could increase without bounds. This is measured using the ADC within the AD6600 while the input is stimulated with dual tones in the minimum attenuation (i.e., maximum gain) range. Harmonic Distortion, 2nd Channel Isolation Integral Nonlinearity The amount of signal leakage from one channel to the next when one channel is driven with a full-scale input, and the other channel is swept from –20 dBFS to –90 dBFS with a frequency offset. The leakage is measured on the side with the smaller signal. The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Maximum Conversion Rate The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, 3rd The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Minimum Conversion Rate The encode rate at which parametric testing is performed. Noise (For Any Range Within the ADC) Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. VNOISE = Z × 0.001 × 10 where: Z FS SNR Signal Differential Nonlinearity FS dBm −SNR dBc −Signal dBFS 10 is the input impedance, is the full-scale of the device for the frequency in question, is the value for the particular input level, is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. The deviation of any code width from an ideal 1 LSB step. Range-Range Gain Tolerance Differential Resonant Port Resistance The gain error in the RSSI attenuator ladder from one range to the next. The resistance shunted across the resonant port (nominally 630 Ω). Used to determine the filter bandwidth and gain of that stage. Range-Range Phase Tolerance The phase error in the RSSI attenuator ladder from one range to the next. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specifications define an acceptable Encode duty cycle. Differential Resonant Port Capacitance The capacitance between the two resonant pins. Used to determine filter bandwidth and resonant frequency. –10– REV. 0 AD6600 RSSI Gain Step AD6600 TRANSFER FUNCTION The input amplitude span between taps of the RSSI (received signal strength) attenuator ladder. Ideally each stage should span 6 dB of input power. 60 54 RSSI Hysteresis Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. 48 42 SNR – dB The amount of movement in the RSSI switch points, depending on the direction of approach. Hysteresis prevents unnecessary RSSI toggling when input signal power is near a threshold. 36 30 24 18 12 Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. 6 0 –100 –90 –80 –70 –60 –50 –40 –30 AIN LEVEL – dBFS –20 Figure 1. SNR vs. Input Power REV. 0 –11– –10 0 AD6600 EQUIVALENT CIRCUITS AVCC EXTERNAL LC FILTER AVCC AVCC FLT FLT ATTENUATOR STAGE AVCC GND EQUIVALENT INPUT R SHOWN ONLY 315 315 GND AIN 4/8 GAIN STAGE 100 VREF GND BUF BUF FROM GAIN STAGE GAIN AVCC TO T/H 100 AIN GND GND Figure 2. Analog Input Stage (Channel A Shown; Channel B Is Equivalent) Figure 5. Resonant (LC Noise Filter) Port AVCC AVCC ISEL_A AVCC ISEL_B AVCC A_SEL R1 AVCC 17k 1/2 AVCC R1 17k 1/2 B_SEL ENCODE ENCODE R2 8k 1/2 BIAS GND GND R2 8k 1/2 TIMING CIRCUITS GND Figure 3. A_SEL, B_SEL Input Mode Pins Figure 6. Encode Inputs DVCC DVCC CURRENT MIRROR CURRENT MIRROR DVCC VREF 500 DVCC VREF CLK2 AB_OUT D10–D0 RSSI [2:0] CURRENT MIRROR CURRENT MIRROR Figure 7. CLK2⫻, AB_OUT Outputs Figure 4. Digital Outputs –12– REV. 0 AD6600 AD6600 TIMING DIAGRAMS tENCH tENCL tENC ENCODE tCF1 CLK2 tCR1 tCLK2L CLK22 tCF2 tCR2 tCLK2L tCLK22 tCLK2H2 CLK21 CLK22 tCLK21 tCLK2H1 CLK21 CLK22 t21_DFL t21_DRL D [10:0] RSSI [2:0] t21_AFL t21_ARL AB_OUT Figure 8. Encode to CLK2⫻ Delays and CLK2⫻ Propagation Delays tENCH tENCL tENC ENCODE tCF1 CLK2 tCR1 tCLK2L CLK22 tCF2 tCR2 tCLK2L tCLK22 tCLK2H2 CLK21 tH_D2 CLK22 tS_D2 tCLK21 tCLK2H1 CLK21 tH_D2 CLK22 tS_D2 D [10:0] RSSI [2:0] tH_A2 tS_A2 tH_A2 tS_A2 AB_OUT Figure 9. CLK2⫻ Setup-and-Hold Time Characteristics tENCH ENCODE tENC ENCODE tCF1 CLK2 tENCL ENCODE tCR1 tCLK2L CLK22 tCF2 CLK21 tCR2 tCLK2L ENCODE tCLK22 tCLK2H2 CLK22 tEN_DFL tEN_DRL tCLK21 tCLK2H1 CLK21 tEN_AFL D [10:0] RSSI [2:0] tEN_ARL AB_OUT Figure 10. Encode to CLK2⫻ Delays and Encode Propagation Delays REV. 0 –13– CLK22 AD6600 tENCH ENCODE tENC ENCODE tCF1 CLK2 tENCL ENCODE tCR1 tCLK2L CLK22 tCR2 tCLK2L tCF2 ENCODE tCLK22 tCLK2H2 CLK21 tCLK21 tCLK2H1 CLK22 tH_DEN CLK21 tS_DEN CLK22 tH_DEN tS_DEN D [10:0] RSSI [2:0] tH_AEN tS_AEN tH_AEN tS_AEN AB_OUT Figure 11. Encode Setup-and-Hold Time Characteristics 3 2.6 CLK2 8 8.4 D [10:0] RSSI [2:0] 6.2 6 AB_OUT Figure 12. Typical Output Rise and Fall Times 20 ENCODE 30 50 40% 18 18 8 30 20 8 CLK2 Figure 13. Encode = 20 MSPS, Duty Cycle = 40% 30 ENCODE 20 50 60% 23 8 23 20 30 8 CLK2 Figure 14. Encode = 20 MSPS, Duty Cycle = 60% –14– REV. 0 AD6600 NOISE FILTER FLT FLT 0dB, –12dB, –24dB RESONANT PORT 630 AIN ATTEN AIN DETECT PEAK 3 SET RSSI RSSI GAIN ANALOG MUX AB_OUT GAIN ENCODE +12, +18dB A/D CONVERTER GAIN TWO'S COMPLEMENT D10–D0 11 3 RSSI SELECT GAIN RSSI [2:0] ENCODE BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL B_SEL GND AVCC CLK2 TIMING AD6600 ENC ENC DVCC Figure 15. Functional Block Diagram THEORY OF OPERATION 0 It is helpful to view this device as a stand-alone ADC using automatic gain control. The gain control referred to in this data sheet as “gain-ranging” works to maintain a constant SNR over as wide a range as possible. 001 000 000 –90 0 4 8 –12 –18 –24 –30 –36 –42 –48 –54 –60 –66 –72 –78 –84 –90 –96 12 16 20 24 28 32 36 40 44 48 52 56 60 SNR – dB 12dB SNR WINDOW Figure 16. SNR for Gain-Ranging ADC AD6600 SUBCIRCUITS Input Step Attenuator and Gain Stage The AD6600 has two identical input attenuators, Channel A and Channel B. These dual inputs are typically used as diversity channels but may also process two independent IF signals. For maximum oversampling the device is used in single channel mode; in this case only one input channel is required. The attenuator steps are 0 dB, –12 dB and –24 dB. The attenuator settings are based on the decisions of the RSSI stage (see Peak Detector/ RSSI section). The outputs of the attenuators connect to an analog multiplexer that selects either Channel A or B for subsequent processing (see Input Mode). The selected signal drives a dual-gain amplifier set to either 12 dB or 18 dB; the selected gain is also determined by the RSSI stage. Therefore, based on all possible combinations of attenuation and gain, the input signal receives –12 dB to +18 dB of voltage gain in 6 dB steps (Table I). Overall gain-matching is typically within 0.1 dB. With a bandwidth of 1 GHz, the phase delay through the front-end ranges from 0.2 degrees to 0.5 degrees, depending on input frequency. Additionally, the input impedance does not change with attenuator settings so there is no AM-to-PM distortion. –15– As stated previously, the AD6600 has a floating-point output: eleven mantissa bits and three exponent bits. As shown in Figure 16, at the lowest input levels SNR increases 1 dB for a 1 dB increase in input power. In this range, the AD6600 is set for maximum gain. However, when the input signal level reaches the gain-ranging section (approximately –42 dBFS), the SNR is contained between about 50 dB and 56 dB or between 44 dB and 56 dB including the effects of hysteresis. Although Figure 16 does not indicate so, there are slight differences between the SNR from one gain range to the next as the gain amp switches between 12 dB and 18 dB. Once the final RSSI range has been exceeded (approximately –12 dBFS), SNR again increases 1 dB per 1 dB input power increase until converter full scale is reached. Again, this performance is very much like the effects of a typical analog AGC loop. REV. 0 101 100 011 010 001 101 100 011 010 AIN – dBFS The AD6600, dual-channel, gain-ranging ADC integrates analog IF circuitry with high speed data conversion. Each analog input stage is a 1 GHz, 0 dB to –24 dB, phase-compensated step attenuator; the step size in each attenuator is 12 dB. Both input stages drive an analog multiplex function followed by a 12 dB/ 18 dB gain amplifier. A simple LC noise filter at the output of the gain amplifier is required to resonate at the desired IF. This resonant filter port precedes a wide input bandwidth (450 MHz) track-and-hold followed by an 11-bit analog-to-digital converter (ADC). A high speed synchronous peak detector monitors signal strength at both input channels. The peak detector drives RSSI circuitry that automatically adjusts attenuation and gain on a clock-by-clock basis. The three RSSI indicator bits and the eleven ADC bits are available at the output providing an exponent and mantissa data format. Together these integrated components form an IF sampling, high dynamic range ADC system. AD6600 Table I. Attenuator and Gain Settings ADC Encoder Attenuator Gain Amp Total RSSI Word 0 dB 0 dB –12 dB –12 dB –24 dB –24 dB +18 dB +12 dB +18 dB +12 dB +18 dB +12 dB +18 dB +12 dB +6 dB 0 dB –6 dB –12 dB 000 001 010 011 100 101 After the calibration period is complete (one clock cycle), the appropriate gain and attenuator settings are determined and set. Once settled, the internal track-and-hold freezes the input signal so that the ADC encoder may digitize the signal. During digitization, the peak detector/RSSI circuitry is already looking at the next sample. When the AD6600 is in dual channel mode, the process is interleaved: while Channel B is monitored for signal strength, Channel A is digitized. This allows the RSSI to update on a clock-by-clock basis. High-Speed Peak Detector and RSSI Circuitry The peak detector along with the attenuator and dual gain amplifier form the control loop within the AD6600. DIGITIZE OLD DATA T-AND-H HOLD ENCODE The peak detector is designed to follow the analog input one clock cycle before the conversion is actually made. Therefore, while the converter section of the AD6600 is converting sample “n,” the peak detector is already looking at sample “n+1.” While looking at the “n+1” sample (the calibration period), the peak detector examines the envelope of the input signal. The more of an envelope that is tracked, the more accurate the gain setting. At the very least, the peak detector must be presented either a positive or negative sinusoidal peak, which represents about one-half of a sine wave cycle. Since the peak detector works for a complete cycle prior to conversion, the absolute minimum IF frequency that can be determined is twice the sample rate per channel. Therefore, at 15 MSPS, the minimum IF frequency that can be sampled would be 30 MHz. Note that the more cycles of the input that are monitored by the peak detector, the more accurate the gain setting will be. Therefore, the actual minimum IF frequency recommended is higher than this. The minimum specified frequency is 70 MHz. Since the RSSI control loop is performed on a sample-by-sample basis, the AD6600 very accurately follows the signals into and out of a deep fade. Hysteresis The AD6600 employs hysteresis to prevent the gain-ranging from unnecessarily changing when the signal envelope is near an RSSI threshold. The hysteresis is digital and will account for exactly 6 dB of shift, depending on whether the signal is increasing or decreasing. This effect is shown in the dashed lines of the overall transfer function, Figure 16. External LC Noise Filter, Resonant Port The output of the attenuator/gain stage drives the wide bandwidth track-and-hold (T/H), followed by the ADC encoder. Because the attenuator/gain stage has a very wide bandwidth (~1 GHz), an LC filter or “resonant port” is provided to limit the amount of wideband noise delivered to the ADC. The simple LC filter does not provide signal selectivity and should typically be 35 MHz to 50 MHz wide. However, because the ADC’s track-and-hold itself has a wide bandwidth (~450 MHz), this noise-limiting filter is critical to meeting overall sensitivity. Specific details on selecting components for the resonant port are provided later in the text (Understanding the External Analog Filter). T-AND-H TRACK ADC DIGITIZE T-AND-H HOLD IF INPUT INTERNAL 2 CLOCK RSSI CAL. RSSI CALIBRATION RSSI SET NOISE FILTER DISCHARGE AMPLIFIER CONTROL NOISE FILTER SETTLING 4/8 AMP T/H INPUT CLAMPED NOISE FILTER SETTLING Figure 17. Internal Timing Figure 17 shows the internal timing of the chip. The encode applied to the device initiates several actions. The first and most important is that the track-and-hold is placed in hold, thus sampling the analog input at that instant. The second action is that the peak detector of the RSSI circuitry is initialized. During this period, the analog input envelope is monitored to determine signal power. The AD6600 is in calibration mode for about onequarter of the encode period. While the AD6600 is in calibration, the external noise filter is discharged and the amplifier driving the filter disabled. Since this filter is shared between the two input channels in dual channel mode, this greatly reduces the feedthrough between the channels that would otherwise exist. One-quarter of an encode period after the calibration is complete, the amplifier is re-enabled and allowed to settle to its new signal conditions for sampling by the wideband T/H on the next encode signal. The final action is that the signal on the resonant port is sampled by the track-and-hold. This happens on the next rising edge of the encode. Input Mode Select The AD6600 has two operating modes: single channel and dual channel. In single channel mode, the ADC always samples Channel A or always samples Channel B. In dual channel mode, the ADC converter is sampling Channel A and Channel B on alternating Encode cycles. Two control pins are provided to select the desired mode of operation. A_SEL and B_SEL arbitrate the selection of how these input channels are connected to the output. Table II shows the truth table for selection of the input. –16– REV. 0 AD6600 Table II. Selecting AD6600 Operating Mode Table V. 16-Bit, Fixed-Point Data Format Mode A_SEL B_SEL Output vs. Encode Clock n n+1 n+2 n+3 Dual: A/B Single: A Single: B Not Valid 1 1 0 0 1 0 1 0 A A B – B A B – A A B – B A B – A_SEL and B_SEL are not logic inputs and should be tied directly to ground or analog VCC (5 V analog). A_SEL and B_SEL = 1 Output Data vs. Encode Clock n n+1 n+2 n+3 D[10:0], RSSI[2:0] AB_OUT A 1 B 0 Data Output Stage The output stage provides data in the form of mantissa, D[10:0], and exponent, RSSI[2:0], where D[10:0] represents the output of the 11-bit ADC coded as two’s complement, and RSSI[2:0] represents the gain-range setting coded in offset binary. Table IV shows the nominal gain-ranges for a nominal 2 V p-p differential full-scale input. Keep in mind that the actual full-scale input voltage and power will vary with input frequency. Table IV. Interpreting the RSSI Bits Differential Analog Input Voltage (V p-p) RSSI [2:0] Decimal Binary Equiv. Attenuation or Gain (dB) 0.5 < VIN 0.25 < VIN < 0.5 0.125 < VIN < 0.25 0.0625 < VIN < 0.125 0.03125 < VIN < 0.0625 VIN < 0.03125 101 100 011 010 001 000 –12 –6 0 +6 +12 +18 5 4 3 2 1 0 16-Bit Data Format Corresponds to a Shift Right of 101 100 011 010 001 000 DATA DATA DATA DATA DATA DATA DATA× 32 DATA× 16 DATA× 8 DATA× 4 DATA× 2 DATA× 1 5 4 3 2 1 0 APPLYING THE AD6600 Encoding the AD6600 Table III. AB_OUT for Dual Channel Operation A 1 11-Bit Word When mated with the AD6620, Digital Receive Processor Chip, the AD6600 floating point data (mantissa + exponent) is automatically converted to 16-bit two’s complement format by the AD6620. In dual channel mode, the AB_OUT signal indicates which input is currently available on the digital output. When the AB_OUT is 1, the digital output is the digitized version of Channel A. Likewise, when AB_OUT is 0, the Channel B is available on the digital output (Table III). B 0 RSSI The AD6600 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Digitizing high frequency signals (IF range 70 MHz–250 MHz) places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB–4 dB with 70 MHz input signals when using a high-jitter clock source. At higher IFs (up to 250 MHz), and with high-jitter clock sources, the higher slew rates of the input signals reduce performance even further. See AN-501, Aperture Uncertainty and ADC System Performance for complete details. For optimum performance, the AD6600 must be clocked differentially. The encode signal is usually ac-coupled into the ENC and ENC pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 18 shows one preferred method for clocking the AD6600. The sine source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6600 to approximately 0.8 V p-p differential. This helps prevent the larger voltage swings of the clock from feeding through to other portions of the AD6600, and limits the noise presented to the encode inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary. SINE SOURCE The digital processing chip which follows the AD6600 can combine the 11 bits of two’s complement data with the 3 RSSI bits to form a 16-bit equivalent output word. Table V explains how the RSSI data can be interpreted when using a PLD or ASIC. Basically, the circuit performs right shifts of the data depending on the RSSI word. This can also be performed in software using the following pseudo code fragment: r0 = dm (rssi); r2 = 5; r0 = r2–r0; r1 = dm (adc); (11 bits, MSB justified into DSP word) rshift r1, r0; (arithmetic shift to extend the sign bit) The result of the shifted data is a 16-bit fixed-point word that can be used as any normal 16-bit word. REV. 0 –17– T1–1T 100 ENCODE AD6600 ENCODE 5082–2810 DIODES Figure 18. Transformer-Coupled Sine Source AD6600 If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 19. When general purpose gain blocks are used, matching can easily be achieved using a transformer. Most gain blocks are available with 50 Ω input and output ports. Thus matching to the 200 Ω impedance of the AD6600 requires only a 1:4 (impedance ratio) transformer as shown in Figure 21. VT 0.1F FROM MIXER OUTPUT ENCODE ECL/ PECL 0.1F AD6600 ENCODE 50 GAIN BLOCK AD6600 ADC Figure 21. Transformer-Coupled Gain Block VT Figure 19. AC-Coupled ECL/PECL Encode Driving the Analog Inputs As with most new high-speed, high dynamic range analog-to-digital converters, the analog input to the AD6600 is differential. Differential inputs allow much improvement in performance on-chip as IF signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection to stray signals such as ground and power noise. They also provide good rejection to common-mode signals such as local oscillator feedthrough. Driving a differential analog input introduces some new challenges. Most RF/IF amplifiers are single-ended and may not obviously interface to the AD6600. However, using simple techniques, a clean interface is possible. The recommended method to drive the analog input port is shown in Figure 20. The AD6600 input is actually designed to match easily to a SAW filter such as SAWTEK 855297. This allows the SAW filter to be used in a differential mode, which often improves the operations of a SAW filter. Using network analyzer data for both the SAW filter output and the AD6600 input ports (see data tables for AD6600 S11 data), a conjugate match can be used for maximum power transfer. Often an adequate match can be achieved simply by using a shunt inductor to make the port look real (Figure 20). For more details on how to exactly match networks, see RF Circuit Design by Chris Bowick, ISBN: 0-672-21868-2. FROM MIXER OUTPUT SAW #1 AD6630 SAW #2 AD6600 ADC Figure 20. Cascaded SAW Filters with AD6630 Where gain is required, the AD6630 differential, low noise, IF gain block is recommended. This amplifier provides 24 dB of gain and provides limiting to prevent damage to the SAW filter and AD6600. The AD6630 is designed to reside between two SAW filters. This low noise device is ideally suited to many applications of the AD6600. For more information on the AD6630, reference the AD6630 data sheet. In the rare case that better matching is required, a conjugate match between the amplifier selected and the transformercoupled analog input can be achieved by placing the matching network between the amplifier and the transformer (Figure 22). For more details on matching, see the reference mentioned previously for more details. FROM MIXER OUTPUT MATCHING NETWORK 50 GAIN BLOCK AD6600 ADC Figure 22. Gain Block and Matching Network Understanding the External Analog Filter Two primary trade-offs must be made when designing the external resonant filter. The obvious one is the bandwidth of the filter. The second, not so obvious, trade-off is settling time of the filter nodes. Resonant Filter Bandwidth determines the amount of noise that is limited at the center frequency chosen. If the resonant filter is too wide, little noise improvement is seen. If the resonant filter is too narrow, amplitude variation can be seen due to the tolerance of filter components. If the narrow filter is off center due to these tolerances (or drift), the 4×/8× signal will fall on the transition band of the filter. An optimum starting point for this filter is approximately 50 MHz. Resonant Filter Settling limits the amount of capacitance of this filter. The output of the 4×/8× amplifier is clamped when the ADC is processing its input (encode high time). This prevents the amp output from feeding through to the ADC (T/H) and corrupting the ADC results. But, upon the falling edge of encode, the amp must now come out of clamp and present an accurate signal to the ADC T/H. The RC of the external filter determines the settling of the amp. If the amp output does not settle, the ADC sees an attenuated signal. So obviously, a narrow bandwidth is desired to improve noise performance; but if the filter is too narrow, the amp will not settle and the ADC will see an attenuated signal. Figure 23 shows a simplified model of the 4×/8× amplifier. A key point to note is that the resistor values in the collector legs are 315 Ω nominal with a tolerance of ± 20%. The filter performance is determined by these values in conjunction with the internal parasitic capacitance, board parasitics and the external filter components. –18– REV. 0 AD6600 So for settling purposes, with 13 MSPS encode and 50% duty cycle, the maximum allowable capacitance for proper settling is CTOTAL = 13.6 pF. AVCC 315 RESONANT FILTER PORT 315 As stated above, this CTOTAL includes the external capacitors, the board parasitics, and the AD6600 parasitics. The parasitics of the AD6600 (lead, internal bond pad and internal connections) at FLT and FLT are 1.75 pF ± 0.35 pF (differential). FLT FLT FROM GAIN STAGE If the resistors are at maximum value (315 + 20%), the maximum allowable capacitance is CTOTAL = 11.3 pF. If the duty cycle is less than 50%, the maximum allowable capacitance is further decreased to allow for settling. CLAMP Power Supplies ENCODE GND Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD6600. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors. Figure 23. 4 ×/8 × Amplifier Clamp Circuitry Figure 24 shows why settling is important for this circuit. If the 4×/8× amp does not settle (come out of clamp), the amplitude presented to the ADC will be decreased. This results in decreased gain when the filter capacitance is too high. ENCODE RESONANT FILTER HOLD TRACK CLAMPED HOLD SETTLING Figure 24. 4 ×/8 × Amplifier Settling This explains why the total capacitance allowed for the external filter varies depending on the clock rate (actually encode clock high time). If the encode is 13 MSPS and the duty cycle is 50%, the allowable settling time is 38.5 ns (1/2 of the encode time). Our assumption is that the amp should be allowed to settle to 1/4 LSB in this time period. This has been proven with both simulation and empirical analysis. If the settling is assumed to be an RC circuit, then: T = RC; t = time; n = number of bits ( ) = A (1 − e ) VO = A 1 − e t /T A− A/2 n 1− t /T 1 = 1 − e t /T 2n 1 = e t /T 2n 1 t = l n n 2 T T= CTOTAL = t ( ) l n 2n (TENCODE × 0.5) = 38.5 ns = 13.6 pF R × l n (8192) 315 Ω × l n (8192) In this case, CTOTAL includes all parasitics and external capacitance. R is nominally 315 Ω. The 8192 is (4 × 2048), which is 1/4 LSB of the converter (11 bits, 2048). REV. 0 The AD6600 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 Volts; however, the DVCC supply may be varied according to output digital logic family. The AD6600 is specified for DVCC = 3.3 V as this is a common supply for digital ASICS. Output Loading Care must be taken when designing the data receivers for the AD6600. Note from the equivalent circuits shown earlier (see Equivalent Circuits) that D[10:0] and RSSI[2:0] contain a 500 Ω output series resistor. To minimize capacitive loading, there should only be one gate on each output pin. Extra capacitive loading will increase output timing and invalidate timing specifications. CLK2× and AB_OUT do not contain the output series resistors. Testing for digital output timing is performed with 10 pF loads. Layout Information The schematic of the evaluation board (Figure 25) represents a typical implementation of the AD6600. A multilayer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6600 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6600, minimal capacitive loading should be placed on these outputs. It is recommended that a fanout of only one be used for all AD6600 digital outputs. The layout of the analog inputs and the external resonant filter are critical. No digital traces must be routed near, under, or above these portions of the circuit. The transformers used for coupling into the analog inputs must be located as close as possible to the analog inputs of the AD6600. The external resonant filter components must be physically close to the filterinput pins, yet separated from the analog inputs. –19– AD6600 The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs. Evaluation Board The evaluation board for the AD6600 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock and the analog inputs. The evaluation board includes the option for an on-board, clock oscillator for encode. Power to the analog supply pins of the AD6600 is connected via the power terminal block (TB1). Power for the digital interface is supplied via Pin 1 of J201, or the VDD e-hole located adjacent to J201. The VDD supply can vary between 3.3 V to 5.0 V and sets the level for the output digital data (J201). The J201 connector mates directly with the AD6620 (Receive Signal Processor) evaluation board, Part # AD6620S/PCB, allowing complete evaluation of system performance. The two analog inputs are connected via SMA connectors AIN and BIN, which are transformer-coupled to the AD6600 inputs. The transformers have a turns-ratio of 1:4 to match the input resistance of the AD6600 (200 Ω) to 50 Ω at the SMA connectors. The Encode signal may be generated using an on-board crystal oscillator, U100. If an on-board crystal is used, R104 must be removed from the board to prevent loading of the oscillator’s output. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled ENCODE. If an external source is used, it must be a high quality and very low phase noise source. The high IF range of the AD6600 (70 MHz –250 MHz) demands that the Encode clock be sufficiently pure to maintain performance. The AD6600 output data is latched using 74LCX574 (U201, U202) latches. The clock for these latches is determined by jumper selection on header J1. The clock can be a delayed version of the encode clock (CLKA, CLKB), or the CLK2× generated by the AD6600. A clock is also distributed with the output data (J201) that is labeled CLKX (Pin 11, J201). The CLK× is selected with jumpers on header J1 and can be CLKA, CLKB, or CLK2×. The resonant LC filter components (SEL2, C2 and C3) are omitted. The user must install proper values based on the IF chosen. See Understanding the External Analog Filter section of the data sheet for guidelines on selecting these components. Table VI. AD6600ST/PCB Bill of Material Item Quantity Reference Description 1 2 3 14 SMA Connector Ceramic Chip Capacitor 1206, 0.1 µF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 1 4 2 1 1 1 2 2 1 1 2 3 1 2 1 AIN, BIN, ENCODE C1, C102–108, C114, C117–118, C120–121, C299 C100–101 C111 C112–C113, C115–116 CR1–2 DUT J1 J201 R1–2 R100–R101 R103 R104 R298–R299 T1–T2, T4 TB1 U201–U202 U204 –20– Tantalum Chip Capacitor, 10 µF Ceramic Chip Capacitor 0805, 0.1 µF Ceramic Chip Capacitor 0508, 0.1 µF 1N2810 Schottky Diode AD6600AST 20-Pin Double Row Male Header 50-Pin Double Row Male Header, Right Angle Omitted Surface Mount Resistor 1206, 10 kΩ Surface Mount Resistor 1206, 100 Ω Surface Mount Resistor 1206, 50 Ω Surface Mount Resistor 1206, 2 kΩ Surface Mount Transformer Mini-Circuits T4–1T PCTB2 Terminal Block 74LCX574 Octal Latch 74LVQ00 Two Input NAND Gate REV. 0 + C101 C103 SMA AIN SMA ENCODE 1:4 C105 6 1 2 T1 TI–4T 4 3 C112 0.01F C111 0.1F R104 50 5 GND GND C107 C117 C115 0.01F C118 CR1 1N2810 44 43 42 41 40 39 38 37 36 35 34 AD6600AST VCC TB1 PCTB2 1 2 + C2 SEL SEL2 C100 C102 C3 SEL VCC GND GND 30 GND VDD AVCC 31 GND 32 DVCC 33 CR2 1N2810 C104 C106 SMA BIN 1:4 C108 6 1 2 T2 T1–4T 3 4 GND GND 24 BIN 23 VCC AVCC 25 ENC 26 ENC 27 CLK2X 28 AB_OUT 29 12 13 14 15 16 17 18 19 20 21 22 VDD A 11 AIN 9 B_SEL 10 A_SEL B 8 RSSI0 7 RSSI1 6 RSSI2 4 AVCC 3 C1 2 GND 1 DVCC C113 0.01F VCC GND VDD 1:4 (MSB) D10 AIN C114 0.1F D9 GND GND 7 K1115 D8 AVCC VCC 1 D7 AVCC VCC 6 D6 FLT 2 C1 0.1F D5 FLT R103 100 R2 D4 AVCC VCC 14 U100 VCC 8 OUT VEE R1 D1 GND T4 TI–4T 4 3 D3 GND GND –21– VCC Figure 25. AD6600ST/PCB Schematic Diagram GND VCC D2 AVCC D0 (LSB) REV. 0 BIN CLKREF 2CLK C120 C121 VCC CLKREF C116 0.01F CLK_2 A/B D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RSSI0 RSSI1 RSSI2 C299 0.1F GND GND R299 2k 10 9 2 1 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 OE 1 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 8 U204 74LVQ00 3 11 8D 7D 6D 5D 4D 3D 2D 1D CK GND GND OE 1 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q U202 74LCX574 11 8D 7D 6D 5D 4D 3D 2D 1D CK 5 4 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 13 12 CLKB GND GND CLKA U201 74LCX574 U204 74LVQ00 D7 D8 D9 D10 RSSI2 RSSI1 RSSI0 GND A/B D0 D1 D2 D3 D4 D5 D6 CLKA CLK_2X CLKB R298 2 VDD CLK A B H20DM J1 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 VDD CLKA CLK BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 CLK CLKX BIT2 BIT1 BIT0 GND GND GND GND GND GND GND RSSIB2 RSSIB1 RSSIB0 GND 11 U204 74LVQ00 6 U204 74LVQ00 BIT7 BIT8 BIT9 BIT10 RSSIB2 RSSIB1 RSSIB0 A/B BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 CLKX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A/B GND R100 10k VCC A R101 10k VCC B REMOVE 21 AND 30 H50DM J201 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD6600 AD6600 Figure 26. AD6600ST/PCB Top Side Silk Screen Figure 27. AD6600ST/PCB Top Side Copper Figure 29. AD6600ST/PCB Power Supply Layer (Negative) Figure 28. AD6600ST/PCB Bottom Side Copper Figure 30. AD6600ST/PCB Ground Layer (Negative) –22– REV. 0 AD6600 Connecting the AD6600 with the AD6620 The AD6600 interfaces directly to the AD6620 Digital Receive Signal Processor as shown in Figure 31. No additional external components are required. Note that the layout requirements discussed previously do apply and deviations can result in degraded performance. The digital outputs of the AD6600 must connect directly to the AD6620 inputs with no additional fanout. Additional loading on the outputs will compromise timing performance. (MSB) D10 D9 D8 D7 D6 D5 D4 D3 AD6600 D2 D1 (LSB) D0 ENC ENC IN15 IN14 IN13 IN12 IN11 IN10 IN9 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 EXP2 EXP1 EXP0 A/B CLK RSSI2 RSSI1 RSSI0 AB_OUT CLK2 Figure 32 shows the timing details between the AD6600 and the AD6620. On Clock 1, D[10:0], RSSI[2:0], and AB_OUT are captured by the AD6620. Since AB_OUT has changed state from the previous clock, the D[10:0] and RSSI[2:0] are processed by the AD6620. This clock allows adequate setup and hold time for AB_OUT, D[10:0], and RSSI[2:0] to be captured by the AD6620. On Clock2, D[10:0], RSSI[2:0], and AB_OUT are captured by the AD6620. Since AB_OUT has not changed from the previous clock, the D[10:0] and RSSI[2:0] are ignored by the AD6620. This clock is concerned only with the AB_OUT setupand-hold time. AD6620 Figure 31. AD6600/AD6620 Connections 38.5 38.5 CLK2 CLOCK1 3.0 16.5 CLOCK2 3.0 16.5 D [10:0] RSSI [2:0] 12.5 7.0 AB_OUT Figure 32. AD6600 to AD6620 Timing at 13 MSPS REV. 0 –23– AD6600 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX C00966–2.5–7/00 (rev. 0) 44-Terminal LQFP (Low-Profile Quad Plastic Flatpack) (ST-44) 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) 33 23 34 22 SEATING PLANE 0.394 (10.0) SQ TOP VIEW (PINS DOWN) 44 12 1 0.057 (1.45) 0.053 (1.35) 0.031 (0.80) BSC 0.018 (0.45) 0.012 (0.30) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) 11 –24– REV. 0