Aug. 2003
Edition 0.2
ASSP
Dual Serial Input
PLL Frequency Synthesizer(Small Package)
MB15F76UV
DESCRIPTION
The Fujitsu MB15F76UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 6000MHz and a
1500MHz prescalers. Both IF and RF PLL section have a 1/4 divider. And a 16/17 or a 32/33 for the 6000MHz
prescaler, and a 4/5 or a 8/9 for the 1500MHz prescaler can be selected for the prescaler that enables pulse swallow
operation.
The BiCMOS process is used, as a result, a supply current is typically 8.5mA typ. at 3.0V. The supply voltage range
is from 2.5V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA selectable
by serial data. Fast locking is acheived for adopting the new circuit.
The new package(BCC18) decreases a mount area of MB15F76UV about 50% comparing with the former BCC20(for
dual PLL).
MB15F76UV is ideally suited for wireless communications, such as W-LAN.
FEATURES
• Very small package: BCC18 (2.4*2.7*0.45mm)
• High frequency operation: RF synthesizer : 6000MHz max
IF synthesizer : 1500MHz max
• Low power supply voltage: VCC = 2.5 to 3.6 V
• Ultra Low power supply current : ICC = 8.5 mA typ. (VCC = 3.0V, Ta=25°C, SW=0 in RF, IF locking state)
• Direct power saving function : Power supply current in power saving mode
Typ. 0.1 µA(Vcc=3.0V, Ta=25°C), Max. 10 µA(Vcc=3.0V)
• Dual modulus prescaler : 6000MHz prescaler(16/17 or 32/33, and 1/4divider)
•
1500MHz prescaler(4/5 or 8/9, and 1/4divider)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 5-bit swallow counter: 0 to 31
- Binary 13-bit programmable counter: 3 to 8191
• On-chip phase comparator for fast lock and low noise
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to 85°C
• Sireal data format compatible with MB15F76UL
l
e
Pr
i
im
.
y
r
a
n
18-pad, Plastic BCC
(LCC-18P-M05)
1
Aug. 2003
Edition 0.2
MB15F76UV
PIN ASSIGNMENT
Clock
OSCIN
Data
18 17 16
GND
1
finIF
2
14
finRF
XfinIF
3
13
XfinRF
GNDIF
4
12
GNDRF
VccIF
5
11
VCCRF
DoIF
6
10
DoRF
TOP
VIEW
7
8
9
15
PSIF
PSRF
LD/fout
LCC-18P-M05
2
LE
Aug. 2003
Edition 0.2
MB15F76UV
PIN DESCRIPTIONS
Pin No.
Pin
name
I/O
1
GND
-
Ground for OSC input buffer and the shift registor circuit.
2
finIF
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
3
XfinIF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
4
GNDIF
-
Ground for the IF-PLL section.
5
VccIF
-
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
6
DoIF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
7
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode
8
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
9
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode
10
DoRF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
11
VccRF
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
12
GNDRF
-
Ground for the RF-PLL section.
13
XfinRF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
14
finRF
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
15
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.
Descriptions
16
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
17
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
18
OSCIN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
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Aug. 2003
Edition 0.2
MB15F76UV
BLOCK DIAGRAM
VCCIF
5
PSIF 7
Intermittent
mode
control
(IF–PLL)
3-bit latch
5-bit latch
13-bit latch
LDS SWIF FCIF
Binary 5-bit
swallow counter
Binary 13-bit
programmable
counter(IF–PLL)
(IF–PLL)
fpIF
GNDIF
4
Phase
comp.
Fast
lock
(IF–PLL)
tuning
Charge Current
pump Switch
(IF–PLL)
6 DoIF
Prescaler
(IF–PLL)
4/5,8/9
finIF 2
XfinIF 3
2-bit latch
1/4divider
T1
T2
14-bit latch
Lock
Det.
1-bit latch
(IF–PLL)
C/P
setting
current
Binary 14–bit programmable ref.
counter(IF–PLL)
LDIF
frIF
OSCin 18
Fast
lock
tuning
AND
OR
T1
finRF 14
XfinRF 13
1/4divider
T2
2-bit latch
Binary 14-bit programmable ref.
counter(RF–PLL)
C/P
setting
current
14-bit latch
1-bit latch
Prescaler
Selector
LD
frIF
frRF
fpIF
fpRF
8 LD/fout
Lock
Det.
frRF
(RF–PLL)
(RF–PLL)
16/17,
32/33
LDS SWRF FCRF
PSRF 9
Intermittent
mode
control
3-bit latch
Binary 5-bit
swallow counter
(RF–PLL)
Binary 13-bit
programmable
counter(RF–PLL)
5-bit latch
13-bit latch
Phase
comp.
(RF–PLL)
fpRF
Fast
lock
tuning
(RF–PLL)
LE 15
Schmitt
circuit
Data 16
Schmitt
circuit
Clock 17
Schmitt
circuit
Latch selector
C
N
C
N
1
2
23-bit shift
register
1
GND
4
11
VccRF
12
GNDRF
Charge Current
pump Switch
(RF–PLL)
10 DoRF
Aug. 2003
Edition 0.2
MB15F76UV
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
VI
–0.5 to VCC +0.5
V
VO
GND to Vcc
V
LD/fout
VDO
GND to Vcc
V
Do
Tstg
–55 to +125
°C
Power supply voltage
Input voltage
Output voltage
Storage temperature
Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
3.6
V
VCCRF = VCCIF
–
VCC
V
–
+85
°C
Min.
Typ.
Max.
VCC
2.5
3.0
Input voltage
VI
GND
Operating temperature
Ta
–40
Power supply voltage
Handling Precautions
(1) VccRF and,VccIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VccRF and VccIF to keep them equal. It is
recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
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Aug. 2003
Edition 0.2
MB15F76UV
ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
"H" level Input voltage
"L" level Input voltage
mA
ICCRF
finRF=2500MHz
VccRF=3.0V
5.2
6.2
7.5
mA
IPSIF
PSIF=PSRF= ”L”
–
0.1*2
10
µA
IPSRF
PSIF=PSRF= ”L”
–
0.1
10
µA
finIF*3
finIF
IF PLL
100
–
1500
MHz
finRF*3
finRF
RF PLL
2000
–
6000
MHz
OSCIN
fosc
3
–
40
MHz
finIF
PfinIF
IF PLL, 50 Ω system
-15
–
+2
dBm
finRF
PfinRF
RF PLL, 50 Ω system
-10
–
+2
dBm
OSCIN
VOSC
0.5
–
1.5
Vp-p
Data,
Clock,
LE
VIH
Schmitt trigger input
Vcc ×
0.7+0.4
–
–
VIL
Schmitt trigger input
–
–
Vcc×
0.3-0.4
Data,
Clock,
LE, PS
LD/fout
"L" level output voltage
"H" level output voltage
"L" level output voltage
High impedance
cutoff current
"H"level Output current
"L" level Output current
Unit
2.9
"L" level Input voltage
"H" level output voltage
Max.
2.3
–
–
DoIF
DoRF
DoIF
DoRF
LD/fout
*2
VIH
–
Vcc×
0.7
–
–
VIL
–
–
–
Vcc×
0.3
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
Vcc –
0.4
–
–
–
–
0.4
PS
"L" level Input current
Typ.
1.8
"H" level Input voltage
"H" level Input current
Min.
finIF=2000MHz
VccIF=3.0V
Power saving current*9
Input sensitivity
Value
ICCIF
Power supply current*1
Operating frequency
Condition
VOH
VCC=2.7V, IOH=–1mA
VOL
VCC=2.7V, IOL=1mA
VDOH
VCC=2.7V, IDOH=-0.5mA
Vcc –
0.4
–
–
VDOL
VCC=2.7V, IDOL=0.5mA
–
–
0.4
IOFF
VCC=2.7V,
VOFF=0.5V to Vp–0.5V
–
–
2.5
IOH*4
VCC = 2.7V
–
–
-1.0
IDOL
VCC = 2.7V
1.0
–
–
V
V
µA
V
V
nA
mA
(Continued)
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Edition 0.2
MB15F76UV
(Continued)
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
Typ.
Max.
Unit
VCC=2.7 V
VDOH=Vcc /2
Ta= 25°C
CS bit ="1"
-8.2
-6.0
-4.1
CS bit ="0"
-2.2
-1.5
-0.8
CS bit ="1"
4.1
6.0
8.2
IDOL
VCC=2.7 V
VDOL=Vcc/2
Ta= 25°C
CS bit ="0"
0.8
1.5
2.2
IDOL/IDOH
IDOMT*5
VDO=Vcc/2
–
3
10
%
vs VDO
IDOVD*6
0.5V < VDO < Vcc-0.5V
–
10
15
%
vs Ta
IDOTA*7
-40°C < Ta < 85 °C,
VDO=Vcc/2
–
5
10
%
DoTX*8
DoRX
"L" level Output current
mA
Conditions; fosc=12.8MHz, Ta = 25°C, SW="L" in locking state.
Vcc=2.7V, fosc=12.8MHz, Ta = 25°C, in power saving mode.
AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol "-"(minus) means direction of current flow.
Vcc=3.0V, Ta=25°C ( ||I3| - |I4|| ) / [( |I3| + |I4| )/2] x 100(%)
Vcc=3.0V, Ta=25°C [( ||I2| - |I1|| ) /2 ] / [( |I1| + |I2| )/2] x 100(%) (Applied to each IDOL, IDOH)
Vcc=3.0V, [(||IDO(85C)| - |IDO(-40C)||) /2] / [(|IDO(85C)| + |IDO(-40C)|) /2] x 100(%) (Applied to each IDOL, IDOH)
When Charge pump current is measured, set LDS="0", T1="0" and T2="1".
PSIF=PSRF=GND (VIL=GND and VIH=Vcc for Clock, Data, LE)
I2
I3
IDOL
I1
IDOH
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
Min.
IDOH*4
"H"level Output current
Charge pump
current rate
Value
Condition
I4
I1
I2
0.5
Vcc/2
Vcc-0.5
Vcc
Output voltage(V)
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Aug. 2003
Edition 0.2
MB15F76UV
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x 4 x fOSC ÷ R
fVCO:
P:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (4 or 8 for IF-PLL, 16 or 32 for RF-PLL)
Preset divide ratio of binary 13-bit programmable counter (3 to 8191)
Preset divide ratio of binary 5-bit swallow counter (0≤ A ≤ 31, condition;A < N)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
CN2
0
0
The programmable reference counter for the IF-PLL.
1
0
The programmable reference counter for the RF-PLL.
0
1
The programmable counter and the swallow counter for the IF-PLL
1
1
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22
23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
C
S
X
X
X
X
CN1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table. 2]
T1, 2
: LD/fout output setting bit
[Table. 3]
CS
: Charge pump current select bit
[Table. 8]
X
: Dummy bits(Set "0" or "1")
NOTE: Data input with MSB first.
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Edition 0.2
MB15F76UV
Programmable Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
F
C
A
1
A
2
A
3
A
4
A
5
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
N
12
N
13
IF/RF IF/RF
CN1, 2
N1 to N11
A1 to A7
SWIF/RF
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 8191)
: Divide ratio setting bits for the swallow counter (0 to 31)
: Divide ratio setting bit for the prescaler
(4 or 8 for the SWIF, 16 or 32 for the SWRF)
: Phase control bit for the phase detector(IF : FCIF, RF : FCRF)
FCIF/RF
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 3]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state
LDS
T1
T2
0
0
0
0
1
0
0
1
1
frIF
1
0
0
frRF
1
1
0
fpIF
1
0
1
fpRF
1
1
1
LD output
fout
output
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Edition 0.2
MB15F76UV
Table.4 Binary 13-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
13
N
12
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
8191
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.5 Binary 5-bit Swallow Counter Data Setting
Divide
ratio
(N)
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
1
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
31
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 31
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
SW = ”1”
SW = ”0”
IF-PLL
4/5
8/9
RF-PLL
16/17
32/33
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF,RF = 1
FCIF,RF = 0
1
DoIF,RF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
1
2
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
10
VCO Output
Frequency
2
VCO Input Voltage
Aug. 2003
Edition 0.2
MB15F76UV
Table. 8 Charge Pump Current Setting
CS
Current value
1
+ 6.0 mA
0
+ 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode.
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Note: • PS pin must be set at “L” for Power ON.
OFF
ON
tv > 1µs
Vcc
Clock
Data
LE
tps > 100ns
PS
(1)
(2)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1µs later after power supply remains stable(Vcc > 2.2V).
(3) Relase power saving mode (PS: L → H) 100nS later after setting serial data.
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MB15F76UV
SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit Invalid data
LSB
MSB
Data
Clock
LE
t2
t1
t4
t3
t5
t7
t6
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
Note: LE should be "L" when the data is transferred into the shift register.
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MB15F76UV
PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = 1)
H
DoIF/RF
Z
L
(FC bit = 0)
DoIF/RF
Z
LD Output Logic Table
RF–PLL section
LD output
Locking state / Power saving state
Locking state / Power saving state
H
Locking state / Power saving state
Unlocking state
L
Unlocking state
Locking state / Power saving state
L
Unlocking state
Unlocking state
L
IF–PLL section
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i.e. tWU > 200ns when foscin = 10 MHz
tWL < 4/fosc: i.e. tWL < 400ns when foscin = 10 MHz
14
Aug. 2003
Edition 0.2
MB15F76UV
TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
Controller
S.G
(Divide ratio setting)
50Ω
S.G
1000pF
S.G
OSCIN Clock Data
50Ω
GND
1
finIF
2
XfinIF
3
18
17
16
15
LE
14
finRF
13
XfinRF
50Ω
MB15F76UV
1000pF
GNDIF
4
12
GNDRF
VccIF
5
11
VccRF
DoIF
6
10
DoRF
7
8
9
1000pF
PSIF LD/fout PSRF
VccRF
0.1µ
0.1µ
Oscilloscope
15
Aug. 2003
Edition 0.2
MB15F76UV
APPLICATION EXAMPLE
1000pF
From controller
TCXO
OSCIN Clock Data
GND
1
finIF
2
XfinIF
3
1000pF
1000pF
GNDIF
4
VccIF
5
DoIF
6
18
17
16
MB15F76UV
7
8
9
15
LE
14
finRF
13
XfinRF
12
GNDRF
11
VccRF
10
DoRF
1000pF
1000pF
0.1µ
PSIF LD/fout PSRF
0.1µ
LPF
VCO
Output
VCO
Output
Lock Det.
LPF
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
16
Aug. 2003
Edition 0.2
MB15F76UV
PACKAGE DIMENSION
BCC18(LCC-18P-M05)
17