ETC TH7121

TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Features
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Single chip solution with only a few external components
Stand-alone fixed-frequency transceiver operation modes
Programmable multi-channel transceiver operation modes
Low current consumption in active mode and very low standby current
PLL-stabilized RF VCO (LO) with external varactor diode
Lock detection in programmable channel applications
3wire bus serial control interface
FSK/ASK modulation selection
FSK for digital data and FM for analog signal reception
RSSI allows signal strength indication and ASK detection
Switchable LNA gain for improved dynamic range
Automatic PA turn-on after PLL lock
FM possible with external varactor
ASK modulation achieved by on/off keying
AFC option for extended input frequency acceptance range
Surface mount package LQFP32
N
I
M
I
L
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R
Ordering Information
Part No. (Engineering Samples)
TH7121
(TH7120-02)
Temperature Code
Y
R
A
E (-40 °C to 85 °C)
Package Code
NE (LQFP32)
Application Examples
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General bi-directional half duplex digital data transmission or analog signal transmission
Low-power telemetry
Alarm and security systems
Keyless car and central locking
Domotics
Model control
Technical Data Overview
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Frequency range: 300 MHz to 930 MHz for programmable channel applications
315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-frequency single-channel variants
Power supply range: 2.5 V to 5.5 V
Temperature range: -40 °C to +85 °C
Standby current: 50 nA
Operating current: 6.0 mA in receive mode at low gain
Operating current 9.0 mA in transmit mode at 0 dBm output power
Adjustable output power range from –15 dBm to +6 dBm
Sensitivity: -103 dBm at FSK with 150 kHz IF filter BW
Sensitivity: -105 dBm at ASK with 150 kHz IF filter BW
Maximum data rate for FSK and ASK: 60 kbit/s NRZ
Maximum input level: –10 dBm at FSK and -20 dBm at ASK
Input frequency acceptance: ± 50 kHz (with AFC option)
Frequency deviation range: ±5 kHz to ±100 kHz
Maximum analog modulation frequency: 20 kHz
3 MHz to 12 MHz crystal reference
3901007121
Rev. 001
Page 1 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
General Description
The TH7120 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi-channel
programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used for ISM,
SRD or any other application operating in the frequency ranging of 300 MHz to 930 MHz.
The TH7120 transceiver IC consists of the following building blocks:
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Low-noise amplifier (LNA) for high-sensitivity RF signal reception with switchable gain
Mixer (MIX) for RF-to-IF down-conversion
IF amplifier (IFA) to amplify and limit the IF signal and for RSSI generation
Phase-coincidence demodulator with external ceramic discriminator (FSK Demodulator)
Operational amplifier, connected to demodulator output (OA1)
Operational amplifier, integrator circuit at FSK-AFC mode (OA2)
Control logic with 3wire bus serial control interface (SCI)
Reference oscillator (RO) with external crystal
Reference divider (R counter)
Programmable divider (N/A counter)
Phase-frequency detector (PFD)
Charge pump (CP)
Voltage control oscillator (VCO) with internal varactor
Power amplifier (PA) with adjustable output power
L
E
R
N
I
IM
Y
R
A
The transceiver can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixedfrequency device. After power up, the transceiver is set to fixed-frequency mode. In this mode, pins
FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation.
The logic levels at pins FS0/SDEN and FS1/LD must not be changed after power up in order to remain in
fixed-frequency mode.
P
Channel frequency
FS0/SDEN
FS1/LD
433.92 MHz
868.3 MHz
315.0 MHz
915.0 MHz
1
0
1
0
0
0
1
1
After the first logic level change at pin FS0/SDEN, the transceiver enters into programmable mode while pin
FS1/LD is now a PLL lock detector output. In this mode, the user can set any PLL frequency or mode of operation by the SCI.
In the fixed-frequency mode, the user can set the transceiver to Standby, Receive, Transmit or Idle (only PLL
synthesizer active) mode via control pins RE/SCLK and TE/SDTA.
Operation mode
Standby
Receive
Transmit
Idle
RE/SCLK
0
1
0
1
TE/SDTA
0
0
1
1
3901007121
Rev. 001
Page 2 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
8
14
SDTA
VEE_DIG
SDEN
18
OA1
SCI
5
OUT_DTA
4
INT1
VCC_DIG
SCLK
bias
17
Control Logic
200k
FS0/SDEN
16
TE/SDTA
15
RE/SCLK
13
ASK/FSK
12
IN_DTA
9
FSK
VEE_RO
FS1/LD
19
MIX
FSK_SW
11
FSK Demodulator
3 IN_DEM
6 OUT_DEM
OA2
INT2
Block Diagram
22 VEE_PLL 10 RO
21 LF
2
RO
IFA
L
E
R
VCC_IF
R
counter
7 RSSI
1.5pF
RO
N
I
IM
23 TNK_LO 20 VCC_PLL
LO
VCO
IF
MIX
N
counter
31
VEE_IF
32
P
1
IN_IFA
OUT_MIX1
Y
R
A
30
IN_MIX
Figure 1:
3901007121
Rev. 001
24 PS_PA
PA
25
OUT_PA
LNA
26
27
VEE_LNA
IN_LNA
29
GAIN_LNA
ASK
28
OUT_LNA
TH7121 block diagram
Page 3 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Pin Definition and Description
Pin No.
1
Name
IN_IFA
I/O Type
Functional Schematic
Description
VCC
input
3.1k
2.2k
IF amplifier input, approx.
2 kΩ single-ended
3.1k
IN_IFA
1
140µA
VEE
2
VCC_IF
supply
3
IN_DEM
analog I/O
positive supply of LNA, MIX,
IFA, FSK Demodulator, PA,
OA1 and OA2
IF amplifier output and demodulator input, connection
to external ceramic discriminator
VCC
77k
IN_DEM
3
N
I
IM
1.5p
10µA
4
INT2
100µA
VEE
VCC
output
Y
R
A
integrator output OA2
INT2
4
L
E
R
OUT_DTA output
5
INT1
INT1
VCC
inverting inputs OA1 and
OA2
bias
OA2
OUT_DEM
5
6
VEE
VCC
120
OUT_DEM analog I/O
output OA1
VEE
VCC
input
120
6
P
8
OUT_DTA
120
8
VEE
10.5p
1k
520k
OA1
demodulator output and noninverting input OA1
10.5p
+
520k
200k
VEE
7
RSSI
output
VCC
VCC
RSSI output
5µA
RSSI
120
7
5µA
VEE
3901007121
Rev. 001
VEE
Page 4 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
Name
I/O Type
9
VEE_RO
ground
10
RO
analog I/O
Functional Schematic
Description
ground of RO
VCC
RO input, base of bipolar
transistor
2.6µA
40p
RO
40p
10
39k
11
FSK_SW
VEE
VCC
analog I/O
FSK_SW
11
VEE
12
IN_DTA
input
N
I
IM
VCC
15
16
13
RE/SCLK
TE/SDTA
ASK/FSK
P
input
IN_DTA
12
RE/SCLK
15
L
E
R
input
16
TE/SDTA
input
120
120k
VEE
VCC
ASK/FSK
13
17
FS0/SDEN input
14
VCC_DIG
supply
18
VEE_DIG
ground
19
FS1/LD
input
FSK pulling pin, switch to
ground or OPEN
Y
R
A
ASK/FSK modulation data
input, pull down resistor
120kΩ
receiver enable input / clock
input for the shift register,
pull down resistor 120kΩ
transmitter enable input /
serial data input, pull down
resistor 120kΩ
ASK/FSK mode select input
120
frequency select input / serial data enable input
17
FS0/SDEN
VEE
positive supply of serial port
and control logic
ground of serial port and
control logic
frequency select input / lock
detector output
VCC
FS1/LD
19
120
VEE
20
VCC_PLL
supply
22
VEE_PLL
ground
3901007121
Rev. 001
positive supply of PLL frequency synthesizer
ground of PLL frequency
synthesizer
Page 5 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
21
Name
LF
I/O Type
Functional Schematic
VCC
analog I/O
LF
Description
charge pump output, connection to external loop filter
120
21
23
TNK_LO
analog I/O
VCC
VCO open-collector output,
connection to external LC
tank
TNK_LO
23
VEE
33
33
VEE
24
PS_PA
VCC
analog I/O
PS_PA
VCC
N
I
IM
120
L
E
R
24
VEE
25
OUT_PA
output
VEE
VCC
OUT_PA
P
VEE
VEE_LNA
ground
28
OUT_LNA
output
VEE
ground of LNA and PA
OUT_LNA
bias
28
37
3.8k
IN_LNA
power amplifier opencollector output
25
27
26
Y
R
A
power-setting input
input
IN_LNA
LNA open-collector output,
connection to external LC
tank at RF
VEE
40p
LNA input,
approx. 50Ω single-ended
26
VEE
29
VCC
GAIN_LNA input
GAIN_LNA
LNA gain control input
120
29
VEE
3901007121
Rev. 001
Page 6 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Pin No.
30
Name
IN_MIX
I/O Type
Functional Schematic
Description
VCC
input
mixer input, approx. 200Ω
single-ended
210
IN_MIX
30
LO
bias
VEE
31
VEE_IF
ground
32
OUT_MIX
output
VEE
VCC
OUT_MIX
32
100
N
I
IM
VEE
P
3901007121
Rev. 001
L
E
R
Page 7 of 28
ground of IFA, Demodulator,
OA1 and OA2
mixer output, approx. 330Ω
single-ended
Y
R
A
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Stand-Alone Fixed-Frequency Operation
After power up the transceiver is set to fixed-frequency mode. In this mode, pins FS0/SDEN and FS1/LD
must be connected to VEE or VCC to set the desired frequency of operation. The logic levels at pins FS0/SDEN
and FS1/LD must not be changed after power up in order to remain in fixed-frequency mode. The default
settings of the control word bits in stand-alone mode are described in the frequency selection table.
Frequency Selection
Channel frequency
433.92 MHz
868.3 MHz
315 MHz
915 MHz
FS0/SDEN
1
0
1
0
FS1/LD
0
0
1
1
Reference oscillator frequency
Y
R
A
7.1505 MHz
R counter ratio in RX mode
16
16
PFD frequency in RX mode
446.91 kHz
18
30
446.91 kHz
397.25 kHz
238.35 kHz
947
1919
766
3794
VCO frequency in RX mode
423.22 MHz
857.60 MHz
304.30 MHz
904.30 MHz
RX frequency
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
16
16
18
30
N/A counter ratio in RX mode
R counter ratio in TX mode
L
E
R
PFD frequency in TX mode
N
I
IM
446.91 kHz
446.91 kHz
397.25 kHz
238.35 kHz
971
1943
793
3839
VCO frequency in TX mode
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
TX frequency
433.92 MHz
868.30 MHz
315.00 MHz
915.00 MHz
10.7 MHz
10.7 MHz
10.7 MHz
10.7 MHz
N/A counter ratio in TX mode
P
IF frequency in RX mode
3901007121
Rev. 001
Page 8 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Default Register Settings After Power-up
Bits
A-word
symbols
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
not used
DI_MODE
MODUL
HighCur
LOCK_MODE
PA_AUTO
Pow1
Pow0
MIXG
LNAG
TE
RE
RR9
RR8
RR7
RR6
RR5
RR4
RR3
RR2
RR1
RR0
Bits
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C-word
symbols
P
LNAGI_E
POLAR
High2
High1
UP
NR16
NR15
NR14
NR13
NR12
NR11
NR10
NR9
NR8
NR7
NR6
NR5
NR4
NR3
NR2
NR1
NR0
3901007121
Rev. 001
Channel Channel Channel Channel
‘00’
‘01’
‘10’
‘11’
868.3 433.92 915.0
315.0
MHz
MHz
MHz
MHz
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
L
E
R
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
1
0
0
1
0
not used
not used
EnDelPLL
LNAHYST
EnAdj
EnFM
Max2
Max1
Max0
Min2
Min1
Min0
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT0
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
0
0
1
0
0
0
0
N
I
IM
Channel Channel Channel Channel
‘00’
‘01’
‘10’
‘11’
868.3 433.92 915.0
315.0
MHz
MHz
MHz
MHz
0
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
B-word
symbols
Channel Channel Channel Channel
‘00’
‘01’
‘10’
‘11’
868.3 433.92 915.0
315.0
MHz
MHz
MHz
MHz
0
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
B-word
symbols
MODUL_CTR
LD_TM1
LD_TM0
ER_TM1
ER_TM0
NT16
NT15
NT14
NT13
NT12
NT11
NT10
NT9
NT8
NT7
NT6
NT5
NT4
NT3
NT2
NT1
NT0
Page 9 of 28
Y
R
A
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
Channel Channel Channel Channel
‘00’
‘01’
‘10’
‘11’
868.3 433.92 915.0
315.0
MHz
MHz
MHz
MHz
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Programmable Channel Operation
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in multichannel mode (see Fig. 2). At each rising edge of the SCLK signal, the logic value on the SDTA pin is written
into a 24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches
on the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first
two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant
24 bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To
program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word
and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 2
and 3. Table REGISTER SETTINGS describes the function of each bit.
SDTA
24-BIT
SHIFT REGISTER
SCLK
22
22
Y
R
A
22
A-word
B - LATCH
22
B-word
C - LATCH
22
C-word
D - LATCH
22
D-word
A - LATCH
22
2
N
I
IM
22
‘00’
L
E
R
‘01’
SDEN
ADDR DECODER
P
‘10’
‘11’
22
Figure 2: SCI block diagram
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as
well as in standby mode.
Invalid
data
SDTA
MSB
bit 23
LSB
bit 22
bit 1
tCH
tCWL tCWH
Invalid
data
bit 0
SCLK
tCS
SDEN
tES
tEW
tEH
Figure 3: Serial data input timing
3901007121
Rev. 001
Page 10 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
SCI Words
A-word
5
X
4
X
3
X
2
X
1
X
RR3
RR2
RR1
21
X
20
X
19
X
18
X
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
B-word
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
2
X
1
X
RT0
RT9
3
X
LSB
NR6
NR5
NR4
NR3
NR2
NR1
13
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
NT6
NT5
NT4
NT3
NT2
NT1
NT0
NR0
NR7
0
X
NT7
NT13
4
X
NR8
NT14
5
X
NT8
NT15
6
X
NR9
NT16
7
X
NT9
14
X
8
X
NR10
15
X
9
X
NT10
16
X
10
X
NR11
17
X
11
X
NT11
18
X
12
X
0
X
NR12
NR14
19
X
1
X
NT12
NR15
20
X
2
X
NR13
NR16
21
X
3
X
Min0
Max0
Max1
Max2
EnFm
EnAdj
UP
13
X
ER_TM0
14
X
High1
15
X
ER_TM1
16
X
High2
17
X
LD_TM0
18
X
POLAR
19
X
4
X
Min1
P
20
X
LD_TM1
1
0
ADDR
21
X
LNAGI_E
22
L
E
R
MODUL_CTR
MSB
N
I
IM
5
X
Min2
C-word
LNAHYST
EnDelPLL
0
1
ADDR
23
Y
R
A
LSB
22
not used
23
not used
MSB
0
X
RR0
6
X
RR6
7
X
RR7
8
X
RR8
9
X
RR9
10
X
RE
11
X
TE
12
X
LNAG
13
X
MIXG
14
X
Pow0
15
X
Pow1
16
X
PA_AUTO
17
X
LOCK_MODE
18
X
HighCur
19
X
MODUL
20
X
DI_MODE
0
0
ADDR
21
X
RR4
LSB
22
not used
23
RR5
MSB
D-word
MSB
23
LSB
22
1
1
ADDR
3901007121
Rev. 001
Page 11 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Register Settings
A-word
Symbol
Bits
No.
[9:0]
10
Description
Software button
RR9:RR0
Reference divider ratio in RX mode
RR9:RR0
TE:RE
[11:10]
2
Select active mode at programmable-channel application:
OPMODE
LNAG
[12]
[13]
Standby mode
‘11’
Idle mode
‘10’
Transmit mode
‘01’
Receive mode
‘0’
low LNA gain
‘1’
high LNA gain
1
1
‘0’
2
L
E
R
‘01’
P
PA_AUTO
‘10’
‘11’
[16]
1
‘0’
‘1’
PA_AUTO
LOCK_MODE
[17]
1
[18]
[19]
[20]
Pmax - 6 dBm
Pmax
Disable automatic PA turn-on after PLL lock:
enabled
disabled
before lock only
‘1’
before and after lock.
Select Charge Pump output current:
1
‘0’
± 260 µA
‘1’
±1300 µA
Select modulation mode at internal modulation control:
ASK/FSK
DI_MODE
Pmax - 12 dBm
‘0’
1
CPCUR
MODUL
Pmax - 20 dBm
Select PFD output analyse mode of lock detecting:
LOCK_MODE
HighCur
high gain
Select output power at programmable-channel application:
‘00’
TXPOWER
low gain
‘1’
[15:14]
N
I
IM
Select mixer conversion gain at programmable-channel application:
MIXGAIN
Pow1:Pow0
Y
R
A
Select LNA gain at internal gain control:
LNAGAIN
MIXG
‘00’
‘0’
ASK
‘1’
FSK
1
Select mode for input data:
‘0’
normal
‘0’ for space at ASK or fmin at FSK, ‘1’ for mark at ASK or fmax at FSK
DI_MODE
‘1’
inverse
‘1’ for space at ASK or fmin at FSK, ‘0’ for mark at ASK or fmax at FSK
not used
3901007121
Rev. 001
[21]
1
‘X’
Page 12 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
B-word
Symbol
Bits
No.
[9:0]
10
Description
Software button
RT9:RT0
Reference divider ratio in TX mode
RT9:RT0
Min2:Min0
[12:10]
3
Select minimum value of RO active current:
ROMIN
‘000’
0 µA
‘001’
50 µA
‘010’
100 µA
‘011’
150 µA
‘100’
200 µA
‘101’
250 µA
‘110’
300 µA
‘111’
Max2:Max0
[15:13]
3
Select maximum value of RO active current:
‘000’
‘001’
L
E
R
‘010’
ROMAX
P
N
I
IM
350 µA
Y
R
A
‘011’
0 µA (RO is off)
50 µA
100 µA
150 µA
‘100’
200 µA
‘101’
250 µA
‘110’
300 µA
‘111’
350 µA
EnFm
[16]
1
Test bit. Forced '0' for correct functioning.
EnAdj
[17]
1
Test bit. Forced '0' for correct functioning.
LNAHYST
[18]
1
Enable LNA hysteresis:
LNAHYST
EnDelPLL
[19]
disabled
‘0’
enabled
1
Enable delayed start of the PLL:
EnDelPLL
not used
[20]
1
‘X’
not used
[21]
1
‘X’
3901007121
Rev. 001
‘1’
‘1’
disabled
‘0’
enabled.
Page 13 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
C-word
Symbol
Bits
No.
[16:0]
17
Description
Software button
NR16:NR0
Feedback divider ratio in RX mode
NR16:NR0
UP
[17]
1
BAND
High2:High1
[19:18]
[20]
‘1’
up to 500 MHz
‘0’
500 to 1000MHz
2
VCOCUR
POLAR
Select frequency band:
Select VCO active current:
‘00’
low current (250 µA)
‘01’
standard current (350 µA)
‘10’
high1 current (450 µA)
‘11’
high2 current (550 µA)
1
Select Phase Detector polarity:
N
I
M
I
L
E
R
‘1’
PFDPOL
P
LNACTRL
3901007121
Rev. 001
positive (1)
(1)
VCO
OUTPUT
FREQUENCY
‘0’
LNAGI_E
Y
R
A
[21]
1
negative (2)
(2)
VCO INPUT VOLTAGE
Select LNA gain control mode:
‘0’
external LNA gain control
‘1’
internal LNA gain control
Page 14 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
D-word
Symbol
Bits
No.
[16:0]
17
Description
Software button
NT16:NT0
Feedback divider ratio in TX mode
NT16:NT0
ER_TM1:ER_TM0 [18:17]
2
ER_TM1:ER_TM0
LD_TM1:LD_TM0 [20:19]
2
Select maximum enabled PFD output error for lock detecting
(in reference frequency clocks):
‘00’
2 clocks
‘01’
4 clocks
‘10’
8 clocks
‘11’
16 clocks
‘00’
‘01’
LD_TM1:LD_TM0
‘10’
‘11’
MODUL_CTR
[21]
1
P
3901007121
Rev. 001
4 clocks
N
I
IM
16 clocks
64 clocks
256 clocks
Select mode of modulation control:
L
E
R
‘0’
MODCTRL
Y
R
A
Select minimum number of PFD reference frequency clocks
before lock detecting:
‘1’
external modulation control
internal modulation control
Page 15 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Technical Data
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Input current
Input RF level
Storage temperature
Electrostatic discharge
Electrostatic discharge
Symbol
Vcc
VIN
IIN
Pimax
TSTG
VESD1
VESD2
Condition / Note
Min
Max
Unit
0
- 0.3
-1
7.0
Vcc+0.3
1
10
+125
+1.0
TBD
V
V
mA
dBm
°C
kV
kV
no damage
human body model, 1)
human body model, 2)
-40
-1.0
TBD
1) pins IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD
2) all pins, exept IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD
Normal Operating Conditions
Parameter
Supply voltage
Operating temperature
Carrier frequency
VCO frequency
RO frequency
Frequency deviation
FSK data rate
FM bandwidth
ASK data rate
P
DC Characteristics
Symbol
Vcc
Ta
fc
fVCO
fRO
∆f
RFSK
fm
RASK
Condition
L
E
R
Max
Unit
2.5
-40
300
300
3
±5
5.5
+85
930
930
12
±120
60
20
60
V
ºC
MHz
MHz
MHz
kHz
kbit/s
kHz
kbit/s
N
I
IM
at FM or FSK
NRZ
Y
R
A
Min
NRZ
all parameters under normal operating conditions, unless otherwise stated;
typical values at Ta = 23 °C and Vcc = 3 V
Parameter
Symbol
Standby current
ISBY
Idle current
IIDLE
Total supply current in
receive mode at low gain
IRX_low
Total supply current in
receive mode at high gain
IRX_high
Total supply current in
transmit mode at 0 dBm power
ITX_0
3901007121
Rev. 001
Condition
TE/SDTA=0,
RE/SCLK=0
TE/SDTA=1,
RE/SCLK=1
@ fi = 868.3 MHz
TE/SDTA=0,
RE/SCLK=1
VGAIN_LNA > 1.4 V
@ fi = 868.3 MHz
TE/SDTA=0,
RE/SCLK=1
VGAIN_LNA < 0.8 V
@ fi = 868.3 MHz
TE/SDTA=1,
RE/SCLK=0
ASK/FSK=1
@ fi = 868.3 MHz,
@ Po = 0 dBm
Page 16 of 28
Min
Typ
Max
Unit
50
100
nA
2.5
3.2
mA
6.0
8.0
mA
7.0
9.0
mA
9.0
11.5
mA
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
AC System Characteristics of the Receiver Part
all parameters under normal operating conditions, unless otherwise stated; all parameters based on test
circuits for FSK (Fig. 4 to 5), FM and ASK (Fig. 6 to 7), respectively; RF at 868.3 MHz
Parameter
Input sensitivity – FSK
Symbol
Pmin_FSK
Input sensitivity – ASK
Pmin_ASK
Maximum input signal – FSK/FM
at low gain
Maximum input signal – FSK/FM
at high gain
Maximum input signal – ASK
at low gain
Maximum input signal – ASK
at high gain
Image rejection
Blocking immunity
Start-up time – FSK/FM
Pmax_FSK_1
Start-up time – ASK
TASK
Spurious emission
Pmax_FSK_0
Pmax_ASK_1
Pmax_ASK_0
∆Pimag
∆Pblock
TFSK
Condition
BIF = 150kHz
∆f = ± 50 kHz (FSK/FM)
-3
BER ≤ 3⋅10
BIF = 150kHz
-3
BER ≤ 3⋅10
-3
BER ≤ 3⋅10
VGAIN_LNA > 1.4 V
-3
BER ≤ 3⋅10
VGAIN_LNA < 0.8 V
-3
BER ≤ 3⋅10
VGAIN_LNA > 1.4 V
-3
BER ≤ 3⋅10
VGAIN_LNA < 0.8 V
∆fblock > ±2MHz, note 1
TE/SDTA=0,
RE/SCLK=1
valid data at output
depends on ASK detector time constant and
start-up mode, valid
data at output
L
E
R
Pspur
Min
N
I
IM
Typ
-103
Max
Unit
dBm
-105
dBm
10
dBm
-10
dBm
-20
dBm
0
dBm
TBD
TBD
dB
dB
ms
Y
R
A
1
TFSK
+
200K * C6
ms
-70
dBm
Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal
P
AC System Characteristics of the Transmitter Part
all parameters under normal operating conditions, unless otherwise stated;
typical values at Ta = 23 °C and Vcc = 3 V;
TE/SDTA=1, RE/SCLK=0, ASK/FSK=1, RPS≥15 kΩ, fc = 868.3 MHz, test circuit shown in Fig. 4 to 7
Parameter
Symbol
Output power
FSK deviation
Po
∆fFSK
Data rate FSK
FM deviation
RFSK
∆fFM
Modulation frequency FM
Data rate ASK
PLL spurs emission
Harmonic emission
VCO gain
Charge pump current
Start-up time
fmod
RASK
Pspur
Pharm
KVCO
ICP
TTX
3901007121
Rev. 001
Condition
Min
Typ
Max
Unit
CW mode
depends on Cx1, Cx2 and
crystal parameter
4
±5
6
±50
8
±100
dBm
kHz
adjustable with varactor
and VFM
at all fc and nominal Po
at all fc and power steps
from ”standby” to
“transmit” mode
Page 17 of 28
60
±6
kbit/s
kHz
5
60
kHz
kbit/s
dBm
dBm
MHz/V
µA
ms
35
260
-36
-36
1
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Output Power Selection
typical values at Ta = 23 °C and Vcc = 3 V:
TE/SDTA = 1, RE/SCLK = 0, ASK/FSK = 1, fc = 868.3 MHz, CW mode
RPS / kΩ
Ω
≥ 15 k
6.8 k
3.3 k
1.0 k
ICC / mA
TBD
9.0
TBD
TBD
PO / dBm
6
0
-6
-15
Pharm / dBm
≤-36
≤-36
≤-36
≤-36
Serial Control Interface
Parameter
Symbol
Data to clock set up time
fCS
150
Data to clock hold time
tCH
50
Clock pulse width high
tCWH
100
Clock pulse width low
tCWL
100
tES
100
P
Parameter
Crystal frequency
Min
N
I
M
I
L
E
R
Clock to load enable set
up time
Crystal Parameters
Condition
Y
R
A
Max
Unit
ns
ns
ns
ns
Symbol
Condition
Min
Max
Unit
fcrystal
fundamental mode, AT
3
12
MHz
10
15
pF
Load capacitance
Cload
Static capacitance
C0
7
pF
Motional resistance
Rm
70
Ω
3901007121
Rev. 001
Page 18 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Application Circuit Examples
Programmable Channel FSK Application Circuit
VCC
RB
CB3
L0
Lock
detect
VD1
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
VEE
FS1/LD
VCC
Y
R
A
SDEN
SDTA
SCLK
RE/SCLK
N
I
M
I
L
E
R
IN_LNA
CRX0
L1
CB1
LF
CTX0
VEE
Antenna
matching
network
TNK_LO
LTX0
CB7
VCC
VEE
OUT_LNA
VCC
ASK/FSK
C1
GAIN_LNA
IN_MIX
CX2
CB5
3901007121
Rev. 001
CERRES
RSSI
OUT_DEM
XTAL
VEE
RSSI
C4
CB4
CX1
RO
C3
CERFIL
Figure 4:
INT1
INT2
IN_DEM
VCC
IN_IFA
P
OUT_DTA
FSK_SW
VEE
OUT_MIX
FSK
input
IN_DTA
C2
RP CP0
C5
FSK
output
VCC
CB0
VCC
Test circuit for programmable channel FSK operation
Page 19 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Fixed-Frequency FSK Application Circuit
VCC
RB
CB3
L0
VD1
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
VEE
FS1/LD
VCC
LF
CTX0
VEE
Antenna
matching
network
TNK_LO
LTX0
RE/SCLK
N
I
M
I
L
E
R
IN_LNA
CRX0
L1
Y
R
A
TX
enable
RX
enable
CB7
VCC
VEE
CB1
OUT_LNA
VCC
ASK/FSK
C1
GAIN_LNA
IN_MIX
CX2
CB5
Figure 5:
3901007121
Rev. 001
OUT_DTA
XTAL
VEE
RSSI
C4
CERRES
CX1
RO
C3
CERFIL
CB4
RSSI
INT1
INT2
IN_DEM
VCC
IN_IFA
P
OUT_DEM
FSK_SW
VEE
OUT_MIX
FSK
input
IN_DTA
C2
RP CP0
C5
FSK
output
VCC
CB0
VCC
Test circuit for fixed-frequency FSK operation at 868 MHz
Page 20 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
FSK test circuit component list to Fig. 4 and Fig. 5
Part
Size
Value
Tolerance
Description
@ 868.3 MHz
C0
0805
8.2 pF
±5%
VCO tank capacitor
C1
0603
NIP
±5%
LNA output tank capacitor
C2
0603
1 pF
±5%
MIX input matching capacitor
C3
0805
10 nF
±10%
data slicer capacitor
C4
0805
100 pF
±10%
C5
0805
330 pF
±10%
demodulator output low-pass capacitor,
depending on data rate
RSSI output low pass capacitor
CB0
0805
100 nF
±10%
blocking capacitor
CB1 to CB4
330 pF
±10%
blocking capacitor
CB5
0805
0603
0603
330 pF
±10%
blocking capacitor
CB6
0603
10 nF
±10%
blocking capacitor
CB7
0603
330 pF
±10%
blocking capacitor
CF1
0805
2.2 nF
±5%
loop filter capacitor
CF2
0805
100 pF
±5%
loop filter capacitor
CX1
0805
15 pF
±5%
RO capacitor
CX2
0805
33 pF
±5%
CP0
0805
10 - 12 pF
RO capacitor for FSK (∆f = ±20 kHz)
CERRES parallel capacitor
CRX0
0603
100 pF
CTX0
0603
10 pF
RB
0805
RP
0805
RF
0805
RF1
0805
RPS
0805
L0
L1
LTX0
VD1
XTAL
P
CERFIL
CERRES
0805
0603
0805
N
I
IM
±5%
Y
R
A
±5%
RX coupling capacitor
±5%
TX coupling capacitor
10 Ω
±10%
blocking resistor for VCC
3.9 KΩ
82 kΩ
±5%
CERFIL parallel resistor
L
E
R
9.1 kΩ
NIP
2.2 nH
±5%
loop filter resistor
±5%
loop filter resistor
±5%
power-select resistor, only required
at fixed-frequency operation
VCO tank inductor
±5%
10 nH
±5%
LNA output tank inductor
2.2 nH // 2.7 pF
±5%
TX impedance matching inductor
BBY-03W
SOD-323
HC49-SMD
7.1505 MHz
Leaded
type
SMD
type
SMD type
SFE10.7MFP @
BIF2 = 40 kHz
SFECV10.7MJS-A
@ BIF2 = 150 kHz
CDACV10.7MG18-A
varactor diode from Infineon
fundamental-mode crystal, Cload = 10 pF to 15pF,
C0, max = 7 pF, Rm, max = 70 Ω
±30ppm calibr.
±30ppm temp.
TBD
ceramic filter from Murata
±40 kHz
ceramic filter from Murata
ceramic demodulator tank from Murata
Notes:
• NIP – not in place, may be used optionally
• Antenna matching network according to Evaluation Board Description EVB7120
3901007121
Rev. 001
Page 21 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Programmable Channel ASK Application Circuit
VCC
RB
CB3
L0
Lock
detect
VD1
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
VEE
FS1/LD
VCC
Y
R
A
SDEN
SDTA
SCLK
RE/SCLK
N
I
M
I
L
E
R
IN_LNA
CRX0
L1
CB1
LF
CTX0
VEE
Antenna
matching
network
TNK_LO
LTX0
CB7
VCC
VEE
OUT_LNA
VCC
ASK/FSK
C1
GAIN_LNA
IN_MIX
CX2
CB5
OUT_DTA
XTAL
VEE
RSSI
CERRES
C5
CB4
3901007121
Rev. 001
CX1
RO
C3
CERFIL
Figure 6:
RSSI
INT1
INT2
IN_DEM
VCC
IN_IFA
P
OUT_DEM
FSK_SW
VEE
OUT_MIX
ASK
input
IN_DTA
C2
ASK
output
VCC
CB0
VCC
Test circuit for programmable channel ASK operation
Page 22 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Fixed-Frequency ASK Application Circuit
VCC
RB
CB3
L0
VD1
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
VEE
FS1/LD
VCC
LF
CTX0
VEE
Antenna
matching
network
TNK_LO
LTX0
RE/SCLK
N
I
M
I
L
E
R
IN_LNA
CRX0
L1
Y
R
A
TX
enable
RX
enable
CB7
VCC
VEE
CB1
OUT_LNA
VCC
ASK/FSK
C1
GAIN_LNA
IN_MIX
CX2
CB5
OUT_DTA
XTAL
VEE
RSSI
CERRES
C5
CB4
3901007121
Rev. 001
CX1
RO
C3
CERFIL
Figure 7:
RSSI
INT1
INT2
IN_DEM
VCC
IN_IFA
P
OUT_DEM
FSK_SW
VEE
OUT_MIX
ASK
input
IN_DTA
C2
ASK
output
VCC
CB0
VCC
Test circuit for fixed-frequency ASK operation at 868 MHz
Page 23 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
ASK test circuit component list to Fig. 6 and Fig. 7
Part
Size
Value
Tolerance
Description
@ 868.3 MHz
C0
0805
8.2 pF
±5%
VCO tank capacitor
C1
0603
NIP
±5%
LNA output tank capacitor
C2
0603
1 pF
±5%
MIX input matching capacitor
C3
0805
10 nF
±10%
data slicer capacitor
C5
0805
330 pF
±10%
RSSI output low pass capacitor
CB0
0805
100 nF
±10%
blocking capacitor
CB1 to CB3
330 pF
±10%
blocking capacitor
CB5
0805
0603
0603
330 pF
±10%
blocking capacitor
CB6
0603
10 nF
±10%
blocking capacitor
CB7
0603
330 pF
±10%
blocking capacitor
CF1
0805
2.2 nF
±5%
loop filter capacitor
Y
R
A
CF2
0805
100 pF
±5%
loop filter capacitor
CX1
0805
15 pF
±5%
RO capacitor
CRX0
0603
100 pF
±5%
RX coupling capacitor
CTX0
0603
10 pF
±5%
TX coupling capacitor
RB
0805
±10%
blocking resistor for VCC
RF
0805
10 Ω
9.1 kΩ
±5%
loop filter resistor
RPS
0805
NIP
±5%
L0
0805
power-select resistor, only required
at fixed-frequency operation
VCO tank inductor
L1
0603
LTX0
0805
XTAL
HC49-SMD
CERFIL
P
L
E
R
Leaded
type
SMD
type
2.2 nH
10 nH
82 nH
7.1505 MHz
SFE10.7MFP @
BIF2 = 40 kHz
SFECV10.7MJS-A
@ BIF2 = 150 kHz
N
I
IM
±5%
±5%
LNA output tank inductor
±5%
TX impedance matching inductor
±30ppm calibr.
±30ppm temp.
TBD
ceramic filter from Murata
±40 kHz
ceramic filter from Murata
fundamental-mode crystal, Cload = 10 pF to 15pF,
C0, max = 7 pF, Rm, max = 70 Ω
Notes:
• NIP – not in place, may be used optionally
• Antenna matching network according to Evaluation Board Description EVB7120
3901007121
Rev. 001
Page 24 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Programmable Channel FSK Application Circuit with AFC
VCC
RB
CB3
L0
Lock
detect
VD1
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
VEE
LF
FS1/LD
SDTA
N
I
M
I
L
E
R
VCC
VEE
OUT_LNA
Y
R
A
SDEN
RE/SCLK
IN_LNA
CRX0
L1
CB1
VCC
Antenna
matching
network
VEE
CTX0
TNK_LO
LTX0
ASK/FSK
SCLK
CB7
VCC
C1
GAIN_LNA
IN_MIX
CX2
CERRES
OUT_DTA
RSSI
XTAL
VEE
RSSI
CERFIL
Figure 8:
CX1
RO
C3
CB5
CB4
INT1
INT2
IN_DEM
VCC
IN_IFA
P
OUT_DEM
FSK_SW
VEE
OUT_MIX
FSK
input
IN_DTA
C2
R2
C4
C5
FSK
output
VCC
CP1
CB0
VD
VCC
Test circuit for programmable channel FSK operation with AFC
Circuit Features
!
!
!
!
3901007121
Rev. 001
Automatic Frequency Control (AFC)
Increases input frequency acceptance range up to RFnom ±50 kHz
Compensation of calibration tolerances of ceramic resonator
Compensation of temperature tolerances of ceramic resonator
Page 25 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Fixed-Frequency FSK Application Circuit with AFC
VCC
RB
CB3
VD1
L0
RF
RF1
RPS
FS0/SDEN
CB2
RF input
RF output
CF2
CF1
CB6
C0
OUT_PA
IN_LNA
VEE
FS1/LD
VCC
N
I
IM
CB1
OUT_LNA
L
E
R
C1
RE/SCLK
RSSI
INT1
INT2
IN_DEM
VCC
IN_IFA
VEE
CX1
RO
XTAL
VEE
C3
CB5
CERRES
FSK
input
CX2
FSK_SW
RSSI
CERFIL
Figure 9:
VCC
IN_DTA
OUT_DEM
IN_MIX
CB4
CB7
ASK/FSK
GAIN_LNA
C2
P
TX
enable
RX
enable
VCC
VEE
OUT_MIX
Y
R
A
OUT_DTA
CRX0
L1
LF
CTX0
VEE
Antenna
matching
network
TNK_LO
LTX0
R2
C4
C5
FSK
output
VCC
CP1
CB0
VD
VCC
Test circuit for fixed-frequency FSK operation at 868 MHz with AFC
Circuit Features
!
!
!
!
3901007121
Rev. 001
Automatic Frequency Control (AFC)
Increases input frequency acceptance range up to RFnom ±50 kHz
Compensation of calibration tolerances of ceramic resonator
Compensation of temperature tolerances of ceramic resonator
Page 26 of 28
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Package Dimensions
D
D1
24
17
16
25
E
e
E1
32
9
1
A
A2
b
A1
8
N
I
IM
Y
R
A
L
L
E
R
Fig. 7: LQFP32 (Low Quad Flat Package)
P
All Dimension in mm, coplanaríty < 0.1mm
E1, D1
A
min
A1
A2
0.05
1.35
7.00
max
e
b
L
0.30
0.45
0.8
1.60
0.15
1.45
E, D
α
0°
9.00
0.45
0.75
7°
0.012
0.018
0°
0.018
0.030
All Dimension in inch, coplanaríty < 0.004”
min
0.002
0.053
0.006
0.057
0.276
max
3901007121
Rev. 001
0.031
0.630
Page 27 of 28
0.354
7°
Data Sheet
Jan. 2002
TH7121
300 to 930MHz
FSK/FM/ASK Transceiver
Your Notes
Important Notice
L
E
R
N
I
IM
Y
R
A
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it
is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to
recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.
© 2000 Melexis GmbH. All rights reserved.
P
For the latest version of this document. Go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1361 1631
All other locations:
Phone: +1 603 223 2362
QS9000, VDA6.1 and ISO14001 Certified
3901007121
Rev. 001
Page 28 of 28
Data Sheet
Jan. 2002