AD AD7993

PRELIMINARY TECHNICAL DATA
4-Channel, 12-/10-Bit ADCs with I2C Compatible
Interface in 16-Lead TSSOP
AD7994/AD7993
Preliminary Technical Data
a
FEATURES
12-Bit ADC with Fast Conversion Time: 2 µs
Four Single-Ended Analog Input Channels
Specified for VDD of 2.7 V to 5.5 V
Low Power Consumption
Fast Throughput Rate:- 188 KSPS
Sequencer Operation
Automatic Cycle Mode
I2CR Compatible Serial Interface
I2CR Interface supports:
Standard, Fast, and High-Speed Modes
Out of Range Indicator/Alert Function
Pin-Selectable Addressing via AS
Two Versions Allow Five I2C Addresses
Shutdown Mode: 1µA max
16-Lead TSSOP Package
FUNCTIONAL BLOCK DIAGRAM
VDD
The AD7994/AD7993 provide a two-wire serial interface
which is compatible with I2C interfaces. The parts come
in two versions, AD7994-0/AD7993-0 to AD7994-1/
AD7993-1. Each version allows for a minimum of two
different I2C addresses. The I2C interface on the AD79940/AD7993-0 supports Standard and Fast I2C Interface
Modes. The I2C interface on the AD7994-1/AD7993-1
supports Standard, Fast and two High-Speed I2C Interface
Modes.
The AD7994/AD7993 normally remain in a shutdown
state while not converting, powering up only for conversions. The conversion process can be controlled using the
CONVST pin, an Automatic Conversion Cycle selected
through software control, or a mode where conversions
occur across Write operations. There are no pipeline delays associated with the part.
The reference for the part is applied externally to the
REFIN pin and can be in the range of 1.2V to VDD. This
allows the widest dynamic input range to the ADC.
CONVST
REFIN
AD7994/AD7993
VIN1
T/H
VIN2
I/P
MUX
VIN3
12-/10-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
VIN4
OSCILLATOR
DATALOW LIMIT
REGISTER CH1-CH4
CONVERSION
RESULT REGISTER
CONFIGURATION
REGISTER
DATAHIGH LIMIT
REGISTER CH1-CH4
ALERT
ALERT STATUS
REGISTER
HYSTERESIS
REGISTER CH1-CH4
GENERAL DESCRIPTION
The AD7994/AD7993 are 4 channel, 12-/10-bit, high
speed, low power, successive-approximation ADCs respectively. They operate from a single 2.7 V to 5.5 V
power supply and feature a conversion time of 2 µs. The
parts contain a four channel multiplexer and track/hold
amplifier which can handle input frequencies in excess of
TBD kHz.
GND
CYCLE TIMER
REGISTER
AS
I2C INTERFACE
SCL
SDA
GND
On-chip registers can be programmed with high and low
limits for the conversion result, and an open drain Out of
Range Indicator output (ALERT), becomes active when
the programmed high or low limits are violated by the
conversion result. This output can be used as an interrupt.
PRODUCT HIGHLIGHTS
1. 2 µs Conversion time with low power consumption.
2. I2C Compatible Serial Interface with pin selectable
addresses. Two AD7994/AD7993 versions allow five
AD7994/AD7993 devices to be connected to the same
serial bus.
3. The parts feature automatic shutdown while not converting to maximize power efficiency. Current consumption
is 1µA max when in shutdown.
4. Reference can be driven up to the power supply.
5. Out of Range Indicator which can be software disabled/
enabled.
6. Oneshot and automatic conversion rates.
7. No Pipeline Delay
The part features a standard successive-approximation
ADC.
SMBus is a trademark and I2C is a registered trademark of Philips Corporation
REV. PrF 09/03
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD7994–SPECIFICATIONS1 otherwise noted; T = T
(VDD = +2.7 V to +5.5 V, unless otherwise noted ; REFIN = 2.5 V; fSCL = 3.4 MHz unless
A
MIN to TMAX, unless otherwise noted.)
B Version1
Units
70
71
-78
-80
dB
dB
dB
dB
-78
-78
10
10
TBD
TBD
TBD
dB typ
dB typ
ns max
ps typ
dB typ
kHz typ
kHz typ
12
±1
±0.6
+1.5/-0.9
±0.75
±1.5
±0.5
±1.5
±0.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to REFIN
±1
30
Volts
µA max
pF typ
REFERENCE INPUT
REFIN Input Voltage Range
DC Leakage Current
Input Capacitance
Input Impedance
1.2 to VDD
±1
TBD
TBD
V min/Vmax
µA max
pF max
k⍀ typ
LOGIC
Input
Input
Input
Input
Input
0.7(V DD )
0.3(V DD )
±1
10
TBD
V min
V max
µA max
pF max
V min
2.4
2.0
0.8
0.4
±1
10
V min
V min
V max
V max
µA max
pF max
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)2
Signal to Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
INPUTS (SDA, SCL)
High Voltage, VINH
Low Voltage, VINL
Leakage Current, IIN
Capacitance, CIN2,3
Hysteresis, VHYST
LOGIC INPUT (CONVST)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN2,3
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2,3
Output Coding
Test Conditions/Comments
FIN = 10kHz Sine Wave
min
min
typ
typ
fa = TBD kHz, fb = TBD kHz
max
typ
max
typ
max
max
max
max
0.4
V max
0.6
V max
±1
µA max
TBD
pF max
Straight (Natural) Binary
FIN = TBD kHz
@ 3 dB
@ 0.1 dB
Guaranteed No Missed Codes to 12
Bits.
VIN = 0 V or VDD
VDD = 5V
VDD = 3 V
VDD = 5V
VDD = 3V
VIN = 0 V or VDD
ISINK = 3mA
ISINK = 6mA
.
–2–
REV. PrF
PRELIMINARY TECHNICAL DATA
= +2.7 V to +5.5 V, unless otherwise noted ; REF = 2.5 V; f
AD7994–SPECIFICATIONS1 (Votherwise
noted; T = T to T , unless otherwise noted.)
DD
IN
A
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Peak Current
Power Down Mode , Interface Inactive
Interface Active
Operating, Interface Inactive
Interface Active
MIN
SCL
= 3.4 MHz unless
MAX
B Version1
Units
2
TBD
TBD
3.4
13
79
µs typ
ns max
ns max
KSPS max
KSPS max
KSPS max
2.7/5.5 V
min/max
TBD
0.2/0.6
0.05/0.2
0.3/0.8
µA max
µA max
mA max
mA max
Digital Inputs = 0 V or VDD
Peak Current during conversion
VDD = 3 V/5 V.
VDD = 3 V/5 V 400 kHz SCL.
VDD = 3 V/5 V 3.4 MHz SCL.
0.06/0.15
0.3/0.6
0.15/0.35
0.6/1.4
mA
mA
mA
mA
VDD
VDD
VDD
VDD
Test Conditions/Comments
See Interface Section
max
max
max
max
Full-Scale step input
Sine wave input <= 30
Standard mode SCL =
Fast Mode SCL = 400
High-Speed Mode SCL
=
=
=
=
3
3
3
3
V/5
V/5
V/5
V/5
V
V
V
V
KHz
100 kHz
kHz
= 3.4 MHz
400 kHz SCL.
3.4 MHz SCL.
400 kHz SCL.
3.4 MHz SCL.
NOTES
1
Temperature ranges as follows: B Version: –40°C to +85°C.
2
See Terminology.
3
Sample tested @ +25°C to ensure compliance.
4
See POWER VERSUS THROUGHPUT RATE section.
Specifications subject to change without notice.
–3–
REV. PrF
PRELIMINARY TECHNICAL DATA
= +2.7 V to +5.5 V, unless otherwise noted ; REF = 2.5 V; f
AD7993–SPECIFICATIONS1 (Votherwise
noted; T = T to T , unless otherwise noted.)
DD
IN
A
MIN
B Version1
Units
61
TBD
-73
-74
dB
dB
dB
dB
-78
-78
10
10
TBD
TBD
TBD
dB typ
dB typ
ns max
ps typ
dB typ
kHz typ
kHz typ
Differential Nonlinearity 2
10
±1
±0.6
±0.9
Bits
LSB max
LSB typ
LSB max
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
Total Unadjusted Error (TUE)2
±1
±0.5
±1
±0.5
±1
LSB
LSB
LSB
LSB
LSB
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to REFIN
±1
30
Volts
µA max
pF typ
REFERENCE INPUT
REFIN Input Voltage Range
DC Leakage Current
Input Capacitance
Input Impedance
TBD/TBD
±1
TBD
TBD
V min/Vmax
µA max
pF max
k⍀ typ
LOGIC INPUTS (SDA, SCL, CONVST)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN2,3
Input Hysteresis, VHYST
0.7(V DD )
0.3(V DD )
±1
10
TBD
V min
V max
µA max
pF max
V min
2.4
2.0
0.8
0.4
±1
10
V min
V min
V max
V max
µA max
pF max
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)2
Signal to Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity2
LOGIC INPUT (CONVST)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN2,3
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2,3
Output Coding
SCL
= 3.4 MHz unless
MAX
Test Conditions/Comments
FIN = 10kHz Sine Wave
min
min
typ
typ
fa = TBD kHz, fb = TBD kHz
FIN = TBD kHz
@ 3 dB
@ 0.1 dB
Guaranteed No Missed Codes to 10
Bits.
max
max
max
max
max
0.4
V max
0.6
V max
±1
µA max
TBD
pF max
Straight (Natural) Binary
VIN = 0 V or VDD
VDD = 5V
VDD = 3 V
VDD = 5V
VDD = 3V
VIN = 0 V or VDD
ISINK = 3mA
ISINK = 6mA
.
–4–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7993–SPECIFICATIONS1 otherwise noted; T = T
(VDD = +2.7 V to +5.5 V, unless otherwise noted ; REFIN = 2.5 V; fSCL = 3.4 MHz unless
A
MIN to TMAX, unless otherwise noted.)
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
B Version1
Units
2
TBD
TBD
3.4
13
79
µs typ
ns max
ns max
KSPS max
KSPS max
KSPS max
2.7/5.5 V
min/max
TBD
0.2/0.6
0.05/0.2
0.3/0.8
mA max
µA max
mA max
mA max
Digital Inputs = 0 V or VDD
Peak Current during conversion
VDD = 3 V/5 V.
VDD = 3 V/5 V 400 kHz SCL.
VDD = 3 V/5 V 3.4 MHz SCL.
0.06/0.15
0.3/0.6
0.15/0.35
0.6/1.4
mA
mA
mA
mA
VDD
VDD
VDD
VDD
Test Conditions/Comments
See Interface Section
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Peak Current
Power Down Mode , Interface Inactive
Interface Active
Operating, Interface Inactive
Interface Active
max
max
max
max
Full-Scale step input
Sine wave input <= 30 KHz
Standard mode 100 kHz
Fast Mode 400 kHz
High-Speed Mode 3.4 MHz
=
=
=
=
3
3
3
3
V/5
V/5
V/5
V/5
V
V
V
V
400 kHz SCL.
3.4 MHz SCL.
400 kHz SCL.
3.4 MHz SCL.
NOTES
1
Temperature ranges as follows: B Version: –40°C to +85°C.
2
See Terminology.
3
Sample tested @ +25°C to ensure compliance.
4
See POWER VERSUS THROUGHPUT RATE section.
Specifications subject to change without notice.
t11
t12
t2
t6
SCL
t6
t4
t5
t3
t8
t1
t9
t10
SDA
t7
P
S
S
P
S = START CONDITION
P = STOP CONDITION
Figure 1. Two-Wire Serial Interface Timing Diagram
I2C TIMING SPECIFICATIONS1
Parameter
fSCL
t1
t2
t3
2
AD7994/AD7993
Limit at TMIN, TMAX
MIN
MAX Unit
Conditions
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
Fast Mode
High-Speed Mode
(VDD = +2.7 V to +5.5 V, unless otherwise noted ; REFIN = 2.5 V; unless otherwise noted; TA =
TMIN to TMAX, unless otherwise noted..)
100
400
3.4
1.7
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
4
0.6
60
120
4.7
1.3
160
320
250
100
10
–5–
kHz
kHz
MHz
MHz
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
Description
Serial Clock Frequency
tHIGH, SCL High Time
tLOW, SCL Low Time
tSU;DAT, Data Setup Time
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
I2C TIMING SPECIFICATIONS1 (Continued.)
Parameter Conditions
t4
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
t5
Fast Mode
High-Speed Mode
Standard Mode
t6
Fast Mode
High-Speed Mode
Standard Mode
t7
Fast Mode
t8
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
t9
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
t 10
Fast Mode
High-Speed Mode,
High-Speed Mode,
t 11
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
t 11A
Standard Mode
Fast Mode
High-Speed Mode,
High-Speed Mode,
Standard Mode
t 12
Fast Mode
High-Speed Mode,
High-Speed Mode,
t SP 4
Fast Mode
High-Speed Mode
t POWER-UP
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
CB = 100pF max
CB = 400pF max
AD7994/AD7993
Limit at TMIN, TMAX
MIN
MAX
0
3.45
0
0.9
0
70
0
150
4.7
0.6
160
4
0.6
160
4.7
1.3
4
0.6
160
1000
20 + 0.1CB 300
10
80
20
160
300
20 + 0.1CB 300
10
80
20
160
1000
20 + 0.1CB 300
10
40
20
80
1000
20 + 0.1CB 300
10
80
20
160
300
20 + 0.1CB 300
10
40
20
80
0
50
0
10
1
Unit
µs
µs
ns
ns
µs
µs
ns
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Description
t HD;DAT, Data Hold Time
tSU;STA, Set-up Time for a repeated START
Condition
t HD;STA, Hold Time (repeated) START
Condition
tBUF, Bus Free Time Between a STOP and a
START Condition.
tSU;STO, Set-up Time for STOP Condition
tRDA, Rise time of SDA signal
tFDA, Fall time of SDA signal
tRCL, Rise time of SCL signal
tRCL1, Rise time of SCL signal after a repeated START Condition and after an
Acknowledge bit.
tFCL, Fall Time of SCL signal
Pulsewidth of Spike Suppressed.
Power-up Time
NOTES
1
See Figure 1. C B refers to the capacitance load on the bus line. Hs-Mode timing specifications apply to the AD7994-1/AD7993-1 only. Standard and Fast Mode timing specifications apply to both the AD7994-0/AD7993-0 and the AD7994-1/AD7993-1.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50ns or 10ns for Fast Mode or High-Speed mode
respectivley.
Specifications subject to change without notice.
–6–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND
–0.3 V to 7 V
Analog Input Voltage to GND
–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND -0.3 V to VDD + 0.3 V
Digital Input Voltage to GND
–0.3 V to 7 V
Digital Output Voltage to GND
–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2
±10 mA
Operating Temperature Range
Commercial (B Version)
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
16-ld TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 secs)
Infared (15 secs)
+150°C
150.4°C/W (TSSOP)
27.6°C/W (TSSOP)
+215°C
+220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
ORDERING GUIDE
Model 1
AD7994BRU-0
AD7994BRU-1
AD7993BRU-0
AD7993BRU-1
Temperature Range
-40°C
-40°C
-40°C
-40°C
to
to
to
to
Linearity Error2(max) Package Option3
+85°C
+85°C
+85°C
+85°C
±1
±1
±1
±1
LSB
LSB
LSB
LSB
RU-16
RU-16
RU-16
RU-16
NOTES
1
The AD7994-0/AD7993-0 supports Standard and Fast I 2 C interface modes. The AD7994-1/AD7993-1 supports Standard, Fast and
Highspeed I 2C Interface Modes.
2
Linearity error here refers to Integral Nonlinearity
3
RU = TSSOP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7994/AD7993 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrF
–7–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
AGND
VDD
REF IN
V IN 1
V IN 3
V IN 4
V IN 2
AS
CONVST
ALERT/BUSY
SDA
SCL
Function
Analog Ground. Ground reference point for all circuitry on the AD7994/AD7993. All analog
input signals should be referred to this GND voltage.
Power Supply Input. The VDD range for the AD7994/AD7993 is from +2.7V to +5.5V.
Voltage Reference Input. The External Reference for the AD7994/AD7993 should 0.1 µF
capacitor should be placed between the REFIN pin and AGND.
Analog Input 1. Single-ended analog input channel. The input range is 0V to REFIN.
Analog Input 3. Single-ended analog input channel. The input range is 0V to REFIN.
Analog Input 4. Single-ended analog input channel. The input range is 0V to REFIN.
Analog Input 2. Single-ended analog input channel. The input range is 0V to REFIN.
Logic Input. Address Select Input which selects one of three I2C addresses for the AD7994/
AD7993 as shown in Table I.
Logic Input Signal. Convert Start Signal. This is an edge triggered logic input. The rising
edge of this signal powers up the part. The power up time for the part is 1µs. The falling
edge of CONVST places the track/hold into hold mode and initiates a conversion. A power
up time of at least 1µs must be allowed for the CONVST high pulse, otherwise the conversion result will be invalid. (See Modes of Operation Section)
Digital Output, selectable as an ALERT or BUSY output function. When configured as an
ALERT output, this pin acts as an Out of Range Indicator, and if enabled becomes active
when the conversion result violates the DATAHIGH or DATALOW values. See Limit Registers
section. When configured as a BUSY output, this pin becomes active when a conversion is in
progress.
Digital I/O. Serial Bus Bi-directional Data. Open-drain output. External pull-up resistor
required.
Digital Input. Serial Bus Clock. External pull-up resistor required.
AD7994/AD7993 PIN CONFIGURATION TSSOP
AGND
1
AGND
2
AGND
3
AGND
4
AD7994
16
AGND
15
SCL
14
SDA
TOP VIEW
13 ALERT
(Not to Scale)
12 CONVST
VDD
5
REFIN
6
11 AS
VIN1
7
10
VIN2
VIN3
8
9
VIN4
–8–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
Table I. I2C Address Selection
AS Pin
I2C Address
AD7993-0
AD7993-0
AD7993-1
AD7993-1
GND
V DD
GND
V DD
010
010
010
010
AD7993-X 1
Float
010 0000
Part Number
0001
0010
0011
0100
Note:1.
If the AS pin is left floating on any of the AD7993 parts the device address will be 010 0000
AS Pin
I2C Address
AD7994-0
AD7994-0
AD7994-1
AD7994-1
GND
V DD
GND
V DD
010
010
010
010
AD7994-X 1
Float
010 0000
Part Number
0001
0010
0011
0100
Note :1.
If the AS pin is left floating on any of the AD7994 parts the device address will be 010 0000
REV. PrF
–9–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
TERMINOLOGY
Channel-to-Channel Isolation
Signal to (Noise + Distortion) Ratio
Channel-to-Channel Isolation is a measure of the level of
crosstalk between channels. It is measured by applying a
fullscale TBD kHz sine wave signal to the nonselected
input channels and determining how much the TBD kHz
signal is attenuated in the selected channel. This figure is
This is the measured ratio of signal to (noise + distortion)
at the output of the A/D converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the
more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal Nbit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7994/
AD7993, it is defined as:
2
2
2
This is the measured interval between the leading edge of
the sampling clock and the point at which the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective
point in time at which the sample is taken.
Thus for a 12-bit converter, this is 74 dB
THD (dB ) = 20 log
given worse case across all channels.
Aperture Delay
2
2
V2 +V3 +V 4 +V5 +V 6
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4 , V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio
of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to
the rms value of the fundamental. Normally, the value
of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise
peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities
will create distortion products at sum and difference
frequencies of mfa ± nfb where m, n = 0, 1, 2, 3,
etc. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb),
while the third order terms include (2fa + fb), (2fa –
fb), (fa + 2fb) and (fa – 2fb).
The AD7994/AD7993 is tested using the CCIF standard where two input frequencies near the top end of
the input bandwidth are used. In this case, the second
order terms are usually distanced in frequency from
the original sine waves while the third order terms are
usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is
the ratio of the rms sum of the individual distortion
products to the rms amplitude of the sum of the fundamentals expressed in dBs.
Full Power Bandwidth
The Full Power Bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed Fundamental is reduced by 0.1 dB or 3 dB for a full-scale
input
PSRR (Power Supply Rejection)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200 mV p-p sine wave applied to the ADC
VDD supply of frequency fs.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs coupled into the ADC VDD supply.
Integral Nonlinearity
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a
point 1 LSB below the first code transition, and full scale,
a point 1 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 1LSB
Offset Error Match
This is the difference in offset error between any two
channels.
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., REFIN – 1
LSB) after the offset error has been adjusted out.
Gain Error Match
This is the difference in Gain error between any two channels.
–10–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
AD7994/AD7993 TYPICAL
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7994 at TBD
kSPS sample rate and TBD kHz input frequency.
TPC 1. AD7994 Dynamic Performance at TBD ksps.
TPC 2. AD7993 Dynamic Performance at TBD ksps.
TPC 3. PSRR vs Supply Ripple Frequency.
TPC 4. AD7994 SINAD vs Analog
Input Frequency for Various Supply Voltages at TBD ksps.
TPC 5. AD7994 Typical INL VDD =
5V.
TPC 6. AD7994 Typical DNL VDD =
5V.
TPC 7. AD7994 Typical INL VDD =
3V.
TPC 8. AD7994 Typical DNL VDD =
3V.
REV. PrF
–11–
TPC 9. AD7994 Change in INLvs
Reference Voltage VDD = 5V.
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
TPC 10. AD7994 Change in DNL vs
Reference Voltage.
TPC 11. AD7994 Shutdown Current vs Supply Voltage, -40 , 25 and
85 °C.
TPC 13. AD7994 Supply Current
vs Supply Voltage for Various
Temperatures.
TPC 14. AD7994 ENOB vs Reference Voltage, VDD = 3V and VDD =
5V.
–12–
TPC 12. AD7994 Supply Current vs
I2C Bus Rate for VDD = 3V and 5V.
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
CIRCUIT INFORMATION
CAPACITIVE
DAC
The AD7994/AD7993 are fast, low-power, 12-/10-bit,
single supply, 4 Channel A/D converters respectively. The
parts can be operated from a 2.7 V to 5.5 V supply.
The AD7994/AD7993 will normally remain in a powerdown state while not converting. When supplies are first
applied the part will come up in a shutdown state. Powerup is intitiated prior to a conversion and the device returns
to power-down upon completion of the conversion. Conversions can be initiated on the AD7994/AD7993 by either
pulsing the CONVST signal, using an automatic cycling
mode or using a mode where wake-up and conversion occur during the write function ( see modes of Operation
section). On completion of a conversion the AD7994/
AD7993 will enter shutdown mode again. This automatic
shutdown feature allows power saving between conversions.
This means any read or write operations across the I2C
interface can occur while the device is in shut-down.
A
VIN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
AGND
Figure 3. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7994/AD7993 is straight
binary. The designed code transitions occur at successive
integer LSB values (i.e., 1LSB, 2LSBs, etc.). The LSB
size for the AD7994 is = REFIN/4096 and REFIN/256 for
the AD7993 . The ideal transfer characteristic for the
AD7994/AD7993 is shown in Figure 4 below.
111...111
111...110
ADC CODE
The AD7994/AD7993 provide the user with a 4-channel
multiplexer, an on-chip track/hold, A/D converter, an onchip oscillator, internal data registers and an I2C compatible serial interface, all housed in a 16-lead TSSOP
package, which offers the user considerable space saving
advantages over alternative solutions. An external reference
is required by the AD7994/AD7993, and this reference can
be in the range of 1.2 V to VDD.
111...000
011...111
AD7994 1 LSB = REFIN/4096
AD7993 1 LSB = REFIN/256
000...010
000...001
000...000
AGND +1 LSB
ANALOG INPUT
0 V TO REFIN
CONVERTER OPERATION
The AD7994/AD7993 are successive approximation analog-to-digital converters based around a capacitive DAC.
Figures 2 and 3 show simplified schematics of the ADC
during its acquisition and conversion phase respectively.
Figure 2 shows the ADC during its acquisition phase.
SW2 is closed and SW1 is in position A, the comparator
is held in a balanced condition and the sampling capacitor
acquires the signal on VINX.
Figure 4. AD7994/AD7993 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 5 shows the typical connection diagram for the
AD7994/AD7993. In Figure 5 the Address Select pin,
AS, is tied to VDD, however AS can also be either tied to
GND or left floating, allowing the user to select up to
three AD7994/AD7993 devices on the same serial bus. An
external reference must be applied to the AD7994/
AD7993. This reference can be in the range of 1.2 V to
VDD. A precision reference like the REF 19X family,
ADR421, ADR03, ADR381 can be used to supply the
Reference Voltage to the ADC.
CAPACITIVE
DAC
A
VIN
CONTROL
LOGIC
SW1
B
SW2
SDA and SCL form the two-wire I2C/SMBus compatible
interface. External Pull-up resistors should be added to
the SDA and SCL bus lines.
COMPARATOR
AGND
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion, see Figure 3, SW2
will open and SW1 will move to position B causing the
comparator to become unbalanced. The input is disconnected once the conversion begins. The Control Logic
and the Capacitive DAC are used to add and subtract
fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code.
Figure 4 shows the ADC transfer function.
REV. PrF
+REFIN -1LSB
The AD7994-0/AD7993-0 support Standard and Fast I2C
Interface Modes. While the AD7994-1/AD7993-1 support
Standard, Fast and High-speed I2C Interface Modes.
Therefore if operating the AD7994/AD7993 in either
Standard or Fast Mode, up to five AD7994/AD7993 devices (3 x AD7994-0/AD7993-0 and 2 x AD7994-1/
AD7993-1 or 3 x AD7994-1/AD7993-1 and 2 x AD79940/AD7993-0) can be connected to the bus. When operating in Hs-Mode then up to three AD7994-1/AD7993-1
devices can be connected to the bus.
Wake-up from power-down prior to a conversion is approximately 1µs while conversion time is approximately
2µs. The AD7994/AD7993 enters power-down mode
again after each conversion, this will be useful in applications where power consumption is of concern.
–13–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
+5V SUPPLY
10µF
0.1µF
RP
0V to REFIN
INPUT
VIN1
VIN2
VIN3
VIN4
VDD
AD7994/
AD7993
RP
RP
TWO WIRE SERIAL
INTERFACE
SDA
µC/µP
SCL
ALERT
CON VST
REFIN
REF 19X
GND
SET TO REQUIRED
ADDRESS
AS
0.1µF
Figure 5 AD7994/AD7993 Typical Connection Diagram
Analog Input
Figure 6 shows an equivalent circuit of the analog input
sturcture of the AD7994/AD7993. The two diodes D1 and
D2 provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never
exceeds the supply rails by more than 300mV. This will
cause these diodes to become forward biased and start
conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing
irreversable damage to the part.
The capacitor C1 in Figure 6 is typically about 4pF and
can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance (RON) of a switch(track and hold switch) and also
includes the RON of the input multiplexer. The total resistance is typically about 400Ω. The capacitor C2 is the
ADC sampling capacitor and has a capacitance of 30 pF
typically.
For ac applications, removing high frequency components
from the analog input signal is recommended by use of an
RC band-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal to noise
ratio are critical the analog input should be driven from a
low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may
necessitate the use of an input buffer amplifier. The choice
of the op amp will be a function of the particular application.
maximum source impedance will depend on the amount of
total harmonic distortion (THD) that can be tolerated.
The THD will increase as the source impedance increases
and performance will degrade. Figure 7 shows a graph of
the Total Harmonic Distortion vs. analog input signal
frequency for different source impedances when using a
supply voltage of 3V±10% and 5V±10% and sampling at
a rate of xkSPS. Figure 8 shows a graph of the total harmonic distortion versus analog input signal frequency for
various supply voltages while sampling at xkSPS .
Figure 7. THD vs. Analog Input Frequency for
Various Source Impedance for VDD= 3V and 5V
When no amplifier is used to drive the analog input the
source impedance should be limited to low values. The
VDD
D1
R1
C2
16PF
VIN
C1
4PF
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
Figure 8. THD vs. Analog Input Frequency,
Fs = xkSPS
Figure 6. Equivalent Analog Input Circuit
–14–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
INTERNAL REGISTER STRUCTURE
ADDRESS POINTER REGISTER
The AD7994/AD7993 contains seventeen internal registers, as shown in Figure 9, that are used to store conversion results, high and low conversion limits, and to
configure and control the device. Sixteen are data registers
and one is an address pointer register.
The Address Pointer register itself does not have, nor does
it require, an address, as it is the register to which the first
data byte of every Write operation is written automatically.
The Address Pointer Register is an 8-bit register in which
the four LSBs are used as pointer bits to store an address
that points to one of the data registers of the AD7994/
AD7993, while the four MSBs are used as command bits
when operating in Mode 2 (see Modes of Operation section). The first byte following each write address is the
address of one of the data registers, which is stored in the
Address Pointer Register, and selects the data register to
which subsequent data bytes are written. Only the four
LSBs of this register are used to select a data register. On
Power up the Address Point register contains all 0’s,
pointing to the Conversion Result Register.
CONVERSION
RESULT REGISTER
ALERT STATUS
REGISTER
CONFIGURATION
REGISTER
CYCLE TIMER
REGISTER
Table II. Address Pointer Register
DATALOW
REGISTER CH1
DATAHIGH
REGISTER CH1
HYSTERESIS
REGISTER CH1
ADDRESS
POINTER
REGISTER
DATALOW
REGISTER CH2
C3
C2
C1
0
0
0
0
D
A
T
A
P3
P2
P1
P0
Register Select
Table III. AD7994/AD7993 Register Addresses
DATAHIGH
P3
P2
P1
P0
0
0
0
0
Conversion Result Register (Read)
0
0
0
1
Alert Status Register (Read/Write)
0
0
1
0
Configuration Register (Read/Write)
REGISTER CH3
0
0
1
1
Cycle Timer Register (Read/Write)
HYSTERESIS
REGISTER CH3
0
1
0
0
DATALOW Reg CH1 (Read/Write)
0
1
0
1
DATA HIGH Reg CH1 (Read/Write)
0
1
1
0
Hysteresis Reg CH1 (Read/Write)
REGISTER CH4
0
1
1
1
DATALOW Reg CH2 (Read/Write)
HYSTERESIS
REGISTER CH4
1
0
0
0
DATA HIGH Reg CH2 (Read/Write)
1
0
0
1
Hysteresis Reg CH2 (Read/Write)
1
0
1
0
DATALOW Reg CH3 (Read/Write)
1
0
1
1
DATA HIGH Reg CH3 (Read/Write)
1
1
0
0
Hysteresis Reg CH3 (Read/Write)
1
1
0
1
DATALOW Reg CH4 (Read/Write)
1
1
1
0
DATA HIGH Reg CH4 (Read/Write)
1
1
1
1
Hysteresis Reg CH4 (Read/Write)
REGISTER CH2
HYSTERESIS
REGISTER CH2
DATALOW
REGISTER CH3
DATAHIGH
DATALOW
REGISTER CH4
DATAHIGH
SDA
SERIAL BUS INTERFACE
SCL
Figure 9. AD7994/AD7993 Register Structure
Each data register has an address which is pointed to by
the Address Pointer register when communicating with it.
The Conversion Result Register is the only data register
that is read only.
REV. PrF
C4
–15–
Registers
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register that is used to set the operating modes of the AD7994/
AD7993. The bit functions of all 8 bits of the Configuration Register are outlined in Table IV.
Table IV.
D7
D6
D5
D4
CH4
CH3
CH2 CH1
0*
0*
0*
0*
Configuration Register Bit Function Description
D3
D2
D1
D0
FLTR ALERT EN
BUSY/ALERT
ALERT/BUSY POLARITY
1*
0*
0*
0*
*Default settings at Power-up
Bit
Mnemonic
Comment
D7-D4 CH4-CH1
These four channel address bits select the analog input channel(s) to be converted on.
A 1 in any of bits D7 to D4 selects a channel for conversion. If more than one channel bit is
set to 1 then the AD7994/AD7993 will sequence through the selected channels, starting with
the lowest channel. All unused channels should be set to zero. Table V shows how these four
channel address bits are decoded. Prior to initiating a conversion a channel(s) must be
selected in the Configuration Register.
D3
FLTR
The value written to this bit of the Control Register determines whether the filtering on SDA
and SCL is enabled or to be bypassed. If this bit is a 1 then the the filtering is enabled, if it is
a 0, then the filtering is bypassed.
D2
ALERT EN
The hardware ALERT function is enabled if this bit is set to 1 and disabled if set to 0. This bit
is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin will
act as an ALERT or a BUSY output. (See Table VI.)
D1
BUSY/ALERT This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/BUSY
output, pin 13, will act as an ALERT or BUSY output (see TABLE V1), or if pin 13 is
configured as an ALERT output pin, if it is to be reset. When reading the Configuration
registerD1 will always be a 0 when D2 is a 1.
D0
BUSY/ALERT This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is
POLARITY
configured as an ALERT or BUSY output. It is active low if this bit is set to 0, and it is active
high if set to 1.
–16–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
Table V. Channel Selection
D7
D6
D5
D4
Analog Input Channel
0
0
0
0
No channel selected, see Address Pointer Byte, Mode 2
0
0
0
1
Convert on VIN1
0
0
1
0
Convert on VIN2
0
0
1
1
Sequence between VIN1 and VIN2
0
1
0
0
Convert on VIN3
0
1
0
1
Sequence between VIN1 and VIN3
0
1
1
0
Sequence between VIN2 and VIN3
0
1
1
1
Sequence between VIN1, VIN2 and VIN3
1
0
0
0
Convert on VIN4
1
0
0
1
Sequence between VIN1 and VIN4
1
0
1
0
Sequence between VIN2 and VIN4
1
0
1
1
Sequence between VIN1, VIN2 and VIN4
1
1
0
0
Sequence between VIN3 and VIN4
1
1
0
1
Sequence between VIN1, VIN3 and VIN4
1
1
1
0
Sequence between VIN2, VIN3 and VIN4
1
1
1
1
Sequence between VIN1, VIN2, VIN3 and VIN4
Note 1:- The AD7994/AD7994 converts on the selected channel in the Sequence in ascending order, starting with the
lowest channel in the sequence.
Table VIIb. Conversion Value Register (Second Read)
Table VI. ALERT/BUSY Function
D2
D1
ALERT/BUSY Pin Configuration
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Pin does not provide any interrupt signal.
B7
B6
B5
B4
B3
B2
B1/0
B0/0
0
1
Pin configured as a BUSY output.
1
0
Pin configured as an ALERT output.
1
1
Resets ALERT output pin, Alert_Flag bit in
Conversion Result Reg, and entire Alert
Status Reg ( if any active).
The AD7994/AD7993 conversion result consists of an
Alert_Flag bit, a leading zero, two Channel Identifier bits
and the 12-/10- bit data result. For the AD7993 the two
LSBs (D1 and D0) of the second read will contain two
zeros.
The Alert_Flag bit indicates whether the conversion result
being read or any other channel result has violated the
limit registers associated with it. The Master may wish to
read the ALERT Status register to obtain more information on where the ALERT occurred if this Alert_Flag bit
is set.
This is followed by a leading zero and the two Channel
Indentifier bits indicating which channel the conversion
result corresponds to. The 12-/10-bit conversion result
then follows MSB first.
If 1/1 is written to bits D2/D1 in the configuration Register to reset the ALERT pin, the Alert Flag bit and the
Alert Status Register; the contents of the Configuration
Register will read 1/0 for D2/D1 respectively if read back.
CONVERSION RESULT REGISTER
The Conversion Result Register is a 16-bit read-only register which stores the conversion result from the ADC in
Straight Binary format. A Two Byte read is necessary to
read data from this register. Table VIIa shows the contents
of the first byte to be read while Table VIIb show the
contents of the second byte to be read from AD7994/
AD7993.
Table VIIa.
D15
D14
Conversion Value Register (First Read)
D13
Alert_Flag Zero CH
REV. PrF
ID1
D12
CH
D11
ID0
D10
D9
D8
M S B B10
B9
B8
Alert_Flag1 Zero
CH
ID1
CH
ID0
Channel# Result
0/1
0
0
0
Channel 1(V IN1)
0/1
0
0
1
Channel 2(V IN2)
0/1
0
1
0
Channel 3(V IN3)
0/1
0
1
1
Channel 4(V IN4)
–17–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
LIMIT REGISTERS
the 12-bit Hysteresis register associated with that channel.
The ALERT pin can also be reset by writing to bit D2,D1
in the Configuration Register. For the AD7993 D1 and
D0 of the DATALOW register should contain 0’s.
The AD7994/AD7993 has four pairs of limit registers,
each to store high and low conversion limits for each analog input channel. Each pair of limit registers has one
associated hysteresis register. All twelve registers are 16bits wide, only the 12 LSBs of the Registers are used for
the AD7994/AD7993, However on the AD7993 the 2
LSBs, D1 and D0, should contain 0s. On power-up, the
contents of the DATAHIGH Register for each channel will
be fullscale, while the contents of the DATALOW registers
will be zeroscale by default. The Limit Registers can be
used to monitor the conversion results on each on the
Analog input channels. The AD7994/AD7993 will signal
an Alert ( in either hardware or software or both depending on configuration) if the result moves outside the upper
or lower limit set by the limit registers.
Table IXa.
D15
DATALOW Register (First Read/Write)
D14
Alert_Flag 0
Table IXb.
D13 D12
D11
D10
D9
D8
0
B11
B10
B9
B8
0
DATALOW Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
DATA HIGH REGISTER CH1/CH2/CH3/CH4
HYSTERESIS REGISTER (CH1/CH2/CH3/CH4)
The DATAHIGH Register for each channel is a 16-bit read/
write register, only the 12 LSBs of the Register are used.
The Registers store the upper limit that will activate the
ALERT output and/or the Alert_Flag bit in the Conversion Result Register. Therefore, if the value in the Conversion Result Register is greater than the value in the
DATAHIGH Register, then the Alert_Flag bit is set to 1
and the ALERT pin is activated (the latter is true if
ALERT is enabled in the Configuration Register). When
the conversion result returns to a value at least N LSBs
below the DATAHIGH Register value the ALERT output
pin and Alert_Flag bit will be reset. The value of N is
taken from the 12-bit Hysteresis register associated with
that channel. The ALERT pin can also be reset by writing to bits D2, D1 in the Configuration Register. For the
AD7993, D1 and D0 of the DATAHIGH register should
contain 0’s.
Each Hysteresis Register is a 16-bit read/write register,
only the 12 LSBs of the register are used. The Registers
store the hysteresis value, N when using the limit registers.
Each pair of Limit registers has a dedicated hysteresis
register. The hysteresis value determines the reset point
for the ALERT pin/Alert_Flag if a violation of the limits
has occurred. If a hysteresis value of say 8 LSBs is required on the upper and lower limits of channel 1 then the
12 bit word, 0000 0000 0000 1000, should be written to
the Hysteresis Register CH1, the address of which is
shown in Table III. On power up, the Hysteresis Registers
will contain a value of 8 LSBs for the AD7994 and 2
LSBs for the AD7993. If a different hysteresis value is
required then that value must be written to the Hysteresis
Register for the channel in question. For the AD7993 D1
and D0 of the Hysteresis Register should contain 0’s.
Table Xa.
Table VIIIa.
D15
DATAHIGH Register (First Read/Write)
D14
Alert_Flag 0
D13 D12
D11
D10
D9
D8
0
B11
B10
B9
B8
0
D15
D14
Alert_Flag 0
Table Xb.
Table VIIIb.
DATAHIGH Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
Hysteresis Register (First Read/Write)
DATALOW REGISTER CH1/CH2/CH3/CH4
The DATALOW Register for each channel is a 16-bit read/
write register, of which only the 12 LSBs are used. The
Register stores the lower limit that will activate the
ALERT output and/or the Alert_Flag bit in the conversion result register. Therefore, if the value in the Conversion Result Register is less than the value in the
DATALOW Register, then the Alert_Flag bit is set to 1 and
the ALERT pin is activated (the latter is true if ALERT is
enabled in the Configuration Register). When the Conversion result returns to a value at least N LSBs above the
DATALOW Register value the ALERT ouput pin and
Alert_Flag bit will be reset. The value of N is taken from
D13 D12
D11
D10
D9
D8
0
B11
B10
B9
B8
0
Hysteresis Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
Using the Limit Registers to Store Min/Max Conversion
Results
If fullscale, i.e. all 1s, is written to the Hysteresis register
for a particular channel then the DATAHIGH and
DATALOW Registers for that channel will no longer act as
Limit registers as previously described, but instead they
will act as storage registers for the maximum and minimum conversion results returned from conversions on a
channel over any given period of time. This function is
useful in applications where the widest span of actual conversion results is required rather than using the ALERT to
signal an intervention is necessary, e.g. monitoring temperature extremes during refrigerated goods transportation. When using the limit registers to store the min and
–18–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
max conversion results, the Alert_Flag bit, D15, can be
used to indicate that an alert has happened on another one
of the Input channels.
It must be noted that on power-up, the contents of the
DATAHIGH register for each channel will be fullscale,
while the contents of the DATALOW registers will be
zeroscale, by default minimum and maximum conversion
values being stored in this way will be lost if power is
removed or cycled.
When using the limit registers to store the min and max
conversion results, the Alert_Flag bit, D15, is used to
indicate that an alert has happened on another one of the
Input channels. If the Alert_Flag bit is set to 1, it will be
reset when the Conversion result returns to a value at least
N LSBs above the DATALOW Register value or below the
DATALOW Register value or if bits D2 and D1 of the
Configuration Register are set to 1. The Alert_Flag bit in
the limit registers is useful if the user is not reading from
the conversion result register when reading the min and
max conversion results from the limit registers.
ALERT STATUS REGISTER
The Alert Status Register is a 8-bit read/write register,
which provides information on an Alert event. If a conversion results in activating the ALERT pin or the Alert_Flag
bit in the Conversion Result Register, as described in the
Limit Registers section, then the Alert Status Register may
be read to gain further information. It contains 2 status
bits per channel, one corresponding to the DATAHIGH
limit and the other to the DATALOW limit. Whichever bit
has a status of 1 will show where the violation occured, i.e.
on which channel and whether on upper or lower limit. If
a second alert event occurs on the other channel between
receiving the first alert and interrogating the Alert Status
register then the corresponding bit for that Alert event will
be set also.
The entire contents of the Alert Status register may be
cleared by writing 1,1, to bits D2 and D1 in the Configuration register as shown in Table VI. This may also be
acheived by ‘writing’ all 1’s to the Alert Status Register
itself. This means that if the Alert Status Register is addressed for a write operation which is all 1’s, then the
contents of the Alert Status Register will then be cleared
or resest to all 0’s. Alternatively, an individual active Alert
bit(s) may be reset within the Alert Status Register by
performing a write of ‘1’ to that bit alone. The advantage
of this is that once an Alert event has been serviced, that
particular bit can be reset, e.g. CH1LO, without clearing
the entire contents of the Alert Status Register, thus preserving the status of any additional Alert, e.g. CH2HI,
which may have occured while servicing the first. If it is
not necessary to clear an Alert directly after servicing then
obviously the Alert Status register may be read again immediately to look for any new Alerts, bearing in mind that
the one just serviced will still be active.
Table XIb. Alert Status Register Bit Function
Description
Bit Mnemonic Comment
D 0 CH1 LO
Violation of DATALOW limit on Channel
1 if this bit set to 1, no violation if 0.
D 1 CH1 HI
Violation of DATAHIGH limit on Chan
nel 1 if this bit set to 1, no violation if 0.
D 2 CH2 LO
Violation of DATALOW limit on Channel
2 if this bit set to 1, no violation if 0.
D 3 CH2 HI
Violation of DATAHIGH limit on Chan
nel 2 if this bit set to 1, no violation if 0.
D 4 CH3 LO
Violation of DATALOW limit on Channel
3 if this bit set to 1, no violation if 0.
D 5 CH3 HI
Violation of DATAHIGH limit on Chan
nel 3 if this bit set to 1, no violation if 0.
Violation of DATALOW limit on Channel
4 if this bit set to 1, no violation if 0.
D 6 CH4 LO
D 7 CH4 HI
Table XIa. Alert Status Register
D7
D6
D5
D4
D3
D2
D1
D0
CH4HI CH4 LO CH3HI CH3 LO CH2HI CH2 LO CH1HI CH1 LO
REV. PrF
–19–
Violation of DATAHIGH limit on Chan
nel 4 if this bit set to 1, no violation if 0.
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
CYCLE TIMER REGISTER
The Cycle Timer Register is a 8-bit read/write register,
which stores the conversion interval value for the Automatic Cycle mode of the AD7994/AD7993, see Modes of
Operation section. The five MSBs of the Cycle Timer
Register are unused and should contain 0’s at all times.
On power up, the Cycle Timer Register will contain all
0s, thus disabling the Automatic Cycle operation of the
AD7994/AD7993. To enable the Automatic Cycle Mode
the user must write to the Cycle Timer Register, selecting
the required conversion interval. Table XIIa shows the
structure of the Cycle Timer register while Table XIIb
shows how the bits in this register are decoded to provide
various automatic sampling intervals.
Table XIIa.
D7
D6
D5
Cycle Timer Register
D4
D3
D2
Sample Bit Trial 0
Dealy
Delay
0
0
Cyc Cyc
Cyc
Bit2 Bit1 Bit0
0*
0*
0*
0*
0*
0*
D1
0*
D0
0*
* Default settings on Power-up
Table XIIb.
D2 D1 D0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
TCONVERT
ADC.
Cycle Timer Intervals
Conversion Interval (typ)
0
Mode not selected
1
T CONVERT x 32
0
T CONVERT x 64
1
T CONVERT x 128
0
T CONVERT x 256
1
T CONVERT x 512
0
T CONVERT x 1024
1
T CONVERT x 2048
is equivalent to the conversion time of the
–20–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
high transition when the clock is high may be interpreted as a STOP signal.
SERIAL INTERFACE
Control of the AD7994/AD7993 is carried out via the
I2C-compatible serial bus. The AD7994/AD7993 is connected to this bus as a slave device, under the control of a
master device, e.g. the processor.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the master device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
SERIAL BUS ADDRESS
Like all I2C-compatible devices, the AD7994/AD7993 has
a 7-bit serial address. The three MSBs of this address for
the AD7994/AD7993 are set to 010. The AD7994/
AD7993 comes in two versions, the AD7994-0/AD7993-0
and AD7994-1/AD7993-1. The two versions have three
different I2C addresses available which are selected by
either tying the Address Select pin, AS, to GND, to VDD
or letting the pin float (see Table I). By giving different
addresses for the two versions, up to five AD7994/
AD7993 devices can be connected to a single serial bus,
or the addresses can be set to avoid conflicts with other
devices on the bus. See I2C Address Selection table.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
WRITING TO THE AD7994/AD7993
Depending on the register being written to, there are two
different writes for the AD7994/AD7993.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line,
SCL, remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be
written to or read from the slave device.
Writing to the Address Pointer Register for a Subsequent Read
In order to read from a particular register, the Address
Pointer register must first contain the address of that register. If it does not, the correct address must be written to
the Address pointer register by performing a single-byte
write operation, as shown in Figure 10. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data
registers. A read operation maybe subsequently performed
to read the register of interest.
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/W bit is a
0 then the master will write to the slave device. If the
R/W bit is a 1 the master will read from the slave device.
Writing a Single Byte of Data to the Alert Status Register or Cycle Register
The Configuration Register and Cycle Register are both
8-bit registers, so only one byte of data can be written to
each. Writing a single byte of data to one of these registers
consists of the serial bus write address, the chosen data
register address written to the Address Pointer Register,
followed by the data byte written to the selected data register. This is illustrated in Figure 11.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
1
Writing two Bytes of Data to a Limit Register, Hysteresis Register or Configuration register.
Each of the four Limit Registers are 12-bit registers, so
two bytes of data are required to write a value to any one
of them. Writing two bytes of data to one of these registers
consists of the serial bus write address, the chosen Limit
Register address written to the Address Pointer Register,
followed by two data bytes written to the selected data
register. This is illustrated in Figure 12.
9
1
9
SCL
SDA
0
1
0
A3
A2
A1
START BY
MASTER
A0
C4
R/9
C3
C2
C1
P3
P2
Figure 10. Writing to the Address Pointer Register to select a register for a subsequent Read operation
–21–
P0
ACK. BY
AD7994/3
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
REV. PrF
P1
ACK. BY
AD7994/3
STOP BY
MASTER
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
1
9
1
9
SCL
0
SDA
1
0
A3
A2
A1
A0
C4
R/9
START BY
MASTER
C3
C2
P3
C1
P2
P1
P0
ACK. BY
AD7994/3
ACK. BY
AD7994/3
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D3
D4
D2
D1
D0
ACK. BY
AD7994/3
STOP BY
MASTER
FRAME 3
DATA BYTE
Figure 11. Single Byte Write Sequence
1
9
1
9
SCL
0
SDA
1
0
A3
A2
A1
A0
C4
R/9
START BY
MASTER
C3
C1
P3
P2
P1
P0
ACK. BY
AD7994/3
ACK. BY
AD7994/3
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
9
C2
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
0
0
0
D11
0
D10
D9
D8
D7
ACK. BY
AD7994/3
MOST SIGNIFICANT DATA BYTE
D6
D5
D4
D3
STOP BY
MASTER
D2
D1/0
D0/0
ACK. BY
AD7994/3
STOP BY
MASTER
LEAST SIGNIFICANT DATA BYTE
Figure 12. Two Byte Write Sequence
If the master is write addressing the AD7994/AD7993 and
wishes to write to more than one register, then after the
first write operation has completed for the first data register in the next byte they can simply write to the address
pointer byte to select the next data register for a write
operation. This eliminates the need to re-address the device in order to write to another data register.
READING DATA FROM THE AD7994/AD7993
Reading data from the AD7994/AD7993 is a one or two
byte operation. Reading back the contents of the Configuration Register, Alert Status Register or the Cycle Timer
Register is a single byte read operation as shown in Figure
13. This assumes the particular register address has previously been set up by a single byte write operation to the
Address Pointer Register, Figure 10. Once the register
address has been set up, any number of reads can subsequently be performed from that particular register without
having to write to the Address Pointer Register again. If a
read from a different register is required, then the relevant
register address will have to be written to the Address
Pointer Register and again any number of reads from this
register may then be performed.
Reading data from the Conversion Result Register,
DATA HIGH Registers, DATALOW Registers or Hysteresis
Registers is a two byte operation as shown in Figure 14.
The same rules apply for a two byte read as a single byte
read.
–22–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
1
9
1
9
SCL
SDA
0
1
0
A3
A2
A1
A0
D7
R/9
START BY
MASTER
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD7994/3
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 2
SINGLE DATA BYTE FROM AD7994/3
FRAME 1
SERIAL BUS ADDRESS BYTE
Figure 13. Reading a single byte of data from a selected
register
1
9
1
9
SCL
SDA
0
1
0
A3
A2
A1
A0
Alert_
Flag
R/9
START BY
MASTER
0
D11
ACK. BY
AD7994/3
D10
D9
D8
ACK. BY
MASTER
CH ID1 CH ID0
FRAME 1
SERIAL BUS ADDRESS BYTE
1
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7994/3
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1/0
D0/0
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM
AD7994/3
Figure 14. Reading two bytes of data from the Conversion
Result Register
ALERT/BUSY PIN
device will win communication rights via standard I2C
arbitration during the slave address transfer.
The ALERT/BUSY may be configured as an Alert or
Busy ouput as shown in Table VI.
The ALERT output becomes active when the value in the
Conversion Result Register exceeds the value in the
DATAHIGH Register or falls below the value in the
DATALOW Register . It is reset when a write operation to
the Configuration register sets D1 to a 1, or when the
conversion result returns N LSBs below or above the value
stored in the DATA HIGH Register or DATALOW Register
respectively. N is the value in the Hysteresis register. (See
Limit Registers section)
SMBus ALERT
The AD7994/AD7993 ALERT output is an SMBus interrupt line for devices that want to trade their ability to
master for an extra pin. The AD7994/AD7993 is a slave
only device and uses the SMBus ALERT to signal the
host device that it wants to talk. The SMBus ALERT on
the AD7994/AD7993 is used as an out of conversion
range indicator (a limit violation indicator).
The ALERT output requires an external pull-up resistor.
This can be connected to a voltage different from VDD
provided the maximum voltage rating of the ALERT output pin is not exceeded. The value of the pull-up resistor
depends on the application, but should be as large as possible to avoid excessive sink currents at the ALERT output.
The ALERT pin has an open-drain configuration which
allows the ALERT outputs of several AD7994/AD7993
devices to be wired-AND together when the ALERT pin
is active low. D0 of the Configuration Register is used to
set the active polarity of the ALERT output. The powerup default is active low. The ALERT function can be
disabled or enabled by setting D2 of the Configuration
Register to 1 or 0 respectively.
The host device can process the ALERT interrupt and
simultaneously access all SMBus ALERT devices through
the alert response address. Only the device which pulled
the ALERT low will acknowledge the ARA (Alert Response Address). If more than one device pulls the
ALERT pin low, the highest priority (lowest address)
REV. PrF
–23–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
ure 15. The master must then issue a repeated start followed by the device Address with a R/W bit. The selected
device will then acknowledge its address.
Placing the AD7994-1/AD7993-1 into High-speed Mode.
Hs-Mode communication commences after the master
addresses all devices connected to the bus with the Master
code, 00001XXX, to indicate that a High-Speed Mode
transfer is to begin. No device connected to the bus is
allowed to Acknowledge the High-Speed Master code,
therefore the code is followed by a not-Acknowledge, Fig-
All devices continue to operate in Hs-Mode until such a
time as the master issues a STOP condition. When the
STOP condition is issued the devices all return to F/S
Mode.
HIGH-SPEED MODE
FAST MODE
1
9
1
9
SCL
0
SDA
0
0
0
1
X
X
X
0
NACK.
START BY
MASTER
1
0
A3
A2
A1
A0
Sr
ACK. BY
AD7994/3
HS-MODE MASTER CODE
SERIAL BUS ADDRESS BYTE
Figure 15. Placing the part into Hs Mode
MODES OF OPERATION
is complete, approximately 2 us later, the part will return
to shutdown (see point C Figure 16) and remain so until
the next rising edge of CONVST. The master can then
read address the ADC to obtain the conversion result. The
address point register must be pointing to the conversion
result register in order to read back the conversion result.
When supplies are first applied to the AD7994/AD7993,
the ADC powers up in shutdown mode and will normally
remain in this shutdown state while not converting. There
are three different methods of initiating a conversion on
the AD7994/AD7993.
If the CONVST pulse does not remain high for more
than 1 µs, then the falling edge of CONVST will still
initiate a conversion but the result will be invalid as the
AD7994/AD7993 will not be fully powered up when the
conversion takes place. The CONVST pin should not be
pulsed when reading from or writing to the serial port.
Mode 1 - Using CONVST Pin.
A conversion can be initiated on the AD7994/AD7993 by
pulsing the CONVST signal. The conversion clock for
the part is internally generated so no external clock is
required, except when reading from, or writing to the
serial port. On the rising edge of CONVST the AD7994/
AD7993 will begin to power up, see point A on Figure
16. The power up time from shutdown mode for the
AD7994/AD7993 is approximately 1 us, the CONVST
signal must remain high for 1 µs for the part to power up
fully. Then CONVST can be brought low after this time.
The falling edge of the CONVST signal places the track
and hold into hold mode and a conversion is also initiated
at this point, see point B Figure 16. When the conversion
A
B
The Cycle Timer Register and bits C4 - C1 in the Address Pointer Register should contain all 0’s to operate the
AD7994/AD7993 in this mode. The CONVST pin
should be tied low for all other Modes of operation. To
select an Analog Input Channel for conversion in this
mode, the user must write to the Configuration Register
and select the corresponding channel for conversion. To
set up a sequence of channels to be converted on with each
CONVST pulse, set the corresponding channel bits in
the Configuration register, see Table V.
C
tPOWER-UP
CONVST
tCONVERT
9 1
1
9
9
SCL
SDA
S
7-BIT ADDRESS
R
A
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
A
P
Figure 16. Mode 1 Operation
–24–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
see point A Figure 17. Table XIII shows the channel selection in this mode via the command bits, C4 to C1 in
the Address Pointer Register. The wake-up and conversion
time together should take approximately 3µs. Following
this, the AD7994/AD7993 must be addressed again to tell
it that a read operation is required. The read then takes
place from the Conversion Result register. This read will
access the result from the conversion selected via the command bits. If the Command bits C2, C1 were set to 1,1,
then a four byte read would be necessary. The first read
accesses the data from the conversion on VIN1. While this
read takes place, a conversion occurs on VIN2. The second
read will access this data from VIN2. Figure 18 illustrates
how this mode operates.
Mode 2 This mode allows a conversion to be automatically initiated anytime a read operation occurs. In order to use this
mode the command bits C4 - C1 in the Address Pointer
Byte shown in Table II must be programmed.
To select a particular Analog input for conversion in this
mode, then the user must set the corresponding channel
command bit to 1 in the Address Pointer Byte, see Table
XIII. When all four command bits are 0 then this mode is
not in use. A sequence can also be set up for this mode, if
more than one of the command bit in the Address Pointer
Byte are set. The ADC will start converting on the lowest
channel in the sequence and then the next lowest until all
the channels in the sequence have been converted on.
Figure 13 illustrates a two byte read operation from the
Conversion Result Register. This operation would normally be preceded by a write to the Address Pointer Register so that the following read will access the desired
register, in this case the Conversion Result Register Figure 10. When the contents of the Address Pointer Register
are being loaded, if the command bits C4 to C1 are set
then the AD7994/AD7993 will begin to power up and
convert upon the selected channel(s), power-up will begin
on the fifth SCL falling edge of the Address Point Byte,
When operating the AD7994-1/AD7993-1 in Mode2 with
Hs-Mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion
result, if this is the case the AD7994-1/AD7993-1 will
hold the SCL line low after the read address during the
ACK clock, until the conversion is complete. When the
conversion is complete the AD7994-1/AD7993-1 will
release the SCL line and the master can then read the
conversion result.
Table XIII Address Pointer Byte
C4
C3
C2
C1
P3
P2
P1
P0
Analog Input Channel
0
0
0
0
0
0
0
0
Mode 2 not selected
0
0
0
1
0
0
0
0
Mode 2 Convert on VIN1
0
0
1
0
0
0
0
0
Mode 2 Convert on VIN2
0
0
1
1
0
0
0
0
Mode 2 Sequence between VIN1 and VIN2
0
1
0
0
0
0
0
0
Mode 2 Convert on VIN3
0
1
0
1
0
0
0
0
Mode 2 Sequence between VIN1 and VIN3
0
1
1
0
0
0
0
0
Mode 2 Sequence between VIN2 and VIN3
0
1
1
1
0
0
0
0
Mode 2 Sequence between VIN1, VIN2 and VIN3
1
0
0
0
0
0
0
0
Mode 2 Convert on VIN4
1
0
0
1
0
0
0
0
Mode 2 Sequence between VIN1 and VIN4
1
0
1
0
0
0
0
0
Mode 2 Sequence between VIN2 and VIN4
1
0
1
1
0
0
0
0
Mode 2 Sequence between VIN1, VIN2 and VIN4
1
1
0
0
0
0
0
0
Mode 2 Sequence between VIN3 and VIN4
1
1
0
1
0
0
0
0
Mode 2 Sequence between VIN1, VIN3 and VIN4
1
1
1
0
0
0
0
0
Mode 2 Sequence between VIN2, VIN3 and VIN4
1
1
1
1
0
0
0
0
Mode 2 Sequence between VIN1, VIN2, VIN3 and VIN4
With the pointer bits set to all 0’s then the next read will
access the results of the conversion Result Register.
REV. PrF
–25–
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
1
8
9 1
W
A COMMAND/ADDRESS POINT BYTE A
A
9
SCL
SDA
S
7-BIT ADDRESS
ACK BY
AD7994/3
ACK BY
AD7994/3
1
9
9
9 1
SCL
SDA
Sr
7-BIT ADDRESS
R
A
A
FIRST DATA BYTE (MSBs)
ACK BY
AD7994/3R
A
SECOND DATA BYTE (LSBs)
ACK BY
MASTER
Sr/
P
NACK BY
MASTER
Figure 17. Mode 2 Operation
8
1
9 1
A
9
SCL
SDA
7-BIT ADDRESS
S
W
A COMMAND/ADDRESS POINT BYTE A
ACK BY
AD7994/3
ACK BY
AD7994/3
1
9
9
9
9
9 1
SCL
SDA
Sr
7-BIT ADDRESS
R
A
ACK BY
AD7994/3
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
ACK BY
MASTER
A
ACK BY
MASTER
RESULT FROM CH1
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
A/A
ACK BY
MASTER
RESULT FROM CH2
Figure 18. Mode 2 Sequence Operation
Mode 3 - Automatic Cycle Mode
An automatic conversion cycle can be selected and enabled
by writing a value to the Cycle Timer Register. A conversion cycle interval can be set up on the AD7994/AD7993
by programming the relevant bits in the 3-bit Cycle Timer
Register as decoded in Table XIIb. When the Cycle
Timer register is programmed with any configuration
other than all 0’s, a conversion will take place every X ms,
depending on the configuration of these bits in the Cycle
Timer Register. There are 7 different cycle time intervals
to choose from as shown in Table XIIb. Once the conversion has taken place the part powers down again until the
next conversion occurs. To exit this mode of operation the
user must program the Cycle Timer Register to contain
all 0’s. For cycle interval options see Table XIIb Cycle
Timer Intervals. To select a channel(s) for operation in
the cycle mode set the corresponding channel bit(s), D7 to
D4, of the Configuration Register. If more than one channel bit is set in the Configuration register the ADC will
automatically cycle through the Channel sequence, starting with the lowest channel and working its way up
through the sequence. Once the sequence is complete the
ADC will start converting on the lowest channel again,
continuing to loop through the sequence until the Cycle
timer register contents are set to all 0’s. This mode is
useful for monitoring signals, e.g. battery voltage, temperature etc, interrupting only when the limits are violated.
–26–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7994/AD7993
It is recommended that no I2C Bus activity occurs when a
conversion is taking place. However if this is not possible,
e.g. when operating in Mode 2 or Mode 3, then in order
to maintain the performance of the ADC, Bits D7 and D6
in the Cycle Timer Register are used to delay critical
sample intervals and bit trials from occurring while there
is activity on the I2C Bus. This will result in a quiet period for each bit decision. In certain cases where there is
excessive activity on the interface lines this may have the
effect of increasing the overall Conversion time. However
if bit trial delays extend longer than 1 µs the conversion
will terminate.
When bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism will be implemented. The
default setting of D7 and D6 is 0. To turn off both set D7
and D6 to 1.
Cycle Timer Register
D7
D6
D4
D3
D2
Sample Bit Trial 0
Dealy
Delay
0
0
Cyc Cyc Cyc
Bit2 Bit1 Bit0
0*
0*
0*
0*
0*
D5
0*
D1
D0
0*
0*
*Default settings at Power-up
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
1
0.246 (6.25)
9
0.169 (4.30)
0.177 (4.50)
16
8
0.006 (0.15)
PIN
1
0.002 (0.05)
SEATING
PLANE
REV. PrF
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–27–
8°
0°
0.028 (0.70)
0.020 (0.50)