SPT5230 10-BIT, 36 MWPS TRIPLE VIDEO DAC FEATURES APPLICATIONS • • • • • • • • • • • 10-Bit Triple Video Digital-to-Analog Converter Output Full-Scale Voltage 0.5 to 2.0 Vp-p 36 MWPS Operation (typ) Low Power: 280 mW (1 Vp-p Output) 5 V Monolithic CMOS 52-pin QFP Package (10mm x 10mm, 0.65 mm pitch) Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis GENERAL DESCRIPTION the full-scale output current. The differential linearity errors of the DACs are guaranteed to be a maximum of ±1.0 LSB over the full temperature range. The device is available in a 52lead QFP package over the commercial temperature range. The SPT5230 is a 10-bit, 36 MWPS triple video digital-toanalog converter specifically designed for high performance, high resolution color graphics monitor applications and video processing applications. A single external resistor controls BLOCK DIAGRAM GOUT ROUT AVDD CLKR VCS2 VCS1 Current Switch Cell Array (Cell 255) Current Switch Cell Array (Cell 4) VSSA Current Switch Cell Array (Cell 255) Latch Latch Latch Decoder Decoder Decoder Latch Latch Latch (MSB) DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) DBØ VCS Current Switch Cell Array (Cell 4) IOB CLKB VREF2 Current Switch Cell Array (Cell 4) Current Switch Cell Array (Cell 255) (MSB) DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1 (LSB) DGØ VREF (MSB) DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 (LSB) DRØ VREF1 BOUT IOG IOR CLKG AVDD AVDD AVDD ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 Supply Voltages AVDD (measured to AVSS) ........................... –0.3 to 7.0 V Output Current IOUT ........................................................................... 0 to 14 mA Input Voltage Clock and Data ......................................... AVSS to AVDD Temperature Operating, ambient ........................................ 0 to +70 °C Storage ................................................... –55 to + 125 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS fCLK = 27 MWPS, AVDD = 5.0 V, Output Pull-Up Load = 75 Ω, TA = 25 °C, AVSS = 0.0 V PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity Analog Outputs Output Voltage Range Conversion Rate Output Offset Voltage Signal-to-Noise Ratio Settling Time1 Propagation Delay (tpd) Crosstalk FS Control Voltage (VCS2) Digital Inputs and Timing Input Current, Logic High Logic Low Set-Up Time, Data and Controls (tS) Hold Time, Data and Controls (th) Clock Duty Cycle Power Supply Requirements Supply Voltage Supply Current Power Dissipation TEST CONDITIONS TEST LEVEL MIN TYP MAX 10.0 TA = TMIN to TMAX I I –1.0 –2.5 VCS2 = +2.1 V I I I I I V I V 3.0 27 –49 2.0 I I I I V –5 5 10 40 VIH = 5 V VIL = 0 V I IV I IV I 1 Vp-p Output 2 Vp-p Output 1 Vp-p Output 2 Vp-p Output 46 1.0 2.0 5.0 36 2.4 52 16 10 –54 14 23 12 4.0 5 60 4.75 485 5.25 56 100 280 500 UNITS Bits LSB LSB V MWPS mV dB ns ns dB V µA µA ns ns % V mA mA mW mW 1Full-scale settling time to within ±2% of full scale. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. SPT5230 2 5/1/00 INTERFACE CONSIDERATIONS CURRENT OUTPUTS Figure 4 shows a typical interface circuit of the SPT5230 in normal circuit operation. Each red, green and blue current output should have a load resistor connected to AVDD. The resistors are typically 75 Ω and should be kept in the 72 Ω to 85 Ω range. The outputs should drive a high impedance load such as a voltage follower. SUPPLY AND GROUND CONSIDERATIONS Fairchild suggests that all power supply pins (AVDD) be tied together and decoupled using a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. OUTPUT LEVEL SHIFTING CIRCUIT The SPT5230 voltage output will swing from +3.0 V to +4.99 V for VCS2 = 2.1 V as shown in table I. If level shifting of the output is desired, Fairchild recommends use of the circuit shown in figure 5. The desired –FS voltage is fed into the collector of the emitter to achieve the desired level shift. (Note the phase inversion that will occur due to the common emitter.) Choose any appropriate video op amp with adequate power supply head room. EXTERNAL REFERENCE VOLTAGE (VREF1) A +3 V (±10%) voltage reference should be externally generated for the VREF1 pin using the simple voltage divider shown in figure 4. Connect a 0.1 µF bypass capacitor between VREF1 and AVSS as close to the pin as possible. EXTERNAL REFERENCE VOLTAGE (VREF2) Table I – Binary Codes 1 LSB = 1.953 mV, VCS2 ≈ 2.1 V VREF2 needs to be externally connected to AVDD through a 1.2 kΩ (5%) resistor. Connect a 0.1 µF bypass capacitor between VREF2 and AVSS as close to the pin as possible. CONTROL VOLTAGE DECOUPLING (VCS1) Step This is a decoupling pin for the control voltage internal circuitry. An external 0.1 µF capacitor should be connected between VCS1 and AVSS as close to the pin as possible. Digital Input Analog A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Out (V) (MSB) 0 1 2 3 . . . 1022 1023 FULL-SCALE ADJUST CONTROL (VCS2) VCS2 is an external control voltage input that controls the peak-to-peak full scale output voltage. This is the only external voltage that has direct control over the SPT5230 output voltage. The voltage output swings between AVDD (+5 V) and a value controlled by VCS2. (LSB) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 . . . 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 . . . 1 1 0 1 0 1 3.000000 3.001953 3.003906 3.005859 0 4.996094 1 4.998047 Assuming that an output load resistor of 75 Ω is connected between the output and AVDD, figure 2 shows what the output voltage will be for the digital inputs all equal to logic 0, as VCS2 is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak output voltage versus VCS2 and table I shows an example in which VCS2 is equal to 2.1 V. SPT5230 3 5/1/00 Figure 1 – Timing Diagram N-Data th ts tpd 1/2 LSB N-Output Level 1/2 LSB Figure 2 – Output Voltage with All Digital Inputs = Ø versus VCS2 Figure 3 – Output Voltage (Vp-p) versus VCS2 2.5 5.0 Output Resistor = 75 Ω TA = +25 °C Digital Inputs = All Ø VREF1 = 3 V 2.0 Output Voltage (Vp-p) Output Voltage (V) (-FS) 4.5 Output Resistor = 75 Ω TA = +25 °C VREF1 = 3 V 4.0 3.5 1.5 1.0 0.5 3.0 0.0 2.5 1.5 2.0 2.5 3.0 3.5 4.0 1.5 4.5 2.0 2.5 3.0 3.5 4.0 4.5 VCS2 (V) VCS2 (V) NOTE: For Digital Inputs = All 1, Output Voltage = +4.998047 V. SPT5230 4 5/1/00 Figure 4 – Typical Interface Circuit AVDD 1.2 kΩ B5 B6 27 32 29 B1 33 28 BØ (LSB) 34 B4 CLKB 35 31 CLKG 36 30 CLKR 37 B2 AVSS 38 20 kΩ B3 AVDD VREF2 0.1 µF AVDD 0.1 µF 6 kΩ AVDD 75 Ω 1.2 kΩ 0.1 µF 75 Ω AVDD 75 Ω AVDD 0.1 µF 0.75 kΩ +5 V 10 µF AVDD 39 0.1 µF VCS2 40 26 B7 VCS1 41 25 B8 AVDD VREF1 42 24 B9 (MSB) 43 23 AVSS AVSS BOUT 44 22 N/C 45 21 GØ (LSB) AVSS GOUT 46 20 G1 47 19 G2 AVSS ROUT 48 18 G3 49 17 G4 AVSS AVDD 50 16 G5 51 15 G6 AVDD 52 14 G7 SPT5230 11 12 13 N/C G9 (MSB) G8 R1 RØ (LSB) 9 R3 R2 10 8 R5 R4 7 6 R6 5 4 R8 R7 R9 (MSB) 3 1 2 Figure 5 – Recommended Output Level Shifting Circuit AVD AVD D D 75 Ω 75 Ω 10 + DAC 1 of 3 10 Ω Out 75 Ω NOTE: All three DACs use the same circuit configuration. -FS SPT5230 5 5/1/00 PACKAGE OUTLINE 52-Lead QFP A B 39 27 40 C SYMBOL 26 INCHES MIN MAX A 0.507 0.523 13.0 13.4 B 0.386 0.394 9.9 10.1 C 0.507 0.523 13.0 13.4 D 0.386 0.394 9.9 10.1 E 0.070 0.090 1.80 2.30 F D G 0.025 typ 0.008 H 52 14 H 1 MILLIMETERS MIN MAX 0.016 0.65 typ 0.2 0.062 typ 0.4 1.6 typ I 0.004 0.008 0.1 0.2 J 0.023 0.039 0.6 1.0 J 13 I E F G SPT5230 6 5/1/00 PIN ASSIGNMENTS PIN FUNCTIONS B6 B5 B3 B4 B1 B2 CLKB BØ (LSB) CLKR CLKG AVSS AVDD VREF2 27 28 30 29 32 31 34 33 36 35 37 39 38 Name Function ROUT Red Analog Current Output GOUT Green Analog Current Output BOUT Blue Analog Current Output R0–R9 Red Data Inputs G0–G9 Green Data Inputs VCS2 40 26 B7 VCS1 41 25 B8 AVDD VREF1 AVSS 42 24 B9 (MSB) B0–B9 Blue Data Inputs 43 23 AVSS 44 22 N/C CLKR Red Clock Input BOUT 45 21 GØ (LSB) CLKG Green Clock Input AVSS 46 20 G1 GOUT AVSS 47 19 G2 CLKB Blue Clock Input 48 18 G3 VREF1 ROUT 49 17 G4 Voltage Reference Input 1 (A 0.1 µF ceramic capacitor should be used.) AVSS AVDD AVDD 50 16 G5 51 15 G6 VREF2 52 14 G7 Voltage Reference Input 2 (A 0.1 µF ceramic capacitor should be used.) VCS1 Control Voltage Decoupling (A 0.1 µF ceramic capacitor should be used.) VCS2 Full-Scale Adjust Control Voltage (A 0.1 µF ceramic capacitor should be used.) AVSS Analog Ground AVDD Analog Power Supply Voltage N/C No Connection QFP 13 12 1 1 10 8 9 6 7 4 5 3 1 2 G8 N/C G9 (MSB) RØ (LSB) R2 R1 R4 R3 R6 R5 R8 R7 R9 (MSB) ORDERING INFORMATION PART NUMBER SPT5230SCT TEMPERATURE RANGE PACKAGE 0 to +70 °C 52L QFP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT5230 7 5/1/00