HVL3224QE LCD CONTROLLER HVL3224QE LCD CONTROLLER May/30//2003 HYVIX 1 HVL3224QE LCD CONTROLLER ■ GENERAL DESCRIPTION The HYVIX-MAIN-R003, color-graphics LCD controller board displays 320-by-240 100 Pin TQFP dot graphics for 65K STN colors. A 16-bit high-speed bus interface and external high- speed SRAM write function enable efficient E 4Q 2 2 L3 V H data transfers and high-speed rewriting of data to the graphics RAM. The feature of this product is less afterimage than old product and possible 2 mode programming (pixel mode, block mode). The HVL3224QE is suitable for any midsized product, such as PDA, digital camera, GPS and DVD/VCD player. ■ FEATURES The HVL3224QE has the following features: ㆍ65K color bitmap STN-LCD display controller ㆍMax 30 frames ㆍRGB (5:6:5) format ㆍ16 bit BUS interface ㆍLess afterimage than old product ㆍMax display area (Horizontal 320 lines × Vertical 240 lines) ㆍLCD panel interface(frame, line, data 4 or 8 bits, clock(latch pulse), dispoff, bias) ㆍExternal frame memory interface (SRAM) ㆍMoving picture for the general color STN LCD panel ㆍAny size support within the max size ㆍColor inverting ㆍDisplay On/Off ㆍFlexible display resolution ㆍDisplay data writing start line and column address set ㆍPixel write and block write ㆍBias selection ㆍLogic supply (3.3V) ㆍC-MOS silicon process ㆍLow current consumption ㆍPackage (100 pin TQFP) HYVIX 2 HVL3224QE LCD CONTROLLER 59 58 57 56 55 54 53 52 51 SA7 VSS SA8 SA9 SA10 SA11 SA12 LVDD 60 65 SA0 SA6 66 LVDD 61 67 SD15 SA5 68 SD14 62 69 SD13 SA4 70 SD12 SA3 71 SD11 64 72 SD10 63 73 SD9 SA2 74 SD8 SA1 75 VSS ■ PIN ASSIGNMENT - 100 TQFP XD4 DATA8 31 96 XD3 DATA9 30 97 XD2 DATA10 29 98 XD1 DATA11 28 99 XD0 DATA12 27 100 VSS LVDD 26 HYVIX VSS 32 95 25 LVDD DATA13 XD5 DATA14 33 94 23 DATA7 24 34 XD6 DATA15 XD7 93 22 92 LVDD 35 DATA6 21 91 DATA5 ADD0 36 LVDD ADD1 DATA4 20 OFF 19 37 90 HVL65K100XA DATA3 ADD2 XCLK 18 38 89 ADD3 DATA2 17 LP WR 39 88 16 DATA1 CS FM LVDD 40 87 HIVIX DATA0 15 FR 14 41 86 RESET VSS 13 VSS CLOCK 42 85 12 CE TSTEN SD0 TP 43 84 11 OE 10 SD1 BYPASS 44 83 9 WE VSS SD2 8 45 82 CHGO SA17 7 SD3 HVDD 46 81 6 SA16 VSS SD4 5 47 80 HVDD 79 SA15 4 48 SD5 VSS 78 SA14 3 49 SD6 XPD 50 SA13 PLLTEST VSS SD7 2 LVDD 77 1 76 3 HVL3224QE LCD CONTROLLER ■ PIN DEMENSION HYVIX 4 HVL3224QE LCD CONTROLLER ■ PIN DESCRIPTION Signals PIN NO. I/O PLL TEST 1 XPD Connected Functions INPUT to N. C. For PLL Test 2 INPUT N. C. For PLL Test VSS 3 VSS GND Common Ground HVDD 4 VDD 3.3V Power Supply for logic circuits(3.3V) VSS 5 VSS GND Common Ground HVDD 6 VDD 3.3V Power Supply for logic circuits(3.3V) CHGO 7 N. C. For PLL Test VSS 8 VSS GND Common Ground BYPASS 9 INPUT N. C. For PLL Test TP 10 INPUT N. C. For Chip Debugging TSTEN 11 INPUT N. C. For Chip Debugging CLOCK 12 INPUT Main Clock RESET 13 INPUT Chip Reset CS 14 INPUT MPU LVDD 15 VDD 3.3V Power Supply for logic circuits(3.3V) WR 16 INPUT MPU Chip Write Signal ADD3 17 INPUT MPU ADD2 18 INPUT MPU External Interface Address Input ADD1 19 INPUT MPU port ADD0 20 INPUT MPU LVDD 21 VDD 3.3V DATA15 22 INPUT MPU DATA14 23 INPUT MPU DATA13 24 INPUT MPU VSS 25 VSS GND Common Ground LVDD 26 VDD 3.3V Power Supply for logic circuits(3.3V) DATA12 27 INPUT MPU DATA11 28 INPUT MPU DATA10 29 INPUT MPU DATA9 30 INPUT MPU DATA8 31 INPUT MPU LVDD 32 VDD 3.3V DATA7 33 INPUT MPU DATA6 34 INPUT MPU DATA5 DATA4 35 36 INPUT INPUT MPU MPU HYVIX External Interface Chip select, Active "0" Power Supply for logic circuits(3.3V) External Data I/O port External Data I/O port Power Supply for logic circuits(3.3V) External Data I/O port 5 HVL3224QE LCD CONTROLLER DATA3 37 INPUT MPU DATA2 38 INPUT MPU DATA1 39 INPUT MPU DATA0 40 INPUT MPU VSS 41 VSS GND CE 42 OUTPUT OE 43 OUTPUT EXT. SRAM SRAM Output Enable, Active "0" WE 44 OUTPUT EXT. SRAM SRAM Write Enable, Active "0" SA17 45 OUTPUT EXT. SRAM SA16 46 OUTPUT EXT. SRAM SA15 47 OUTPUT EXT. SRAM SA14 48 OUTPUT EXT. SRAM SA13 49 OUTPUT EXT. SRAM External Data I/O port Common Ground SRAM Chip Enable, Active "0" SRAM Address Output port VSS 50 VSS GND Common Ground LVDD 51 VDD 3.3V Power Supply for logic circuits(3.3V) SA12 52 OUTPUT EXT. SRAM SA11 53 OUTPUT EXT. SRAM SA10 54 OUTPUT EXT. SRAM SA9 55 OUTPUT EXT. SRAM SA8 56 OUTPUT EXT. SRAM VSS 57 VSS GND SA7 58 OUTPUT EXT. SRAM SA6 59 OUTPUT EXT. SRAM SA5 60 OUTPUT EXT. SRAM SA4 61 OUTPUT EXT. SRAM SA3 62 OUTPUT EXT. SRAM SA2 63 OUTPUT EXT. SRAM SA1 64 OUTPUT EXT. SRAM SA0 65 OUTPUT EXT. SRAM LVDD 66 VDD 3.3V SD15 67 BID EXT. SRAM SD14 68 BID EXT. SRAM SD13 69 BID EXT. SRAM SD12 70 BID EXT. SRAM SD11 71 BID EXT. SRAM SD10 72 BID EXT. SRAM SD9 73 BID EXT. SRAM HYVIX SRAM Address Output port Common Ground SRAM Address Output port Power Supply for logic circuits(3.3V) SRAM Data I/O port 6 HVL3224QE LCD CONTROLLER SD8 74 BID EXT. SRAM SRAM Data I/O port VSS 75 VSS GND Common Ground LVDD 76 VDD 3.3V Power Supply for logic circuits(3.3V) SD7 77 BID EXT. SRAM SD6 78 BID EXT. SRAM SD5 79 BID EXT. SRAM SD4 80 BID EXT. SRAM SD3 81 BID EXT. SRAM SD2 82 BID EXT. SRAM SD1 83 BID EXT. SRAM SD0 84 BID EXT. SRAM VSS 85 VSS GND Common Ground FR 86 OUTPUT LCM LCD Bias Signal FM 87 OUTPUT LCM LP 88 OUTPUT LCM LCD Data Signal Latch Clock XCLK 89 OUTPUT LCM LCD Data Signal Shift Clock OFF 90 OUTPUT LCM LCD OFF LVDD 91 VDD 3.3V Power Supply for logic circuits(3.3V) XD7 92 OUTPUT LCM XD6 93 OUTPUT LCM XD5 94 OUTPUT LCM XD4 95 OUTPUT LCM XD3 96 OUTPUT LCM XD2 97 OUTPUT LCM XD1 98 OUTPUT LCM XD0 99 OUTPUT LCM VSS 100 VSS GND HYVIX SRAM Data I/O port LCD Synchronous Signal for driving scanning line LCD Display Data Output port Common Ground 7 HVL3224QE LCD CONTROLLER ■ PIN CROSS REFERENCE : NUMERICAL ORDER BY PIN NUMBER PIN # PIN NAME PIN # PIN NAME PIN # PIN NAME PIN # PIN NAME 1 PLLTEST 26 VCCINT 51 VCCINT 76 VCCINT 2 XPD 27 DATA12 52 SA12 77 SD7 3 VSS 28 DATA11 53 SA11 78 SD6 4 MVDD 29 DATA10 54 SA10 79 SD5 5 VSS 30 DATA9 55 SA9 80 SD4 6 AVDD 31 DATA8 56 SA8 81 SD3 7 CHGO 32 VCCIO 57 GND 82 SD2 8 LPVSS 33 DATA7 58 SA7 83 SD1 9 BYPASS 34 DATA6 59 SA6 84 SD0 10 TP 35 DATA5 60 SA5 85 GND 11 TSTEN 36 DATA4 61 SA4 86 FR 12 CLOCK 37 DATA3 62 SA3 87 FM 13 RESET 38 DATA2 63 SA2 88 LP 14 CS 39 DATA1 64 SA1 89 XCLK 15 RD 40 DATA0 65 SA0 90 OFF 16 WR 41 GND 66 VCCIO 91 VCCIO 17 ADD3 42 CE 67 SD15 92 XD7 18 ADD2 43 OE 68 SD14 93 XD6 19 ADD1 44 WE 69 SD13 94 XD5 20 ADD0 45 SA17 70 SD12 95 XD4 21 VCCIO 46 SA16 71 SD11 96 XD3 22 DATA15 47 SA15 72 SD10 97 XD2 23 DATA14 48 SA14 73 SD9 98 XD1 24 DATA13 49 SA13 74 SD8 99 XD0 25 GND 50 GND 75 GND 100 GND HYVIX 8 HVL3224QE LCD CONTROLLER ■ FUNCTIONAL DESCRIPTION HVL3224QE receives the image pixel data from the interface (like a camera or Microprocessor) and saves it in SRAM. After that HVL3224QE brings the pixel data in order and makes it go through the unique data conversion algorithm and changes it to the proper color data through the RGB table, and then it is transmitted to color STN LCD with an address. Read Operation ▶ Read Waveform tRC Address tAA tOH RD tRHZ tOE tRLZ CS tCHZ tACE Data Out tCLZ Data Valid ▶ Read Cycle Parameter Read cycle time Address access time Chip select (CS) access time Output enable (RD) access time Output hold from address change CS Low to output in low Z CS High to output in high Z RD Low to output in low Z RD High to output in high Z HYVIX Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tRLZ tRHZ Min 10 3 0 0 - Max 10 10 5 5 5 Unit ns ns ns ns ns ns ns ns ns 9 HVL3224QE LCD CONTROLLER ◆ Write Operation ▶ Write Waveform tWC tAH tWR Address tCW CS tAS tAW tWP WR tDW Data IN tDH Data Valid tWZ Data OUT tOW Data undefined High Z ▶ Write Cycle Parameter Write cycle time Chip enable (CS) to write end Address setup to write end Address setup time Write pulse width (RD=high) Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in High-Z Output active from write end HYVIX Symbol tWC tCW tAW tAS tWP1 tWR tAH tDW tDH tWZ tOW Min 10 5 5 0 5 0 0 5 0 0 5 Max 0 5 - Unit ns ns ns ns ns ns ns ns ns ns ns 10 HVL3224QE LCD CONTROLLER ◆ LCD Interface Example HIROSE HIF3F-40PA 3.3V 3.3V FR FM LP XCLK OFF D0 D1 D2 D3 D4 D5 D6 D7 2 • Insert a 33 Ω resistance to each signal line and connect Driver • Use a thick and short signal line to each signal • Use a thick and wide GND line Step-Up Circuit (LCD Power) 39 0V 0V STN LCD 40 INVERTER 5V D R I V E R Back Light 0V LCD Interface Timing Chart LP XCLK XD0 ~ XD7 SEG SEG 944~951 952~959 SEG 0~7 SEG 8~15 #1 DATA SEG SEG 944~951 952~959 SEG 0~7 SEG 8~15 FLM LP (Reduction) 240 x T FLM (Reduction) HYVIX 11 HVL3224QE LCD CONTROLLER ■ CONTROL REGISTER DESCRIPTION Addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 LPI LPI LPI LPI LPI LPI LPI LPI Rst LPI 0x00 0x01 0x02 0x03 9 8 7 6 5 4 3 2 1 FMI FMI FMI FMI FMI FMI FMI FMI FMI 9 8 7 6 5 4 3 2 0x04 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MG Inv LPI LPW LPW LPW LPW LPW LPW 0 5 4 3 2 1 0 FMI FMW FMW FMW FMW FMW FMW 1 0 5 4 3 2 1 0 M7 M6 M5 M4 M3 M2 M1 M0 0x05 0x06 XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 0x07 YL8 YL7 YL6 YL5 YL4 YL3 YL2 YL1 YL0 0x08 X8 X7 X6 X5 X4 X3 X2 X1 X0 0x09 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 G3 G2 G1 G0 B4 B3 B2 B1 B0 0x0A R4 R3 R2 R1 R0 G5 G4 0x0B 0x0C 0x0D 0x0E 0x0F Table 2-1 LCD Decoder Registers ㆍMG : M generator function enable ㆍRst : Software Reset ㆍInv : Set by 1, The color is turned over Set by 0, The color won't be changed ㆍDoff : Screen off ㆍM7~M0 : M Configuration ㆍXL8~XL0 : Point out the color LCD horizontal resolution ㆍYL8~YL0 : Point out the color LCD vertical resolution ㆍX0~8 : Column Data address of the main frame memory ㆍY0~8 : Row Data address of the main frame memory (default) ㆍR4~R0, G5~G0, B4~B0 : RGB display data (5:6:5)bit HYVIX 12 HVL3224QE LCD CONTROLLER ■ ABSOLUTE MAXIMUM RATINGS Item Power Supply Voltage Input Voltage Symbol Limits Unit VDD -0.3 to 4.0 V VI -0.3 to VDD + 0.5 *1 V -0.3 to VDD + 0.5 *1 V Output Voltage VO Output Current/Pin IOUT ±30 mA Storage Temperature TSTG -65 to 150 ˚C *1: Possibles to use from -0.3V to 7.0V of N channel open drain bi-directional buffers, input buffer in the IDC and IDH systems and Fail Safe cells. ■ RECOMMENDED OPERATING CONDITIONS Item Power Supply Voltage Input Voltage Symbol Min. Typ. Max. Unit VDD 3.00 3.30 3.60 V VI VSS *1 V ˚C tri 50 ns Normal Input Falling Time tfa 50 ns Schmitt Input Rising Time tri 5 ms Schmitt Input Falling Time tfa 5 ms Ta Normal Input Rising Time 25 25 *2 70 85*3 Ambient Temperature 0 -40 VDD *1: Possible to use 5.25 or 5.50V of N channel open drain bi-directional buffers, input buffer in the IDC and IDH systems and Fail Safe cells. *2: The ambient temperature range is recommended for Tj = 0 to 80˚C *3: The ambient temperature range is recommented for Tj = -40 to 125˚C HYVIX 13 HVL3224QE LCD CONTROLLER ■ ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 0.3V, VSS = 0V, Ta = -40 to 85˚C) Item Symbol Quiescent Current*1 IDDS Conditions Min. Typ. Max. Unit Quiescent Conditions 170 A Input Leakage Current ILI -1 1 A Off State Leakage Current IOZ -1 1 A High Level Output Voltage VOH Low Level Output Voltage VOL High Level Input Voltage VIH1 IOH=-0.1mA(Type S), -1mA(Type M) -2mA(Type 1), -6mA(Type 2) -12mA(Type 3) VDD=Min. IOL=0.1mA(Type S), 1mA(Type M) 2mA(Type 1), 6mA(Type 2) 12mA(Type 3) VDD=Min. LVTTL Level, VDD=Max. Low Level Input Voltage VIL1 LVTTL Level, VDD=Min. Positive Trigger Voltage VT1+ LVTTL Schmitt Negative Trigger Voltage VT1- LVTTL Schmitt Hysteresis Voltage VH1 LVTTL Schmitt 0.1 V High Level Input Voltage*3 VIH3 PCI Level, VDD=Max. 1.8 V Low Level Input Voltage VIL3 High Level Output Current*3 IOH3 PCI Level, VDD=Min. PCI Response VOH=0.90V, VDD=Min. VOL=2.52V, VDD=Max. PCI Response VOH=1.80V, VDD=Min. VOL=0.65V, VDD=Max. *3 Low Level Output Current*3 *2 Pull Up Resistor Pull Down Resistor*2 IOL3 RPU RPD Low Level Reversal Current IBHLO Input Terminal Capacitance 1.1 2.4 V 0.6 1.8 V 0.9 -36 48 20 Type 2 40 mA mA 137 Type 1 V mA -115 VI = VDD CO IBHHO V V 40 CIO High Level Reversal Current V 0.8 Type 2 Input/Output Terminal Capacitance IBHL 2.0 VI = 0V Output Terminal Capacitance Low Level Maintenance Current 0.4 20 CI IBHH V -0.4 Type 1 Bus Hold Response, VIN=2.0V VDD=Min. Bus Hold Response, VIN=0.8V VDD=Min. Bus Hold Response, VIN=0.8V VDD=Max. Bus Hold Response, VIN=2.0V VDD=Max. f =1MHz, VDD=0V High Level Maintenance Current VDD mA (100) 120 k (200) 100 240 (100) 50 120 k (200) 100 240 50 -20 A 17 A -350 A 210 A 10 pF f =1MHz, VDD=0V 10 pF f =1MHz, VDD=0V 10 pF *1: The quiescent current is a typical value (Tj=85˚C) for each master. For details, please see Tables 1-9 and 1-10. *2: The values parenthesized means in case of Ta=0 to 70˚C. Values are doubled for VDD=3.3V±-0.3V, VSS=0V, and Ta=-40˚C to 85˚C. *3: Complies with Rev. 2.2 of PCI standard. HYVIX 14 HVL3224QE LCD CONTROLLER ■ TYPICAL APPLICATION ▶ PART LIST No. Qty Reference Part Mfg 1 12 C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12 104 2 2 C13, C14 100uF 16V 3 2 D1,D2 GREEN (LED) 4 1 JP1 HEADER 20X2 5 1 JP2 JUMPER 3X1 6 1 JP3 HEADER 25X2 7 1 J1 CON2 8 1 L1 BEAD FERRITE 9 1 R1 1K 10 1 R2 220 11 1 R3 470 12 1 R4 200 13 1 SW1 TAC 14 1 U1 HVL3224QE 15 1 U2 K6R4016V1C-T10 SAMSUNG 16 1 U3 EZ1117-3.3V SEMTECK 17 1 Y1 50MHz HYVIX ▶ SCHEMATIC HYVIX 15 A B C D 3.3V 5V 3 VIN U3 50MHz GND E/D C1 104 C3 104 VOUT OUT VCC 5 1 2 3 JP2 1 2 C5 104 C6 104 BEAD FERRITE L1 R4 200 3.3V 12 34 5V C7 104 C8 104 3.3V C9 104 TAC C10 104 R1 1K 3.3V C13 100uF 16V SW1 + 3.3V 3.3V SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 29 30 31 32 35 36 37 38 11 33 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 4 7 8 9 10 13 14 15 16 CLOCK GND GND VCC VCC I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 K6R4016V1C-T10 CS WE OE LB UB A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 JUMPER 2 C4 104 3 4 6 17 41 39 40 1 2 3 4 5 18 19 20 21 22 23 24 25 26 27 42 43 44 U2 + C11 104 C12 104 5V 22 23 24 27 28 29 30 31 33 34 35 36 37 38 39 40 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 3.3V 17 18 19 20 ADD3 ADD2 ADD1 ADD0 3 5 8 25 41 50 57 75 85 100 15 21 26 32 51 66 76 91 4 6 12 13 14 16 1 2 7 9 10 11 CLOCK RESET CS WR C14 100uF 16V 3.3V RST2 5V CON2 1 2 J1 3.3V 3 5 4 3 The capacitors are closely connected with each 3.3V power pin of IC. C2 104 RST1 RESET RST2 EZ1117-3.3V 2 1 Y1 CE WE OE SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 GND 1 R3 470 R2 220 HVL3224QE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD HVDD HVDD DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADD3 ADD2 ADD1 ADD0 CLOCK RESET CS WR PLLTEST XPD CHGO BYPASS TP TSTEN U1 GREEN D2 GREEN D1 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 FR FM LP XCLK OFF SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 CE OE WE 92 93 94 95 96 97 98 99 86 87 88 89 90 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 FR FM LP XCLK OFF SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 45 46 47 48 49 52 53 54 55 56 58 59 60 61 62 63 64 65 67 68 69 70 71 72 73 74 77 78 79 80 81 82 83 84 CE OE WE 42 43 44 3.3V 3.3V CS WR DATA0 DATA2 DATA4 DATA6 DATA8 DATA10 DATA12 DATA14 ADD0 ADD2 FR LP OFF XD0 XD2 XD4 XD6 2 Date: Size A4 Title Monday, June 02, 2003 Document Number STN LCD Controller (HVL3224QE) Hwasung city, Kyungki-do, Korea San 2-2, Wawoo-ri, Bongdam-eub, #610, TIC, KITI, 6FL, Suwon Univ., 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Sheet 1 1 of HYVIX Co., LTD HEADER 25X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 JP3 HEADER 20X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 JP1 1 1 Rev 1 RST1 DATA1 DATA3 DATA5 DATA7 DATA9 DATA11 DATA13 DATA15 ADD1 ADD3 XD1 XD3 XD5 XD7 FM XCLK A B 3.3V C D 3.3V