FUJITSU SEMICONDUCTOR DATA SHEET DS04-27240-1E ASSP for Power Supply Applications (Secondary Battery) DC/DC Converter IC for Charging Li-ion Battery MB39A113 ■ DESCRIPTION MB39A113 is a DC/DC converter IC of pulse width modulation (PWM) type for charging, capable of independently controlling the output voltage and output current. MB39A113 is suitable for down conversion. MB39A113 can dynamically control the charge current of the secondary battery, to keep the power constant by detecting a voltage drop in an AC adapter (dynamically-controlled charging) . MB39A113 can easily set the charge current value, making it ideal for use as a built-in charging device in products such as notebook PC. ■ FEATURES • Built-in dual constant-current control circuits • Analog control of charge current is possible. (+INE1 and +INE2 terminals) • Built-in AC adapter detection function (fixing the output in the off state when the VCC voltage is lower than the battery voltage + 0.2 V) • Possible to prevent mis-detecting of fully-charged state by constant-voltage control state detection function (CVM terminal) • Built-in overvoltage detection function of charge-voltage (OVP terminal) (Continued) ■ PACKAGE 24-pin plastic SSOP (FPT-24P-M03) MB39A113 (Continued) • Wide range of operating power-supply voltage : 8 V to 25 V • Output voltage setting accuracy : ± 0.74% (Ta = −10 °C to + 85 °C) • Built-in high accuracy current detection amplifier : ± 5% (At the input voltage difference of 100 mV) , ± 15% (At the input voltage difference of 20 mV) • Output voltage setting resistor is open to enable prevention of invalidity current at IC standby. (ICC = 0 µA Typ) • Oscillation frequency range : 100 kHz to 500 kHz • Built-in current detection amplifier with wide in-phase input voltage range : 0 V to VCC • Built-in soft-start function independent of loads • Built-in standby current function : 0 µA (Typ) • Built-in totem-pole output stage supporting P-channel MOS FETs devices 2 MB39A113 ■ PIN ASSIGNMENT (TOP VIEW) −INC2 1 24 +INC2 OUTC2 2 23 GND +INE2 3 22 CS −INE2 4 21 VCC CVM 5 20 OUT VREF 6 19 VH FB12 7 18 OVP −INE1 8 17 RT +INE1 9 16 −INE3 OUTC1 10 15 FB3 OUTD 11 14 CTL −INC1 12 13 +INC1 (FPT-24P-M03) 3 MB39A113 ■ PIN DESCRIPTION 4 Pin No. Symbol I/O Description 1 −INC2 I Current detection amplifier (Current Amp2) inverted input terminal 2 OUTC2 O Current detection amplifier (Current Amp2) output terminal 3 + INE2 I Error amplifier (Error Amp2) non-inverted input terminal 4 −INE2 I Error amplifier (Error Amp2) inverted input terminal 5 CVM O Open drain type output terminal of constant-voltage control state detection comparator (CV Comp.) 6 VREF O Reference voltage output terminal 7 FB12 O Error amplifier (Error Amp1, Error Amp2) output terminal 8 −INE1 I Error amplifier (Error Amp1) inverted input terminal 9 + INE1 I Error amplifier (Error Amp1) non-inverted input terminal 10 OUTC1 O Current detection amplifier (Current Amp1) output terminal 11 OUTD O With IC in standby mode, this terminal is set to Hi-Z to prevent loss of current through output voltage setting resistance. CTL terminal : Output “L” level at “H” level 12 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal 13 + INC1 I Current detection amplifier (Current Amp1) non-inverted input terminal 14 CTL I Power supply control terminal Setting the CTL terminal at “L” level places the IC in the standby mode. 15 FB3 O Error amplifier (Error Amp3) output terminal 16 −INE3 I Error amplifier (Error Amp3) inverted input terminal 17 RT Triangular wave oscillation frequency setting resistor connection terminal 18 OVP O Open drain type output terminal of overvoltage detection comparator (OVComp.) 19 VH O Power supply terminal for FET drive circuit. (VH = VCC−6 V) 20 OUT O External FET gate drive terminal. 21 VCC Power supply terminal for reference power supply control circuit and output circuit 22 CS Soft-start capacitor connection terminal 23 GND Ground terminal 24 + INC2 I Current detection amplifier (Current Amp2) non-inverted input terminal MB39A113 ■ BLOCK DIAGRAM <CV Comp.> − 5 CVM 18 OVP 21 VCC 20 OUT 19 VH 14 CTL + −INE1 8 OUTC1 10 +INC1 13 −INC1 12 +INE1 2.6 V VREF <Current Amp 1> + ×20 − <OV Comp.> + <Error Amp1> − − + + 1.4 V 9 0.2 V <UV Comp.> + −INE2 − 4 OUTC2 2 +INC2 24 −INC2 1 +INE2 3 <Current Amp 2> + ×20 − −INC2 (VO) <Error Amp2> <PWM Comp.> − + + + + − <OUT> Drive FB12 7 VREF VCC − 6 V <Error Amp3> −INE3 16 OUTD 11 − + + −2.5 V VH −1.5 V Bias Voltage UVLO 4.2 V VREF UVLO FB3 15 <SOFT> 4.2 V bias VREF VCC 10 µA <OSC> 500 kHz CS <REF> <CTL> 22 VREF 5.0 V CT 45 pF 17 6 23 RT VREF GND 5 MB39A113 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Output current Peak output current Power dissipation Storage temperature Symbol VCC IOUT IOUT PD TSTG Conditions VCC terminal Duty ≤ 5% (t = 1/fosc × Duty) Ta ≤ +25 °C Rating Min −55 Max 28 60 700 740* +125 Unit V mA mA mW °C * : The package are mounted on the dual-sided epoxy board (10 cm × 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Reference voltage output current VH terminal output current Symbol VCC IREF IVH VINE Input voltage VINC CTL terminal input voltage VCTL Output current IOUT Peak output current IOUT CVM terminal output voltage VCVM CVM terminal output current ICVM OVP terminal output voltage VOVP OVP terminal output current IOVP OUTD terminal output voltage VOUTD OUTD terminal output current IOUTD Oscillation frequency fosc Timing resistor RT Soft-start capacitor CS VH terminal capacitor CVH Reference voltage output capacitor CREF Operating ambient temperature Ta Conditions Min VCC terminal 8 −1 0 −INE1 to −INE3, + INE1, + INE2 terminal 0 + INC1, + INC2, −INC1, −INC2 terminal 0 0 −45 Duty ≤ 5% (t = 1/fosc × Duty) −600 0 0 0 0 0 0 100 27 −30 Value Typ 300 47 0.022 0.1 0.1 +25 Max 25 0 30 5 VCC 25 +45 +600 25 1 25 1 17 2 500 130 1.0 1.0 1.0 +85 Unit V mA mA V V V mA mA V mA V mA V mA kHz kΩ µF µF µF °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB39A113 ■ ELECTRICAL CHARACTERISTICS (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Pin No. VREF1 6 Ta = +25 °C 4.975 5.000 5.025 V VREF2 6 Ta = −10 °C to +85 °C 4.963 5.000 5.037 V Input stability Line 6 VCC = 8 V to 25 V 3 10 mV Load stability Load 6 VREF = 0 mA to −1 mA 1 10 mV Ios 6 VREF = 1 V −50 −25 −12 mA VTLH 6 VREF = 2.6 2.8 3.0 V VTHL 6 VREF = 2.4 2.6 2.8 V Hysteresis width VH 6 0.2* V Charge current ICS 22 −14 −10 −6 µA Oscillation frequency fosc 20 RT = 47 kΩ 270 300 330 kHz Frequency temperature stability ∆f/fdt 20 Ta = −30 °C to + 85 °C 1* % VIO 3, 4, 8, 9 FB12 = 2 V 1 5 mV Input bias current IB 3, 4, 8, 9 −100 −30 nA Voltage gain AV 7 DC 100* dB Frequency bandwidth BW 7 AV = 0 dB 1.3* MHz VFBH 7 4.8 5.0 V VFBL 7 0.8 0.9 V ISOURCE 7 FB12 = 2 V −120 −60 µA ISINK 7 FB12 = 2 V 2.0 4.0 mA Output voltage Reference Voltage Block [REF] Short-circuit output current UnderVoltage (VCC) Lockout Protection Circuit Block [UVLO] Soft-start Block [SOFT] Triangular Wave Oscillator Block [OSC] Conditions Min Typ Max Unit Threshold voltage Input offset voltage Error Amplifier Block [Error Amp1, Error Amp2] Value Symbol Parameter Output voltage Output source current Output sink current * : Standard design value (Continued) 7 MB39A113 (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Parameter Input current Voltage gain Frequency bandwidth Output voltage Symbol Pin No. IINE AV BW VFBH VFBL 16 15 15 15 15 15 15 16 Error Output source current ISOURCE Amplifier Output sink current ISINK Block VTH1 [Error Amp3] Threshold voltage VTH2 OUTD terminal output leak current OUTD terminal output ON resistor Input offset voltage FB3 = 2 V FB3 = 2 V FB3 = 2 V, Ta = + 25 °C FB3 = 2 V, Ta = −10 °C to + 85 °C 4.169 4.200 4.231 V OUTD = 17 V 0 1 µA RON 11 OUTD = 1 mA 35 50 Ω +3 mV 30 µA 0.2 µA µA µA 2.1 V 0.46 V 2.2 V 0.6 V VCC V 21 V/V 200 −1 MHz V mV mA µA VIO Input current I+INCL I−INCL VOUTC1 VOUTC2 VOUTC3 VOUTC4 In-phase input voltage range VCM Voltage gain AV Frequency bandwidth 11 I−INCH Current detection voltage −INE3 = 0 V DC AV = 0 dB Value Unit Min Typ Max −100 −30 nA 100* dB 1.3* MHz 4.8 5.0 V 0.8 0.9 V −120 −60 µA 2.0 4.0 mA 4.179 4.200 4.221 V ILEAK I+INCH Current Detection Amplifier Block [Current Amp1, Current Amp2] 16 Conditions BW VOUTCH Output voltage VOUTCL Output source current ISOURCE Output sink current ISINK 1, 12, + INC1 = + INC2 = −3 13, 24 −INC1 = −INC2 = 3 V to VCC + INC1 = + INC2 = 3 V to VCC, 13, 24 20 ∆VIN = −100 mV + INC1 = + INC2 = 3 V to VCC, 1, 12 0.1 ∆VIN = −100 mV + INC1 = + INC2 = 0 V, 13, 24 −180 −120 ∆VIN = −100 mV + INC1 = + INC2 = 0 V, 1, 12 −195 −130 ∆VIN = −100 mV + INC1 = + INC2 = 3 V to VCC, 2, 10 1.9 2.0 ∆VIN = −100 mV + INC1 = + INC2 = 3 V to VCC, 2, 10 0.34 0.40 ∆VIN = −20 mV + INC1 = + INC2 = 0 V, 2, 10 1.8 2.0 ∆VIN = −100 mV + INC1 = + INC2 = 0 V, 2, 10 0.2 0.4 ∆VIN = −20 mV 1, 12, 0 13, 24 + INC1 = + INC2 = 3 V to VCC, 2, 10 19 20 ∆VIN = −100 mV 2, 10 AV = 0 dB 2* 2, 10 4.7 4.9 2, 10 20 2, 10 OUTC1 = OUTC2 = 2 V −2 2, 10 OUTC1 = OUTC2 = 2 V 150 300 * : Standard design value (Continued) 8 MB39A113 (Continued) (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Parameter PWM Comparator Block [PWM Comp.] Threshold voltage Typ Max Unit VTL 7, 15 Duty cycle = 0% 1.4 1.5 V VTH 7, 15 Duty cycle = 100% 2.5 2.6 V −400* mA ISINK 20 OUT = 19 V, Duty ≤ 5% (t = 1/fosc × Duty) 400* mA ROH 20 OUT = −45 mA 6.5 9.8 Ω ROL 20 OUT = 45 mA 5.0 7.5 Ω Rise time tr1 20 OUT = 3300 pF 50* ns Fall time tf1 20 OUT = 3300 pF 50* ns VTLH 21 VCC = , −INC2 = 16.8 V 17.2 17.4 17.6 V VTHL 21 VCC = , −INC2 = 16.8 V 16.8 17.0 17.2 V VH 21 0.4* V VTLH 5 FB3 = 2.6 2.7 2.8 V VTHL 5 FB3 = 2.5 2.6 2.7 V VH 5 0.1* V ILEAK 5 CVM = 25 V 0 1 µA RON 5 CVM = 1 mA 200 400 Ω VTLH 18 FB3 = 1.3 1.4 1.5 V VTHL 18 FB3 = 1.2 1.3 1.4 V VH 18 0.1* V OVP terminal output leak current ILEAK 18 OVP = 25 V 0 1 µA OVP terminal output ON resistor RON 18 OVP = 1 mA 200 400 Ω VON 14 IC operation mode 2 25 V VOFF 14 IC standby mode 0 0.8 V ICTLH 14 CTL = 5 V 100 150 µA ICTLL 14 CTL = 0 V 0 1 µA Output voltage VH 19 VCC = 8 V to 25 V, VH = 0 mA to 30 mA VCC −6.5 VCC −6.0 VCC −5.5 V Standby current ICCS 21 CTL = 0 V 0 10 µA Power supply current ICC 21 CTL = 5 V 5 7.5 mA Output ON resistor Threshold voltage Hysteresis width Threshold voltage Hysteresis width CTL input voltage Control Block [CTL] Input current General Min Constant-voltage Hysteresis width Control State Detection Block CVM terminal output leakage current [CV Comp.] CVM terminal output ON resistor Bias Voltage Block [VH] Value OUT = 13 V, Duty ≤ 5% (t = 1/fosc × Duty) Threshold voltage Overvoltage Detection Block [OV Comp.] Conditions 20 Output sink current AC Adaptor Detection Block [UV Comp.] Pin No. ISOURCE Output source current Output Block [OUT] Symbol * : Standard design value 9 MB39A113 ■ TYPICAL CHARACTERISTICS 5 4 3 2 Ta = +25 °C CTL = 5 V 1 0 0 5 10 15 20 25 1000 900 800 700 600 500 400 300 200 100 0 ICTL 5 15 25 20 Reference Voltage vs. Load Current 6 Reference voltage VREF (V) 6 5 4 3 2 Ta = +25 °C CTL = 5 V VREF = 0 mA 1 0 0 5 10 15 20 Ta = +25 °C VCC = 19 V CTL = 5 V 5 4 3 2 1 0 25 0 5 10 Power supply voltage VCC (V) VCC = 19 V CTL = 5 V VREF = 0 mA 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 −40 −20 0 20 40 60 80 Operating ambient temperature Ta ( °C) 20 25 30 35 Triangular Wave Oscillation Frequency vs. Power Supply Voltage 100 Triangular wave oscillation frequency fosc (kHz) 5.08 15 Load current IREF (mA) Reference Voltage vs. Operating Ambient Temperature Reference voltage VREF (V) 10 CTL terminal input voltage VCTL (V) Reference Voltage vs. Power Supply Voltage Reference voltage VREF (V) VREF 0 Power supply voltage VCC (V) 10 9 8 7 6 5 4 3 2 1 0 Ta = +25 °C VCC = 19 V VREF = 0 mA Reference voltage VREF (V) 6 CTL Terminal Input Current, Reference Voltage vs. CTL Terminal Input Voltage CTL terminal input current ICTL (µA) Power supply current ICC (mA) Power Supply Current vs. Power Supply Voltage 340 Ta = +25 °C CTL = 5 V RT = 47 kΩ 330 320 310 300 290 280 270 260 0 5 10 15 20 25 Power supply voltage VCC (V) (Continued) 10 MB39A113 Triangular Wave Oscillation Frequency vs. Timing Resistor Triangular wave oscillation frequency fosc (kHz) 340 VCC = 19 V CTL = 5 V RT = 47 kΩ 330 320 310 300 290 280 270 260 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) 1000 Ta = +25 °C VCC = 19 V CTL = 5 V 100 10 10 100 1000 Timing resistor RT (kΩ) Error Amplifier Threshold Voltage vs. Operating Ambient Temperature Error amplifier threshold voltage VTH (V) Triangular wave oscillation frequency fosc (kHz) Triangular Wave Oscillation Frequency vs. Operating Ambient Temperature 4.25 VCC = 19 V CTL = 5 V 4.24 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) (Continued) 11 MB39A113 Error Amplifier, Gain and Phase vs. Frequency Ta = +25 °C VCC = 19 V 180 40 30 AV 0 −10 −90 −20 Phase ϕ (deg) 10 0 240 kΩ 90 ϕ 10 kΩ 1 µF + Gain AV (dB) 20 IN 8 2.4 kΩ (4) 9 10 kΩ (3) −30 − 7 + + OUT CS Error Amp1 (Error Amp2) −180 −40 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) Error Amplifier, Gain and Phase vs. Frequency Ta = +25 °C VCC = 19 V 180 40 30 ϕ AV 0 −10 −90 −20 Phase ϕ (deg) 10 0 240 kΩ 90 10 kΩ 1 µF + Gain AV (dB) 20 16 2.4 kΩ IN 10 kΩ − 15 + + OUT Error Amp3 −30 CS 4.2 V −180 −40 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) Current Detection Amplifier, Gain and Phase vs. Frequency 180 40 AV 30 ϕ 0 0 −10 −90 −20 IN 10 kΩ VCC = 19 V 13 + (24) 12 − (1) 10 (2) OUT 12.6 V Current Amp1 (Current Amp2) −30 −180 −40 100 10 kΩ 1 µF + Gain AV (dB) 10 Phase ϕ (deg) 90 20 1k 10 k 100 k 1M 10 M Frequency f (Hz) (Continued) 12 MB39A113 (Continued) Power dissipation PD (mW) Power Dissipation vs. Operating Ambient Temperature 800 740 700 600 500 400 300 200 100 0 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) 13 MB39A113 ■ FUNCTIONAL DESCRIPTION 1. DC/DC Converter Block (1) Reference voltage block (REF) The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) using the voltage supplied from the VCC terminal (pin 21) . The voltage is used as the reference voltage for the IC’s internal circuit. The reference voltage can be used to supply a load current of up to 1 mA to an external device through the VREF terminal (pin 6) . (2) Triangular wave oscillator block (OSC) The triangular wave oscillator block has built-in a frequency setting capacitor, and generates the triangular wave oscillation waveforms by connecting the frequency setting resistor with the RT terminal (pin 17) . The triangular wave is input to the IC’s internal PWM comparator. (3) Error amplifier block (Error Amp1) The error amplifier (Error Amp1) detects voltage drop of the AC adaptor and a PWM control signal is output. By connecting a feedback resistor and capacitor between FB12 terminal (pin 7) and −INE1 terminal (pin 8) , it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 22) . The use of error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. (4) Error amplifier block (Error Amp2) The error amplifier detects output signal of current detection amplifier (Current Amp2) and outputs PWM control signal by comparison with +INE2 terminal (pin 3) , also controls charge current. By connecting a feedback resistor and capacitor between FB12 terminal (pin 7) and −INE2 terminal (pin 4) , it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 22) . The use of error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. (5) Error amplifier block (Error Amp3) The error amplifier (Error Amp3) detects the DC/DC converter output voltage and outputs PWM control signals. An arbitrary output voltage can be set for 1 to 4 cells by connecting external output voltage setting resistors to the error amplifier inverting input pins. By connecting a feedback resistor and capacitor between FB3 terminal (pin15) and −INE3 terminal (pin 16) , it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS terminal (pin 22) . The use of error amplifier for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load. 14 MB39A113 (6) Current detection amplifier block (Current Amp1) The current detection amplifier (Current Amp1) detects voltage drop which occurs between both ends of the output sense resistor (RS) due to the flow of the charge current, using the +INC1 terminal (pin 13) and −INC1 terminal (pin 12) . Then it outputs the signal amplifier by 20 times to the error amplifier (Error Amp1) at the next stage. (7) Current detection amplifier block (Current Amp2) The current detection amplifier (Current Amp2) detects voltage drop which occurs between both ends of the output sense resistor (RS) due to the flow of the charge current, using the +INC2 terminal (pin 24) and −INC2 terminal (pin 1) . Then it outputs the signal amplified by 20 times to the error amplifier (Error Amp2) at the next stage. (8) PWM comparator block (PWM Comp.) The PWM comparator circuit is a voltage-to-pulse width modulator that controls the output duty depending on the output voltage of error amplifier (Error Amp1 to Error Amp3) . The PWM comparator circuit compares the triangular wave generated by the triangular wave oscillator to the error amplifier output voltage and turns on the external output transistor during the interval in which the triangular wave voltage is lower than the error amplifier output voltage. (9) Output block (OUT) The output circuit uses a totem-pole configuration capable of driving an external P-channel MOS FET. The output “L” level sets the output amplitude to 6 V (Typ) using the voltage generated by the bias voltage block (VH) . This results in increasing conversion efficiency and suppressing the withstand voltage of the connected external transistor in a wide range of input voltages. (10) Power supply control block (CTL) Setting the CTL terminal (pin 14) low places the IC in the standby mode. (The supply current is 10 µA at maximum in the standby mode.) CTL function table CTL Power L OFF (Standby) H ON (Active) (11) Bias voltage block (VH) The bias voltage circuit outputs VCC−6 V (Typ) as the minimum potential of the output circuit. In the standby mode, this circuit outputs the potential equal to VCC. 15 MB39A113 2. Protection Functions (1) Under-voltage lockout protection circuit (UVLO) The transient state of when the power supply (VCC) is turned on or a momentary decrease in supply voltage/ internal reference voltage (VREF) may cause malfunctions in the control IC, resulting in breakdown or degradation of the system. To prevent such malfunctions, the under-voltage lockout protection circuit detects an internal reference voltage drop and fixes OUT terminal (pin 20) to “H” level. The system restores when the internal reference voltage reaches the threshold voltage of the under-voltage lockout protection circuit. Protection circuit (UVLO) operation function table At UVLO operating (VREF voltage is lower than UVLO threshold voltage.) OUTD OUT CS CVM Hi-Z H L H OVP H (2) AC adapter detection block (UV Comp.) This block detects that power-supply voltage (VCC) is lower than the battery voltage + 0.2 V (Typ) , and the OUT terminal (pin 18) fixed at the “H” level. The system restores voltage supply when the supply voltage reaches the threshold voltage of the AC adapter detection block. Protection circuit (UV Comp.) operation function table At UV Comp. operating (VCC voltage is lower than UV Comp. threshold voltage.) OUTD OUT CS L H L 3. Soft-start Function Soft-start block (SOFT) Connecting a capacitor to the CS terminal (pin 22) prevents rush currents from flowing upon activation of the power supply. Using the error amplifier to detect a soft-start allows to soft-start at constant setting time intervals independent of the output load of the DC/DC converter. 4. Detection Function (1) Constant-voltage control state detection block (CV Comp.) Error amplifier (Error Amp3) detects the voltage at FB3 (pin 15) falling to or below 2.6 V (Typ) and outputs “L” level to the constant-voltage control state detection block output terminal (CVM, pin 5). (2) Overvoltage detection block (OV Comp.) Error amplifier (Error Amp3) detects the voltage at FB3 (pin 15) falling to or below 1.3 V (Typ) and outputs “H” level to the overvoltage detection block output terminal (OVP, pin 18). 16 MB39A113 ■ SETTING THE CHARGING VOLTAGE The charge voltage (DC/DC output voltage) can be set by connecting an external output voltage setting resistors (R3, R4) to the −INE3 terminal (pin 16) . Select a resistor value at which the on-resistor (35 Ω at 1 mA) of the built-in FET connected to the OUTD terminal (pin 11) can be ignored. Charge voltage of battery : VO VO (V) = (R3 + R4) /R4 × 4.2 (V) B VO R3 <Error Amp3> −INE3 16 R4 11 − + + 4.2 V OUTD 22 CS ■ SETTING THE CHARGING CURRENT The charge current value (output limit current) can be set depending on the voltage value at the +INE2 terminal (pin 3) . If a current exceeding the set current value attempts to flow, the charge voltage drops according to the set current value. Battery charge current setting voltage : + INE2 + INE2 (V) = 20 × I1 (A) × RS (Ω) ■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency is determined by the timing resistor (RT) connected to the RT terminal (pin 17) . Triangular wave oscillation frequency : fosc fosc (kHz) =: 14100/RT (kΩ) 17 MB39A113 ■ SETTING OF SOFT-START TIME (1) Setting constant voltage mode soft-start To prevent rush currents when the IC is turned on, the IC allows soft-start using the capacitor (CS) connected to the CS terminal (pin 22) . When the CTL terminal (pin 14) is placed under “H” level and IC is activated (threshold voltage of VCC ≥ UVLO) , and Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 µA. The Error Amp output potential (FB3 terminal (pin 15)) is determined through comparison between either of the lower potentials at two non-inverting input terminals (internal reference voltage (4.2 V Typ) , CS terminal voltage), and the inverting input terminal voltage ( − INE3 terminal (pin 16)) . Within the soft-start period (CS terminal voltage < 4.2 V) , FB3 is determined by comparison between − INE3 terminal voltage and CS terminal voltage, and DC/DC converter output voltage goes up proportionately with the increase of CS terminal voltage caused by charging on the soft-start capacitor. The soft-start time is obtained from the following formula. Soft-start time : ts (time until output voltage 100%) ts (s) =: 0.42 × CS (µF) =: 4.9 V CS terminal voltage =: 4.2 V Error Amp block internal reference voltage =: 0 V Soft-start time : ts VREF 10 µA 10 µA FB3 15 −INE3 16 CS − + + 22 Error Amp3 4.2 V CS Q2 Soft-start circuit 18 UVLO MB39A113 (2) Setting constant current mode soft-start To prevent rush currents when the IC is turned on, the IC allows soft-start using the capacitor (CS) connected to the CS terminal (pin 22) . When the CTL terminal (pin 14) is placed under “H” level and IC is activated (threshold voltage of VREF ≥ UVLO) , and Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 µA. The Error Amp1 output potential (FB12 terminal (pin 7) ) is determined through comparison between either of the lower potentials at two non-inverting input terminals ( + INE1 terminal (pin 9) voltage and CS terminal voltage), and the inverting input terminal voltage ( − INE1 terminal (pin 8) ) . Within the soft-start period (CS terminal voltage < + INE1) , FB12 is determined by comparison between − INE1 terminal voltage and CS terminal voltage, and DC/DC converter output voltage goes up proportionately with the increase of CS terminal voltage caused by charging on the soft-start capacitor. The Error Amp1 output potential (FB12 terminal (pin 7) ) is determined through comparison between either of the potentials at two non-inverting input terminals ( + INE2 terminal (pin 3) ) voltage and CS terminal voltage), and the inverting input terminal voltage ( − INE2 terminal (pin 4) ) . Within the soft-start period (CS terminal voltage < + INE2) , FB12 is determined by comparison between − INE2 terminal voltage and CS terminal voltage, and DC/DC converter output voltage goes up proportionately with the increase of CS terminal voltage caused by charging on the soft-start capacitor. The soft-start time is obtained from the following formula. Soft-start time : ts (time until output voltage 100%) ts (s) =: + INE1 ( + INE2) /10 µA × CS (µF) CS terminal voltage =: 4.9 V + INE1 ( + INE2) Error Amp1 block Comparison voltage with −INE1 voltage (Error Amp2 block Comparison voltage with −INE2 voltage) =: 0 V Soft-start time : ts 19 MB39A113 VREF 10 µA FB12 −INE1 −INE2 CS 10 µA 7 Error Amp1 (Error Amp2) 8 4 − + + 22 +INE1 CS +INE2 9 3 Q2 Soft-start circuit 20 UVLO MB39A113 ■ SETTING THE DYNAMICALLY-CONTROLLED CHARGING With an external resistor connected to + INE1(pin 9), the IC enters the dynamically-controlled charging mode to reduce the charge current to keep AC adapter power constant when the partial potential point A of the AC adapter voltage (VCC) become lower the − INE2 terminal voltage. Dynamically-controlled charging setting voltage : Vth Vth (V) = (R1 + R2) /R2 × −INE1 −INE1 A VCC R1 +INE1 <Error Amp1> 8 − 9 + R2 ■ ABOUT CONSTANT-VOLTAGE CONTROL STATE DETECTION/OVERVOLTAGE DETECTION TIMING CHART In the constant-voltage control state, the CVM terminal (pin 5) of the constant-voltage control state detection block (CV Comp.) outputs “L” level, when the voltage at the FB3 terminal (pin 15) of the error amplifier (ErrorAmp 3) becomes 2.6 V (Typ) or less. When the DC/DC converter output voltage enters the state of the over-voltage higher than a setting voltage, the voltage at FB3 terminal (pin 15) of the error amplifier (Error Amp3) becomes 1.3 V (Typ) or less. As a result, the OVP terminal (pin 18) of the overvoltage detection block (OV Comp.) outputs “H” level. Both the CVM terminal and the OVP terminal are open-drain output forms : Error Amp3 FB3 2.6 V CV Comp. VTHL 2.5 V Error Amp2 Error Amp1 FB12 1.5 V 1.3 V OV Comp. VTHL CV Comp. CVM OV Comp. OVP OUT Constant current control Constant voltage control Overvoltage state 21 MB39A113 ■ ABOUT THE OPERATION TIMING CHART Error Amp2 Error Amp1 FB12 2.5V Error Amp3 FB3 1.5 V Current Amp2 OUTC2 OUT Constant voltage control 22 Constant current control AC adaptor dynamicallycontrolled charging MB39A113 ■ PROCESSING WITHOUT USING OF THE CURRENT AMP1 AND AMP2 When Current Amp is not used, connect the +INC1 terminal (pin 13), +INC2 terminal (pin 24), −INC1 terminal (pin 12), and −INC2 terminal (pin 1) to VREF, and open the OUTC1 terminal (pin 10) and OUTC2 terminal (pin 2). • Connection when Current Amp is not used 12 −INC1 +INC1 13 1 −INC2 +INC2 24 10 OUTC1 2 OUTC2 6 VREF “Open” ■ PROCESSING WITHOUT USING OF THE ERROR AMP1 AND AMP2 When Error Amp is not used, leave the FB12 terminal (pin 7) open and connect the −INE1 terminal (pin 8) and −INE2 terminal (pin 4) to GND, and connect +INE1 terminal (pin 9) and +INE2 terminal (pin 3) to VREF. • Connection when Error Amp is not used 9 3 +INE1 +INE2 8 4 −INE1 −INE2 7 FB12 6 VREF GND 23 “Open” 23 MB39A113 ■ PROCESSING WITHOUT USING OF THE CS TERMINAL When soft-start function is not used, leave the CS terminal (pin 22) open. • When no soft-start function is specified “Open” CS 24 22 MB39A113 ■ I/O EQUIVALENT CIRCUIT Reference voltage block Control block VCC 21 + − CTL 14 6 VREF ESD protection element 33.1 kΩ 37.8 kΩ ESD protection element 12.35 kΩ GND 23 GND Triangular wave oscillator block Soft-start block VREF (5.0 V) 51 kΩ Error amplifier block (Error Amp1) VCC VCC VREF (5.0 V) 22 CS 1.3 V + − −INE1 8 7 FB12 CS 17 RT GND GND GND 9 +INE1 Error amplifier block (Error Amp3) Error amplifier block (Error Amp2) VCC VCC VREF (5.0 V) VREF (5.0 V) −INE2 4 −INE3 16 FB12 CS GND CS 4.2 V 15 FB3 GND 3 +INE2 Current detection amplifier block (Current Amp2) Current detection amplifier block (Current Amp1) VCC VCC +INC1 13 +INC2 24 10 OUTC1 GND 2 OUTC2 GND 12 −INC1 1 −INC2 (Continued) 25 MB39A113 (Continued) PWM comparator block Output block VCC AC adaptor detection block VCC VCC −INC2 FB12 20 OUT CT VREF (5.0 V) FB3 VH GND GND GND Constant-voltage control state detection block Overvoltage detection block VCC VCC VREF (5.0 V) 5 CVM VREF (5.0 V) FB3 FB3 GND GND Bias voltage block Prevent inefficient current block VCC 11 OUTD 19 VH GND 26 18 OVP GND MB39A113 ■ APPRICATION EXAMPLE D2 VIN (8 V to 25 V) R4 180 kΩ R5 330 kΩ R6 30 kΩ R10 120 kΩ R7 22 kΩ R11 30 kΩ <CV Comp.> − C8 10000 pF −INE1 8 OUTC1 +INC1 −INC1 CVM 5 + 10 13 12 2.6 V VREF <Current Amp 1> + ×20 − <OV Comp.> + <Error Amp 1> OVP 18 − − + + 1.4 V +INE1 9 0.2 V − 4 C10 4700 pF R9 10 kΩ R8 100 kΩ OUTC2 +INC2 A −INC2 2 24 1 B R12 30 kΩ <UV Comp.> + −INE2 <Current Amp 2> + ×20 − −INC2 (VO) <Error Amp 2> VCC 21 <PWM Comp.> − + + + + − +INE2 C12 0.1 µF <OUT> 3 Drive FB12 R13 20 kΩ R16 200 kΩ Q2 SW R14 1 kΩ R15 120 Ω R19 100 kΩ R18 200 kΩ C1 4.7 µF C2 4.7 µF A OUT B Q1 20 7 I1 L1 VREF VH VCC − 6 V <Error Amp 3> −INE3 − + + 16 OUTD C6 1500 pF R3 330 kΩ C7 0.1 µF −2.5 V VH −1.5 V Bias Voltage 15 µH 19 + D1 C3 22 µF R27 100 kΩ VO Q3 R1 0.033 Ω C4 4.7 µF Battery 11 R17 100 kΩ UVLO 4.2 V VREF UVLO FB3 15 <SOFT> 4.2 V bias VREF VCC 10 µA CTL <OSC> 500 kHz CS <REF> <CTL> 14 22 C11 0.022 µF VREF 5.0 V CT 45 pF 17 6 RT VREF 23 GND R2 47 kΩ C9 0.1 µF 27 MB39A113 ■ PARTS LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1, Q3 Q2 Pch FET Nch FET VDS = −30 V, ID = −7.0 A VDS = 30 V, ID = 1.4 A NEC SANYO µPA2714GR MCH3401 D1, D2 Diode VF = 0.42 V (Max) , At IF = 3 A ROHM RB053L-30 L1 Inductor 15 µH 3.6 A, 50 mΩ SUMIDA CDRH104R-150 C1, C2, C4 C3 C6 C7, C9 C8 C10 C11 C12 Ceramics Condenser OS-CONTM Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 4.7 µF 22 µF 1500 pF 0.1 µF 0.01 µF 4700 pF 0.022 µF 0.1 µF 25 V 20 V 50 V 50 V 50 V 50 V 50 V 50 V TDK SANYO TDK TDK TDK TDK TDK TDK C3225JB1E475K 20SVP22M C1608JB1H152K C1608JB1H104K C1608JB1H103K C1608JB1H472K C1608JB1H223K C1608JB1H104K R1 R2 R3, R5 R4 R6 R7 R8 R9 R10 R11, R12 R13 R14 R15 R16, R18 R17, R19 R27 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 33 mΩ 47 kΩ 330 kΩ 180 kΩ 30 kΩ 22 kΩ 100 kΩ 10 kΩ 120 kΩ 30 kΩ 20 kΩ 1 kΩ 120 Ω 200 kΩ 100 kΩ 100 kΩ 1% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% KOA ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm SL1TTE33LOF RR0816P-473-D RR0816P-334-D RR0816P-184-D RR0816P-303-D RR0816P-223-D RR0816P-104-D RR0816P-103-D RR0816P-124-D RR0816P-303-D RR0816P-203-D RR0816P-102-D RR0816P-121-D RR0816P-204-D RR0816P-104-D RR0816P-104-D Note : NEC : NEC Corporation SANYO : SANYO Electric Co., Ltd ROHM : ROHM CO., LTD. SUMIDA : Sumida Corporation TDK : TDK Corporation KOA : KOA Corporation ssm : SUSUMU CO., LTD OS-CON is a trademark of SANYO Electric Co., Ltd. 28 MB39A113 ■ SELECTION OF COMPONENTS • Pch MOS FET The P-channel MOSFET for switching use should be rated for at least + 20% more than the input voltage. To minimize continuity loss, use a FET with low RDS (ON) between the drain and source. For high input voltage and high frequency operation, on-cycle switching loss will be higher so that power dissipation must be considered. In this application, the µPA2714GR (NEC products) is used. Continuity loss, on/off switching loss and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values. Continuity loss : Pc PC = ID2 × RDS (ON) × Duty On-cycle switching loss : PS (ON) PS (ON) = VD (Max) × ID × tr × fosc 6 Off-cycle switching loss : PS (OFF) PS (OFF) = VD (Max) × ID (Max) × tf × fosc 6 Total loss : PT PT = PC + PS (ON) + PS (OFF) Example) Using the µPA2714GR Setting 16.8 V Input voltage VIN = 25 V, output voltage VO = 16.8 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz, L = 15 µH, drain-source ON resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 3+ VIN−Vo tON 2L 25−16.8 2 × 15 × 10 −6 × 1 300 × 103 × 0.672 =: 3.6 A Drain current (Min) : ID (Min) ID (Min) = Io − = 3− VIN−Vo 2L tON 25−16.8 2 × 15 × 10−6 × 1 300 × 103 × 0.672 =: 2.4 A PC = ID2 × RDS (ON) × Duty = 32 × 0.018 × 0.672 =: 0.109 W 29 MB39A113 PS (ON) = VD × ID × tr × fosc 6 25 × 3 × 15 × 10−9 × 300 × 103 = 6 =: 0.056 W PS (OFF) = = VD × ID (Max) × tf × fosc 6 25 × 3.6 × 42 × 10−9 × 300 × 103 6 =: 0.189 W PT = PC + PS (ON) + PS (OFF) =: 0.109 + 0.056 + 0.189 =: 0.354 W The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W. Setting 12.6 V Input voltage VIN = 22 V, output voltage VO = 12.6 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz, L = 15 µH, drain-source ON resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 3+ VIN−Vo tON 2L 22−12.6 2 × 15 × 10−6 × 1 300 × 103 × 0.572 =: 3.6 A Drain current (Min) : ID (Min) ID (Min) = Io − = 3− VIN−Vo tON 2L 22−12.6 2 × 15 × 10 −6 =: 2.4 A PC = ID2 × RDS (ON) × Duty = 32 × 0.018 × 0.572 =: 0.093 W 30 × 1 300 × 103 × 0.572 MB39A113 PS (ON) = = =: PS (OFF) = = VD × ID × tr × fosc 6 22 × 3 × 15 × 10−9 × 300 × 103 6 0.050 W VD × ID (Max) × tf × fosc 6 22 × 3.6 × 42 × 10−9 × 300 × 103 6 =: 0.166 W PT = PC + PS (ON) + PS (OFF) =: 0.093 + 0.050 + 0.166 =: 0.309 W The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W. • Inductor In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light-load. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristic becomes worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L L≥ 2 (VIN−Vo) Io tON 16.8 V output Example) 2 (VIN (Max) −Vo) L≥ Io ≥ ≥ 2 × (25−16.8) 3 tON × 1 300 × 103 × 0.672 12.2 µH 31 MB39A113 12.6 V output Example) 2 (VIN (Max) −Vo) L≥ Io ≥ 2 × (22−12.6) 3 tON 1 × 300 × 103 × 0.572 ≥ 12.0 µH Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light-loads. So, it is necessary to determine the load level at which continuous operation becomes possible. In this application, the SUMIDA CDRH104R-150 is used. The following equation is available to obtain the load current as a continuous current condition when 15 µH is used. The load current value under continuous operating conditions : Io Io ≥ Vo 2L tOFF Example) Using the CDRH104R-150 15 µH (tolerance ± 30%) , rated current = 3.6 A 16.8 V output Vo Io ≥ tOFF 2L ≥ 16.8 2 × 15 × 10 −6 × 1 300 × 103 × (1−0.672) × (1−0.572) ≥ 0.61 A 12.6 V output Vo Io ≥ tOFF 2L ≥ 12.6 2 × 15 × 10 −6 × 1 300 × 103 ≥ 0.60 A To determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak value : IL VIN−Vo IL ≥ Io + 2L Peak-peak value : ∆IL ∆IL = 32 VIN−Vo L tON tON MB39A113 Example) Using the CDRH104R-150 15 µH (tolerance ± 30%) , rated current = 3.6 A Peak value 16.8 V output IL ≥ Io + ≥ VIN−Vo 2L tON 25−16.8 3+ 2 × 15 × 10 −6 × 1 300 × 103 × 0.672 ≥ 3.6 A 12.6 V output IL ≥ Io + ≥ VIN−Vo 2L tON 22−12.6 3+ 2 × 15 × 10 −6 × 1 300 × 103 × 0.572 ≥ 3.6 A Peak-peak value 16.8 V output VIN−Vo ∆IL = L = =: 25−16.8 15 × 10 −6 tON × 1 300 × 103 × 0.672 1.22 A 12.6 V output VIN−Vo ∆IL = L 22−12.6 = 15 × 10−6 =: 1.2 A tON × 1 300 × 103 × 0.572 • Flyback diode As a flyback diode, in general, a Schottky barrier diode (SBD) is used when the reverse voltage to the diode is 40 V or less. The SBD has the characteristic of higher speed in terms of faster reverse recovery time, and lower forward voltage, and is ideal for archiving high efficiency. There is no problem as long as the DC reverse voltage is sufficiently higher than the input voltage, and the mean current flowing during the diode conduction time is within the mean output current level, and as the peak current is within the peak surge current limits. In this application the RB053L-30 (ROHM) are used. The diode mean current and diode peak current can be obtained by the following formulas. Diode mean current : IDi Vo ) IDi ≥ Io × (1− VIN Diode peak current : IDip Vo IDip ≥ (Io + tOFF) 2L 33 MB39A113 Example) Using the RB053L-30 VR (DC reverse voltage) = 30 V, average output current = 3.0 A, peak surge current = 70 A VF (forward voltage) = 0.42 V, at IF = 3.0 A 16.8 V output Vo ) VIN ≥ 3 × (1−0.672) ≥ 0.984 A IDi ≥ Io × (1− 12.6 V output Vo ) VIN ≥ 3 × (1−0.572) ≥ 1.284 A IDi ≥ Io × (1− 16.8 V output IDip ≥ ≥ (Io + Vo 2L tOFF) Vo 2L tOFF) 3.6 A 12.6 V output IDip ≥ ≥ (Io + 3.6 A • Smoothing capacitor The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smoothing capacitor, it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low ESR. Note, however, that the use of a capacitor with low ESR has substantial effects on loop phase characteristics, and impairing system stability. Care should also be taken to use a capacity with sufficient margin for allowable ripple current. In this application the 20SVP22M (OS-CONTM : SANYO) are used. The ESR, capacitance value, and ripple current can be obtained by the following formulas. Equivalent series resistance : ESR ∆Vo 1 ESR ≤ − 2πfCL ∆IL Capacitance value : CL ∆IL CL ≥ 2πf (∆Vo−∆IL × ESR) Ripple current : ICLrms (VIN−Vo) tON ICLrms ≥ 2√3L 34 MB39A113 Example) Using the 20SVP22M Rated voltage = 20 V, ESR = 60 mΩ, maximum allowable ripple current = 1450 mArms Equivalent series resistance 16.8 V output ∆Vo 1 ESR ≤ − 2πfCL ∆IL 0.168 ≤ 1.22 ≤ 1 − 2π × 300 × 103 × 22 × 10−6 114 mΩ 12.6 V output ∆Vo ESR ≤ ∆IL 0.126 ≤ 1.2 1 − 2πfCL 1 − 2π × 300 × 103 × 22 × 10−6 ≤ 80 mΩ Capacitance value 16.8 V output CL ≥ ≥ ∆IL 2πf (∆Vo−∆IL × ESR) 1.22 2π × 300 × 10 × (0.168−1.22 × 0.06) 3 ≥ 6.8 µF 12.6 V output CL ≥ ≥ ∆IL 2πf (∆Vo−∆IL × ESR) 1.2 2π × 300 × 10 × (0.126−1.2 × 0.06) 3 ≥ 11.8 µF Ripple current 16.8 V output (VIN−Vo) tON ICLrms ≥ 2√3L ≥ ≥ (25−16.8) × 0.672 2√3 × 15 × 10−6 × 300 × 103 707 mArms 12.6 V output (VIN−Vo) tON ICLrms ≥ 2√3L ≥ (22−12.6) × 0.572 2√3 × 15 × 10−6 × 300 × 103 ≥ 690 mArms 35 MB39A113 ■ REFERENCE DATA Conversion Efficiency vs. Charge Current (constant voltage mode) 100 98 Efficiency η (%) 96 94 92 90 88 Ta = + 25 °C VAC = 19 V VBATT = 12.6 V setting η = (VBATT × IBATT) / (VAC × IAC) Converted to VBATT 86 84 82 80 0.01 0.1 1 10 IBATT (A) Conversion Efficiency vs. Charge Voltage (constant current mode) 100 98 Efficiency η (%) 96 94 92 90 88 Ta = + 25 °C VAC = 19 V IBATT = 3 A setting η = (VBATT × IBATT) / (VAC × IAC) Converted to VBATT 86 84 82 80 0 2 4 6 8 10 12 14 VBATT (V) BATT Voltage vs. BATT Charge Current (12.6 V setting) 18 16 14 Ta = + 25 °C VAC = 19 V VBATT = 12.6 V setting VBATT (V) 12 D.C.C. Mode 10 8 Dead Battery Mode 6 4 2 0 0.0 D.C.C. Mode : Dynamically-controlled charging 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IBATT (A) (Continued) 36 MB39A113 Conversion Efficiency vs. Charge Current (constant voltage mode) 100 98 Efficiency η (%) 96 94 92 90 88 Ta = + 25 °C VAC = 19 V VBATT = 16.8 V setting η = (VBATT × IBATT) / (VAC × IAC) Converted to VBATT 86 84 82 80 0.01 0.1 1 10 IBATT (A) Conversion Efficiency vs. Charge Voltage (constant current mode) 100 98 Efficiency η (%) 96 94 92 90 88 Ta = + 25 °C VAC = 19 V IBATT = 3 A setting η = (VBATT × IBATT) / (VAC × IAC) Converted to VBATT 86 84 82 80 0 2 4 6 8 10 12 14 16 VBATT (V) BATT Voltage vs. BATT Charge Current (16.8 V setting) 18 16 D.C.C. Mode 14 VBATT (V) 12 Dead Battery Mode 10 8 6 4 Ta = + 25 °C VAC = 19 V VBATT = 16.8 V setting 2 0 0.0 D.C.C. Mode : Dynamically-controlled charging 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IBATT (A) (Continued) 37 MB39A113 Switching Waveform at Constant Voltage Mode (12.6 V setting) OUT(V) 15 VAC = 19 V CV mode IBATT = 1.5 A VBATT = 12.6 V setting VD(V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) Switching Waveform at Constant Current Mode (12.6 V setting at 10 V) OUT(V) 15 VAC = 19 V CC mode IBATT = 3 A setting VBATT = 10 V VD(V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) (Continued) 38 MB39A113 Switching Waveform at Constant Voltage Mode (16.8 V setting) OUT(V) 15 VAC = 19 V CV mode IBATT = 1.5 A VBATT = 16.8 V setting VD(V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) Switching Waveform at Constant Current Mode (16.8 V setting at 10 V) OUT(V) 15 VAC = 19 V CC mode IBATT = 3 A setting VBATT = 10 V VD(V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) (Continued) 39 MB39A113 Soft-start Operating Waveform at Constant Voltage Mode (12.6 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft-start Operating Waveform at Constant Voltage Mode (12.6 V setting) (2) CVM(V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 40 MB39A113 Discharge Operating Waveform at Constant Voltage Mode (12.6 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge Operating Waveform at Constant Voltage Mode (12.6 V setting) (2) CVM(V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 41 MB39A113 Soft-start Operating Waveform at Constant Current Mode (12.6 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft-start Operating Waveform at Constant Current Mode (12.6 V setting) (2) CVM(V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 42 MB39A113 Discharge Operating Waveform at Constant Current Mode (12.6 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge Operating Waveform at Constant Current Mode (12.6 V setting) (2) CVM(V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP(V) 5 0 CTL(V) OVP 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 43 MB39A113 Soft-start Operating Waveform at Constant Voltage Mode (16.8 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft-start Operating Waveform at Constant Voltage Mode (16.8 V setting) (2) CVM(V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 44 MB39A113 Discharge Operating Waveform at Constant Voltage Mode (16.8 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge Operating Waveform at Constant Voltage Mode (16.8 V setting) (2) CVM(V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 45 MB39A113 Soft-start Operating Waveform at Constant Current Mode (16.8 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft-start Operating Waveform at Constant Current Mode (16.8 V setting) (2) CVM(V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 46 MB39A113 (Continued) Discharge Operating Waveform at Constant Current Mode (16.8 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting VO(V) 20 15 10 5 VO 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge Operating Waveform at Constant Current Mode (16.8 V setting) (2) CVM(V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP(V) 5 OVP 0 CTL(V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) 47 MB39A113 ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. • • • • For semiconductors, use antistatic or conductive containers. When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. The work table, tools, and measuring instruments must be grounded. The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage. • Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. 48 MB39A113 ■ ORDERING INFORMATION Part number MB39A113PFV Package Remarks 24-pin plastic SSOP (FPT-24P-M03) 49 MB39A113 ■ PACKAGE DIMENSION Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 24-pin plastic SSOP (FPT-24P-M03) 0.17±0.03 (.007±.001) *17.75±0.10(.305±.004) 24 13 *2 5.60±0.10 7.60±0.20 (.220±.004) (.299±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 (Mounting height) 0.25(.010) 1 "A" 12 0~8˚ +0.08 0.65(.026) 0.24 –0.07 +.003 .009 –.003 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F24018S-c-4-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 50 MB39A113 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 FUJITSU LIMITED Printed in Japan