Triple, 6-Channel LCD Timing Delay-Locked Loop AD8389 PRODUCT FEATURES PRODUCT DESCRIPTION High speed Up to 85 MHz clock rate Triple (R, G, B) output Matched delay lines Low power dissipation: 40 mW Reference to rising or falling edge of MONITI input Selectable loop delay Available in 48-lead 7 mm × 7 mm LFCSP The AD8389 is a triple 6-channel LCD microdisplay delaylocked timing loop. As part of a closed-loop system, the AD8389 maintains a constant delay between the common input, DXI, and each independent feedback reference, MONITxI. The AD8389 consists of a selectable fixed delay element, a phase detector, a charge pump, and six matched variable delay lines per color. The phase detector, charge pump, and master delay line form a closed loop when connected to a compatible LCD microdisplay. Five additional delay lines track the master for a complete set of matched timing signals. APPLICATIONS LCD microdisplay horizontal timing The AD8389 dissipates 40 mW nominal power. The AD8389 is offered in a 48-lead 7 mm × 7 mm LFCSP package and operates over the commercial temperature range of 0°C to 85°C. FUNCTIONAL BLOCK DIAGRAM AVDD(4) AVSS(4) DRVDD(2) DRVSS(2) AD8389 COMPEDGE SELECTABLE DELAY SLOW PHASE DETECTOR CHARGE PUMP VCONTR MONITRI DXI MATCHED VARIABLE DELAY LINES (6-CHANNEL) DXI ENBX1I ENBX2I ENBX3I ENBX4I CLXI 6 / PHASE DETECTOR 6 / CHARGE PUMP DXRO ENBX1RO ENBX2RO ENBX3RO ENBX4RO CLXRO VCONTG MONITGI MATCHED VARIABLE DELAY LINES (6-CHANNEL) PHASE DETECTOR 6 / CHARGE PUMP DXGO ENBX1GO ENBX2GO ENBX3GO ENBX4GO CLXGO VCONTB MATCHED VARIABLE DELAY LINES (6-CHANNEL) CLK INTERNAL TIMING 6 / DXBO ENBX1BO ENBX2BO ENBX3BO ENBX4BO CLXBO 04515-0-001 MONITBI Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD8389 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing.................................................................................................6 Absolute Maximum Ratings............................................................ 4 Operating Principles .........................................................................7 Exposed Paddle............................................................................. 4 Operation .......................................................................................7 Maximum Power Dissipation ..................................................... 4 Outline Dimensions ..........................................................................9 Pin Configuration and Function Descriptions............................. 5 Ordering Guide .............................................................................9 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD8389 SPECIFICATIONS Table 1. @ 25°C, AVDD = DRVDD = 3.3 V, TMIN = 0°C, TMAX = 85°C, unless otherwise noted Parameter LOGIC INPUTS CIN IIN VIH VIL VTH OUTPUTS VOH VOL TIMING SPECIFICATIONS Operating Frequency CLK, fCLK CLXI, ENBX(1–4)I DXI, MONITxI Input Low Pulse Width, t1—All Inputs except CLK DXI, MONITxI ENBX(1–4)I, CLXI CLK High Pulse Width, t2 CLK Low Pulse Width, t3 CLK to DXI Setup Time, t4 Output Rise, Fall Times—tr, tf Delay t5 Output Skew, t6 t5 ≤ 130 ns t5 ≤ 170ns t5 ≤ 230ns Loop Delay, t7 COMPEDGE = H, SLOW = H COMPEDGE = H, SLOW = L COMPEDGE = L, SLOW = H COMPEDGE = L, SLOW = L POWER SUPPLIES AVDD Operating Range DRVDD Operating Range Total Operating Current Power Dissipation Operating Temperature Conditions Min Typ –2 2.0 AGND Max Unit +2 AVDD 0.8 pF µA V V V 1.5 IO = –2 µA IO = +2 µA DRVDD – 0.4 60 t5 ≤ 230ns CL = 30 pF DXI to DXxO CL = 30 pF 75 DVRSS + 0.4 V V 85 (2t1)–1 (2t1)–1 MHz Hz Hz 5 350 ns ns ns ns ns ns ns 2.5 3.4 5 ns ns ns 280 30 4.7 4.7 2 22 0.3 0.45 0.7 9/(fCLK) + t4 15/(fCLK) + t4 26/(fCLK) + t4 32/(fCLK) + t4 3 3 fCLK = 75 MHz, CL = 30 pF fCLK = 75 MHz, CL = 30 pF 3.6 3.6 11 40 0 Rev. 0 | Page 3 of 12 ns ns ns ns 85 V V mA mW °C AD8389 ABSOLUTE MAXIMUM RATINGS Table 2. AD8389 Stress Ratings1 Parameter Supply Voltages AVDDx – AVSSx DRVDDx – DRVSSx Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Internal Power Dissipation2 LFCSP Package @ TA = 25°C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec) 1 EXPOSED PADDLE Rating To ensure high reliability, the exposed paddle must be soldered to GND. 3.9 V 3.9 V MAXIMUM POWER DISSIPATION AVDD + 0.3 V AVSS – 0.3 V 4.8 W 0°C to 85°C –65°C to +125°C 300°C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability. 2 48-Lead LFCSP Package: θJA = 26°C/W (JEDEC Standard 4-layer PCB in still air) θJC = 20°C/W The maximum power that can be safely dissipated by the AD8389 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices as determined by the glass transition temperature of the plastic is approximately 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. To ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation as follows: PDMAX = (TJMAX – TA)/θJA 5.0 POWER DISSIPATION (W) 4.5 4.0 3.5 3.0 2.0 25 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 12 04515-0-002 2.5 AD8389 AVSS 1 37 DRVSS 38 DRVDD 39 CLK 40 SLOW 41 DXI 42 ENBX1I 43 ENBX2I 44 ENBX3I 45 ENBX4I 46 CLXI 47 COMPEDGE 48 AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DXRO 35 ENBX1RO MONITGI 3 34 ENBX2RO MONITBI 4 33 ENBX3RO AVDD 5 32 ENBX4RO 31 CLXRO 30 DXGO 29 ENBX1GO 28 ENBX2GO VCONTG 10 27 ENBX3GO VCONTB 11 26 ENBX4GO AVSS 12 25 CLXGO PIN 1 INDICATOR AD8389 AVSS 6 TOP VIEW (Not to Scale) VCONTR 7 AVDD 8 NC 24 DXBO 23 ENBX1BO 22 ENBX2BO 21 ENBX3BO 20 ENBX4BO 19 CLXBO 18 DRVSS 17 NC 15 NC 14 AVDD 13 NC = NO CONNECT DRVDD 16 48-LEAD LFCSP 7mm × 7mm AVSS 9 04515-0-003 36 MONITRI 2 Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration Table 3. Pin Function Descriptions Mnemonic AVDD, DRVDD AVSS, DRVSS CLK COMPEDGE Function Power Supply Ground Clock Edge Select SLOW Delay Select DXI CLXI ENBX(1–4)I MONITxI Reference Input Input Inputs Feedback Inputs DXxO CLXxO ENBX(1–4)xO VCONTx Delayed Outputs Delayed Outputs Delayed Outputs Control Voltage Description Power Supply. Ground. Clock Input. Active edge is the rising edge. When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling edge of MONITxI. When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 9/(fCLK) + t4. The delay is maintained at 26/(fCLK) + t4 when COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 15/(fCLK) + t4. The delay is maintained at 32/(fCLK) + t4 with COMPEDGE = LOW. LCD Timing Input from the Image Processor. Used as the input to all phase detectors. LCD Timing Input from the Image Processor. LCD Timing Inputs from the Image Processor. Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389 forms part of a closed loop, it maintains a constant delay between the DXI input and this reference input pin. 200 pF capacitors connected between these pins and the AVSS plane are required for proper operation of the internal charge pump. Rev. 0 | Page 5 of 12 AD8389 TIMING Table 4. Timing Specifications Parameter Operating Frequency CLK, fCLK CLXI, ENBX(1–4)I DXI, MONITxI Input Low Pulse Width, t1—All Inputs except CLK DXI, MONITxI ENBX(1–4)I, CLXI CLK High Pulse Width—t2 CLK Low Pulse Width—t3 CLK to DXI Setup Time—t4 Output Rise, Fall Time—tr, tf Delay—t5 Output Skew— t6 t5 ≤ 130 ns t5 ≤ 170ns t5 ≤ 230ns Loop Delay, t7 COMPEDGE = H, SLOW = H COMPEDGE = H, SLOW = L COMPEDGE = L, SLOW = H COMPEDGE = L, SLOW = L Conditions Min Typ Max Unit 60 75 85 (2t1)–1 (2t1)–1 MHz Hz Hz 5 350 ns ns ns ns ns ns ns 2.5 3.4 5 ns ns ns 280 30 4.7 4.7 2 t5 ≤ 230ns CL = 30 pF DXI to DXxO CL = 30 pF 22 0.3 0.45 0.7 9/(fCLK) + t4 15/(fCLK) + t4 26/(fCLK) + t4 32/(fCLK) + t4 ns ns ns ns t3 DXI t2 VTH CLK t7 MONITxI t4 t4 tEXT VTH t1 DXO 04515-0-004 DXI t5 DXxO CLXxO ENBX(1–4)XO t6 Figure 5. Input and Output Waveforms at COMPEDGE = HIGH Rev. 0 | Page 6 of 12 04515-0-005 Figure 4. CLK and DXI Timing AD8389 OPERATING PRINCIPLES MON MONITO DX DXI CLX, ENBX(1–4) DXRO CLXRO, ENBX(1–4)O DXI DXO CLXIN, ENBX(1–4)I VCONTR 200pF MONITI H SHIFT REGISTER CLXO, ENBX(1–4)O AD8384/AD8385 AD8389 RED LCD LEVEL SHIFTER SECTION 04515-0-006 MONITRI Figure 6. AD8389 Application in the Red Channel of an LCD Projection System The image quality of an LCD system is dependent on the timing relationship between the control inputs, DX, CLX, ENBX(1–4), and the video channels. TFT delay and switching speed variations, due to temperature variations and LCD aging, degrade image quality if not compensated. An internal reference TFT connected to an internal pull-up resistor, as shown in Figure 6, characterizes the internal S/H TFTs of the LCD and monitors switching speed and delay variations due to aging and temperature. When the MON output of an LCD that includes such an internal reference TFT is connected to the reference input of the AD8389 delay-locked timing loop, continuously optimized timing of the LCD is maintained automatically. OPERATION As part of a closed loop, the AD8389 maintains a constant delay between the common input, DXI, and each independent feedback reference, MONITxI. The block diagram of such closed-loop system is shown in Figure 6. A constant delay, t7, selected via the COMPEDGE and SLOW control inputs, is applied to the DXI input to approximate the nominal, initially expected total delay, t7, through the level shifters and the LCD as shown in Table 5. Table 5 COMPEDGE 1 1 SLOW 0 1 Constant Delay 15/fCLK + t4 9/fCLK + t4 DX CONSTANT MONITRI 0 0 0 1 32/fCLK + t4 26/fCLK + t4 CONSTANT DX MONITRI Rev. 0 | Page 7 of 12 AD8389 When the loop is locked, t7 = t5 + tEXT, where tEXT is the total delay through the level shifter and the LCD. CLK CONSTANT DX MONITRI AD8389 INPUTS The phase detector compares the delayed DX and MONITxI reference inputs and automatically adjusts the variable delay (t5), maintaining the constant delay (t7) between the active edges of DX and MONITxI. Five matched delay lines maintain the phase relationship between DXxO, CLXxO, and ENBX(1–4)xO. The external delay of a typical system is the sum of the level shifter delay (20 ns typical) and the LCD delay, (typically in the range of 20 ns to 120 ns). At a 75 MHz operating clock frequency, the maximum expected total delay of 140 ns is equal to 10.5 clock cycles, requiring COMPEDGE = 1, SLOW = 0 for systems using negative active edge for DX. CLX ENBX1 ENBX2 ENBX3 ENBX4 DXO MONITI LCD INPUTS AND OUTPUT CLXO ENBX1O ENBX2O ENBX4O Figure 7. Typical Input Waveforms at the AD8389 and at the LCD. COMPEDGE = HIGH. Rev. 0 | Page 8 of 12 04515-0-007 ENBX3O AD8389 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.75 BSC SQ TOP VIEW 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 5.25 5.10 SQ 4.95 BOTTOM VIEW 0.50 0.40 0.30 25 24 12 13 0.25 MIN 1.00 0.85 0.80 12° MAX 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 8. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48) ORDERING GUIDE Model AD8389ACPZ1 1 Temperature Range 0°C to 85°C Package Description 48-Lead Lead Frame Chip Scale Package Z = lead-free. Rev. 0 | Page 9 of 12 Package Option CP-48 AD8389 NOTES Rev. 0 | Page 10 of 12 AD8389 NOTES Rev. 0 | Page 11 of 12 AD8389 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04515–0–10/03(0) Rev. 0 | Page 12 of 12