AS29LV400 Preliminary Information March 2001 ® 3V 512K x 8/256K × 16 CMOS Flash EEPROM Features • Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current • JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO; availabillity TBD • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - DQ2 toggle bit - RY/B Y output • Erase suspend/resume - Supports reading data from or programming data to a sector not being erased • Low VCC write lock-out below 1.5V • 10 year data retention at 150C • 100,000 write/erase cycle endurance • Organization: 512Kx8/256Kx16 • Sector architecture - One 16K; two 8K; one 32K; and seven 64K byte sectors - One 8K; two 4K; one 16K; and seven 32K word sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 2.7-3.6V power supply for read/write operations • Sector protection • High speed 70/80/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors • Hardware RES ET pin - Resets internal state machine to read mode Pin arrangement 48-pin TSOP WE B Y TE Input/output buffers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RESE T Erase voltage generator 44-pin SO A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE VSS NC VCC DQ0–DQ15 RE SE T BY NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 RY/ Sector protect/ erase voltage switches Program/erase control Command register Program voltage generator AS29LV40 STB Chip enable Output enable Logic CE OE Data latch STB Timer Y decoder Y gating X decoder Cell matrix 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BY TE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE CE A0 VSS A0–A17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC detector Address latch A-1 RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 AS29LV40 Logic block diagram Selection guide 29LV400-70 29LV400-80 29LV400-90 29LV400-120 Unit Maximum access time tAA 70 80 90 120 ns Maximum chip enable access time tCE 70 80 90 120 ns Maximum output enable access time tOE 30 30 35 50 ns 3/20/01; V.0.9.3 Alliance Semiconductor P. 1 of 25 Copyright © Alliance Semiconductor. All rights reserved. AS29LV400 March 2001 ® Functional description The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP. A 44-pin SOP package may be offered in the future. This device is designed to be programmed and erased with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE ), write enable (W E ), and output enable (OE ) controls. Word mode (×16 output) is selected by B Y T E = high. Byte mode (×8 output) is selected by B Y T E = low. The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations. Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper cell margins. Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip Erase command will automatically erase all unprotected sectors. When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low V C C detector automatically inhibits write operations during power transtitions. The RY/B Y pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are completed. DQ2 indicates which sectors are being erased. The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control register architecture permits alteration of memory contents only when successful completion of specific command sequences has occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE , CE , or W E. To initiate Write commands, C E and W E must be a logical zero and O E a logical 1. When the device’s hardware RE S ET pin is driven low, any Program/Erase operation in progress is terminated and the internal state machine is reset to Read mode. If the RE S ET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory. The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using the EPROM programming mechanism of hot electron injection. 3/20/01; V.0.9.3 Alliance Semiconductor P. 2 of 25 AS29LV400 March 2001 ® Operating modes Mode CE OE WE A0 A1 A6 A9 RESE T DQ ID read MFR code L L H L L L VID H Code ID read device code L L H H L L VID H Code Read L L H A0 A1 A6 A9 H DOUT Standby H X X X X X X H High Z Output disable L H H X X X X H High Z Write L H L A0 A1 A6 A9 H DIN Enable sector protect L VID Pulse/L L H L VID H X Sector unprotect L VID Pulse/L L H H VID H X Temporary sector unprotect X X X X X X X VID X Verify sector protect† L L H L H L VID H Code Verify sector unprotect† L L H L H H VID H Code Hardware Reset X X X X X X L High Z X L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care. In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1. † Verification of sector protect/unprotect during A9 = VID. Mode definitions Item Description ID MFR code, device code Selected by A9 = VID(9.5V–10.5V), CE = O E = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29LV400. Read mode Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Standby Selected with CE = H. Part is powered down, and ICC reduced to <1.0 µA when CE = VCC ± 0.3V = R ESE T. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Output disable Part remains powered up; but outputs disabled with O E pulled high. Write Selected with CE = W E = L, O E = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of W E or CE , whichever occurs later. Data latching occurs on the rising edge W E or CE , whichever occurs first. Filters on W E prevent spurious noise events from appearing as write commands. Enable sector protect Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page 14. Sector unprotect Disables sector protection for all sectors using external programming equipment. All sectors must be protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm on page 14. Verify sector protect/ unprotect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. 3/20/01; V.0.9.3 Alliance Semiconductor P. 3 of 25 AS29LV400 March 2001 ® Item Description Temporary sector unprotect Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RE SET to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +10V from RE S ET. RE SET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted. Deep power down Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns. Automatic sleep mode Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new data is returned within standard access times. Flexible sector architecture Bottom boot sector architecture (AS29LV400B) Top boot sector architecture (AS29LV400T) Sector ×8 ×16 Size (Kbytes) ×8 ×16 Size (Kbytes) 0 00000h–03FFFh 00000h–01FFFh 16 00000h–0FFFFh 00000h–07FFFh 64 1 04000h–05FFFh 02000h–02FFFh 8 10000h–1FFFFh 08000h–0FFFFh 64 2 06000h–07FFFh 03000h–03FFFh 8 20000h–2FFFFh 10000h–17FFFh 64 3 08000h–0FFFFh 04000h–07FFFh 32 30000h–3FFFFh 18000h–1FFFFh 64 4 10000h–1FFFFh 08000h–0FFFFh 64 40000h–4FFFFh 20000h–27FFFh 64 5 20000h–2FFFFh 10000h–17FFFh 64 50000h–5FFFFh 28000h–2FFFFh 64 6 30000h–3FFFFh 18000h–1FFFFh 64 60000h–6FFFFh 30000h–37FFFh 64 7 40000h–4FFFFh 20000h–27FFFh 64 70000h–77FFFh 38000h–3BFFFh 32 8 50000h–5FFFFh 28000h–2FFFFh 64 78000h–79FFFh 3C000h–3CFFFh 8 9 60000h–6FFFFh 30000h–37FFFh 64 7A000h–7BFFFh 3D000h–3DFFFh 8 10 70000h–7FFFFh 38000h–3FFFFh 64 7C000h–7FFFFh 3E000h–3FFFFh 16 In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if B Y TE = VIL; address range is A17–A0 if B Y T E = VIH. 3/20/01; V.0.9.3 Alliance Semiconductor P. 4 of 25 AS29LV400 March 2001 ® ID Sector address table Bottom boot sector address (AS29LV400B) Top boot sector address (AS29LV400T) Sector A17 A16 A15 A14 A13 A12 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 X 0 0 0 X X X 1 0 0 0 0 1 0 0 0 1 X X X 2 0 0 0 0 1 1 0 1 0 X X X 3 0 0 0 1 X X 0 1 1 X X X 4 0 0 1 X X X 1 0 0 X X X 5 0 1 0 X X X 1 0 1 X X X 6 0 1 1 X X X 1 1 0 X X X 7 1 0 0 X X X 1 1 1 0 X X 8 1 0 1 X X X 1 1 1 1 0 0 9 1 1 0 X X X 1 1 1 1 0 1 10 1 1 1 X X X 1 1 1 1 1 X READ codes Mode A17–A12 A6 A1 A0 Code MFR code (Alliance Semiconductor) X L L L 52h ×8 T boot X L L H B9h ×8 B boot X L L H BAh ×16 T boot X L L H 22B9h ×16 B boot X L L H 22BAh Sector address L H L 01h protected 00h unprotected Device code Sector protection Key: L =Low (<VIL); H = High (>VIH); X =Don’t care 3/20/01; V.0.9.3 Alliance Semiconductor P. 5 of 25 AS29LV400 March 2001 ® Command format Command sequence Reset/Read 2nd bus cycle Address Data Address Data 1 XXXh F0h Read Address Read Data ×16 Reset/Read 1st bus cycle Required bus write cycles 555h 3 2AAh AAh ×8 AAAh ×16 555h Autoselect ID Read ×16 555h 555h 3 ×8 ×16 ×8 AAAh ×16 Program ×16 Unlock bypass 2AA Program data Unlock bypass reset 2 XXX 90h XXX 00h 555h ×16 Sector Erase 2AAh AAh 1 XXXh B0h Sector Erase Resume 1 XXXh 30h 0001h=protected 0000h=unprotected Program Address Program Data 555h 80h 2AAh AAh AAAh 555h 55h 555h Sector Erase Suspend 1 2 3 4 5 6 555h AAAh 2AAh AAh AAAh XXX04h Sector protection 20h 55h 555h 555h 6 ×8 0001h = protected 0000h = unprotected 555 Program address AAAh 52h XXX02h Sector protection AAA A0h 6 A0h 55h 555 XXX ×16 Data 555h 2 ×8 0052h 6th bus cycle Address AAAh Unlock bypass program Chip Erase 00h MFR code Data 90h 55h AAh B9h(T) BAh(B) AAAh 555h AAA 02h Device code 555h 2AAh 555 3 ×8 22B9h (T) 22BAh (B) 90h 55h AAh AAAh 01h Device code 555h 555h 555h 4 ×8 Read Data AAAh 2AAh AAh Read Address Address 90h 55h 555h 555h F0h AAAh 2AAh AAh AAAh Data 555h 55h 5th bus cycle Address AAAh 2AAh AAAh 4th bus cycle Data 555h 55h 555h AAh ×8 3rd bus cycle Address 555h 80h AAAh 10h AAAh 2AAh AAh AAAh 555h 55h 555h 55h 555h Sector Address 30h Bus operations defined in "Mode definitions," on page 3. Reading from and programming to non-erasing sectors allowed in Erase Suspend mode. Address bits A11-A17 = X = Don’t Care for all address commands except where Program Address and Sector Address are required. Data bits DQ15-DQ8 are don’t care for unlock and command cycles. The Unlock Bypass command must be initiated before the Unlock Bypass Program command. The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode. 3/20/01; V.0.9.3 Alliance Semiconductor P. 6 of 25 AS29LV400 March 2001 ® Command definitions Item Description Reset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Hardware Reset Holding R ES E T low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 µs after RE SET is driven low. RY/BY remains low until internal state machine resets. After RESE T is set high, there is a delay of 50 ns for the device to permit read operations. Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of C E or WE , whichever is last; data is latched on the rising edge of CE or WE , whichever is first. The AS29LV400’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word Programming Check programming status by sampling data on the RY/B Y pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/B Y pin = high. The AS29LV400 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode. 3/20/01; V.0.9.3 Alliance Semiconductor P. 7 of 25 AS29LV400 March 2001 ® Item Description The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h. Unlock Bypass Command Sequence The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed. The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of W E; the command, 30h is latched on the rising edge of WE . The sector erase operation begins after a sector erase time-out. Sector Erase To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after sector erase time-out from the last rising edge of W E from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV400 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. 3/20/01; V.0.9.3 Alliance Semiconductor P. 8 of 25 AS29LV400 March 2001 ® Item Description Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don’t Care when writing Erase Suspend or Erase Resume commands. Erase Suspend AS29LV400 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/B Y. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV400 ignores redundant writes of Erase Suspend. While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV400 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume operations during sector erase. Sector Protect When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors. Ready/Busy RY/B Y indicates whether an automated on-chip algorithm is in progress (RY/B Y = low) or completed (RY/B Y = high). The device does not accept Program/Erase commands when RY/B Y = low. RY/B Y= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. Status operations DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm). Toggle bit 1 (DQ6) Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when C E or O E toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth W E pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors are protected). Exceeding time limit (DQ5) Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1. 3/20/01; V.0.9.3 Alliance Semiconductor P. 9 of 25 AS29LV400 March 2001 ® Sector erase timer (DQ3) Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. Toggle bit 2 (DQ2) During sector erase, DQ2 toggles with OE or C E only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. Write operation status Standard mode Erase suspend mode Exceeded time limits Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY Auto programming DQ 7 Toggle 0 N/A No toggle † 0 0 Program/erase in auto erase 0 Toggle 0 1 Toggle Read erasing sector 1 No toggle 0 N/A Toggle 1 Read non-erasing sector Data Data Data Data Data 1 Program in erase suspend DQ 7 Toggle 0 N/A Toggle† 0 Auto programming (byte) DQ 7 Toggle 1 N/A No toggle 1 1 1 Program/erase in auto erase 0 Toggle 1 N/A Toggle† Program in erase suspend (non-erase suspended sector) DQ 7 Toggle 1 N/A No toggle DQ2 toggles when an erase-suspended sector is read repeatedly. DQ6 toggles when any address is read repeatedly. DQ2 = 1 if byte address being programmed is read during erase-suspend program mode. † DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase. 3/20/01; V.0.9.3 Alliance Semiconductor P. 10 of 25 March 2001 AS29LV400 ® Automated on-chip programming algorithm Automated on-chip erase algorithm START START Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA polling or toggle bit successfully completed Erase complete Individual sector/multiple sector Increment address Last address? Chip erase command sequence ×16 mode (address/data): NO YES erase command sequence ×16 mode (address/data): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector address/30h Programming completed Program command sequence ×16 mode (address/data): 555h/AAh 2AAh/55h 555h/A0h Sector address/30h Program address/program data Sector address/30h optional sector erase commands † 3/20/01; V.0.9.3 The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. Alliance Semiconductor P. 11 of 25 March 2001 AS29LV400 ® Pro g r am m i ng u s i n g u nl oc k byp a s s c o m m an d Unlock bypass command sequence x16 mode (address/data) START 555h/AAh Write unlock bypass command (3 cycles) 2AAh/55h 555h/20h Write unlock bypass program command (2 cycles) Unlock bypass program command sequence x16 mode (address/data) DATA polling or toggle bit successfully completed xxxh/A0h Increment address Last address? program address/ program data NO Unlock bypass reset command sequence x16 mode (address/data) YES xxxh/90h Write unlock bypass reset command (2 cycles) xxxh/00h Programming completed 3/20/01; V.0.9.3 Alliance Semiconductor P. 12 of 25 March 2001 AS29LV400 ® DATA polling algorithm Toggle bit algorithm Read byte (DQ0–DQ7) Address = VA† DQ7 = data ? Read byte (DQ0–DQ7) Address = don’t care DQ6 = toggle ? YES DONE NO NO NO 1 YES Read byte (DQ0–DQ7) Address = VA YES† Read byte (DQ0–DQ7) Address = don’t care DQ6 = toggle† ? DONE NO† NO DONE YES FAIL FAIL VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. ‡ DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. 3/20/01; V.0.9.3 DQ5 = ? YES † DONE YES DQ5 = 1 ? DQ7 = data‡ ? NO † DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. Alliance Semiconductor P. 13 of 25 AS29LV400 March 2001 ® Sector protect algorithm Temporary sector unprotect mode No Sector unprotect algorithm START START PLSCNT = 1 PLSCNT = 1 RESET# = VID RESET# = VID Wait 1 µs Wait 1 µs Protect all sectors: The shaded portion of the sector protct algorithm must be initiated for all unprotected sectors before calling the sector unprotect First Write Cycle=60h? Yes Set up sector address Sector protect: write 60h to sector address with A6=0, A1=1, A0=0 No All sectors protected? Yes Sector unprotect: write 60h to sector address with A6=1, A1=1, A0=0 Verify sector protect; write 40h to sector address with A6=0, A1=1, A0=0 PLSCNT=25? Wait 15 ms Set up first sector address Read from sector address with A6=0, A1=1, A0=0 No No Verify sector unprotect; write 40h to sector address with A6=1, A1=1, A0=0 Increment PLSCNT Read from sector address with A6=1, A1=1, A0=0 Data=01h? No Yes Set up next sector address Yes Device failed Protect another sector? Yes PLSCNT =1000? No Remove VID from RESET# Write reset command Temporary sector unprotect mode Yes Wait 150 µs Increment PLSCNT No First Write Cycle=60h? No Data=00h? Yes Yes Device failed Last sector verified? No Yes Remove VID from RESET# Sector protect complete Write reset command Sector unprotect complete 3/20/01; V.0.9.3 Alliance Semiconductor P. 14 of 25 AS29LV400 March 2001 ® DC electrical characteristics VCC = 2.7–3.6V Parameter Symbol Test conditions Min Max Unit Input load current ILI VIN = VSS to VCC, VCC = VCC MAX - ±1 µA A9 Input load current ILIT VCC = VCC MAX, A9 = 10V 35 µA Output leakage current ILO VOUT = VSS to VCC, VCC = VCC MAX - ±1 µA Active current, read @ 5MHz ICC1 CE = VIL, O E = VIH - 20 mA Active current, program/erase ICC2 CE = VIL, O E = VIH - 100 mA Automatic sleep mode* ICC3 CE = VIL, O E = VIH; VIL= 0.3V, VIH = VCC - 0.3V - 5 µA Standby current ISB CE = VCC - 0.3V, RE SET = VCC - .3V - 5 µA Deep power down current3 IPD RE SET = 0.3V - 5 µA Input low voltage VIL -0.5 0.8 V Input high voltage VIH 0.7×VCC VCC + 0.3 V Output low voltage VOL IOL = 4.0mA, VCC = VCC MIN - 0.45 V Output high voltage VOH IOH = -2.0 mA, VCC = VCC MIN 0.85×VCC - V Low VCC lock out voltage VLKO 1.5 - V Input HV select voltage VID 9 11 V * Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA. 3/20/01; V.0.9.3 Alliance Semiconductor P. 15 of 25 AS29LV400 March 2001 ® AC parameters — read cycle -70 JEDEC Symbol Std Symbol Parameter Min tAVAV tRC Read cycle time 70 tAVQV tACC Address to output delay - tELQV tCE Chip enable to output tGLQV tOE -80 Max Min -90 -120 Max Min Max Min Max Unit 80 - 90 - 120 - ns 70 - 80 - 90 - 120 ns - 70 - 80 - 90 - 120 ns Output enable to output - 30 - 30 - 35 - 50 ns tOES Output enable setup time 0 - 0 - 0 - 0 - ns tEHQZ tDF Chip enable to output High Z - 20 - 20 - 30 - 30 ns tGHQZ tDF Output enable to output High Z - 20 - 20 - 30 - 30 ns tAXQX tOH Output hold time from addresses, first occurrence of C E or OE 0 - 0 - 0 - 0 - ns Output enable hold time: Read 10 - 10 - 10 - 10 - ns tOEH Output enable hold time: Toggle and data polling 10 - 10 - 10 - 10 - ns tRH RESE T high to output delay - 50 - 50 - 50 - 50 ns tREADY RESE T pin low to read mode - 10 - 10 - 10 - 10 µs tRP RESE T pulse 500 - 500 - 500 - ns tPHQV 500 Read waveform tRC Addresses stable Addresses tACC CE tDF tOE tOES OE tOEH WE tCE Outputs High Z tOH Output valid High Z tRH R ESE T 3/20/01; V.0.9.3 Alliance Semiconductor P. 16 of 25 AS29LV400 March 2001 ® AC parameters — write cycle WE controlled -70 -80 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 70 - 80 - 90 - 120 - ns tAVWL tAS Address setup time 0 - 0 - 0 - 0 - ns tWLAX tAH Address hold time 45 - 45 - 45 - 50 - ns tDVWH tDS Data setup time 35 - 35 - 45 - 50 - ns tWHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - ns tELWL tCS CE setup time 0 - 0 - 0 - 0 - ns tWHEH tCH CE hold time 0 - 0 - 0 - 0 - ns tWLWH tWP Write pulse width 35 - 35 - 35 - 50 - ns tWHWL tWPH Write pulse width high 30 - 30 - 30 - 30 - ns Write waveform WE controlled 3rd bus cycle Addresses tWC tAS 555h Program address DATA polling Program address tAH tCH CE tGHWL; tOES OE tWP WE tCS tWHWH1 or 2 tWPH tDH DATA 3/20/01; V.0.9.3 Program data A0h DQ 7 DOUT tDS Alliance Semiconductor P. 17 of 25 AS29LV400 March 2001 ® AC parameters — write cycle 2 CE controlled -70 -80 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 70 - 80 - 90 - 120 - ns tAVEL tAS Address setup time 0 - 0 - 0 - 0 - ns tELAX tAH Address hold time 45 - 45 - 45 - 50 - ns tDVEH tDS Data setup time 35 - 35 - 45 - 50 - ns tEHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tGHEL tGHEL Read recover time before write 0 - 0 - 0 - 0 - ns tWLEL tWS WE setup time 0 - 0 - 0 - 0 - ns tEHWH tWH WE hold time 0 - 0 - 0 - 0 - ns tELEH tCP CE pulse width 35 - 35 - 35 - 50 - ns tEHEL tCPH CE pulse width high 30 - 30 - 30 - 30 - ns Write waveform 2 CE controlled DATA Addresses 555h Program address tWC tAS polling Program address tAH WE tGHEL, tOES OE tCP tWHWH1 or 2 CE tCPH tDH DATA A0h Program data DQ 7 DOUT tDS 3/20/01; V.0.9.3 Alliance Semiconductor P. 18 of 25 AS29LV400 March 2001 ® AC parameters — temporary sector unprotect JEDEC Symbol -70 -80 -90 -120 Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tVIDR VID rise and fall time 500 - 500 - 500 - 500 - ns 4 - 4 - 4 - 4 - µs RESE T setup time for tRSP temporary sector unprotect Temporary sector unprotect waveform 10V 0 or 3V R ESE T tVIDR CE 0 or 3V tVIDR Program/erase command sequence WE tRSP RY/BY AC parameters — R ES E T JEDEC Symbol -80 -90 -120 Parameter Min Max Min Max Min Max Min Max Unit tRP R ES E T pulse 500 - 500 - 500 - 500 - ns - 50 - 50 - 50 - 50 ns - 10 - 10 - 10 - 10 µs tRH tREADY RE SET -70 Std Symbol R ES E T High time before Read R ES E T Low to Read mode waveform tRP RESET tRP tREADY RY/BY tRH DQ status status valid data valid data Erase waveform ×16 mode tWC Addresses tAS 555h 2AAh 555h 555h 2AAh Sector address tAH CE tGHWL OE tWP tWC WE tWPH tCS tDH AAh Data 55h 80h AAh 55h 10h for Chip Erase 30h tDS 3/20/01; V.0.9.3 Alliance Semiconductor P. 19 of 25 AS29LV400 March 2001 ® AC Parameters — READY/BUSY JEDEC Symbol -70 -80 -90 -120 Std Symbol Parameter Min Max Min Max Min Max Min Max Unit - tVCS VCC setup time 50 - 50 - 50 - 50 - µs - tRB Recovery time from RY/BY 0 - 0 - 0 - 0 - ns - tBUSY Program/erase valid to RY/BY delay 90 - 90 - 90 - 90 - ns RY/B Y waveform CE Rising edge of last WE signal WE RY/B Y tri-stated open-drain tBUSY Program/erase operation tRB VCC tVCS DATA polling waveform tCH CE tDF tOE OE tOEH WE tCE tOH DQ7 Output DQ 7 Input DQ7 Output High Z tWHWH1 or 2 Toggle bit waveform CE tOEH WE OE DQ6 tOE tDH 3/20/01; V.0.9.3 toggle Alliance Semiconductor toggle no toggle P. 20 of 25 AS29LV400 March 2001 ® Word/byte configuration -70 JEDEC Symbol Std Symbol Parameter - tELFL/tELFH - BYTE -80 -90 -120 Min Max Min Max Min Max Min Max Unit CE to BYTE switching Low or High - 10 - 10 - 10 - 10 ns tFLQZ B Y TE switching Low to output High-Z - 30 - 30 - 35 - 40 ns tFHQZ B Y TE switching High to output Active 70 - 80 - 90 - 120 - ns read waveform CE OE B Y TE BYTE Word to Byte tELFL DQ15/A-1 tELFH B Y TE Byte to Word DQ0-DQ14 Data output DQ0-DQ14 DQ0-DQ7 Data output DQ15 output tFLQZ DQ0-DQ14 DQ0-DQ7 Data output DQ15/A-1 Address input Address input DQ0-DQ14 Data output DQ15 output tFHQV BYTE write waveform CE falling edge of last WE signal WE BY TE tSET (tAS) See Erase/Program operations table for tAS and tAH specifications. tHOLD (tAH) Sector protect/unprotect RE SE T# VID VIH SA, A6, A 1 , A0 Don’t care Valid* Don’t care S e c to r p ro te c t/ u n pro t e c t DATA CE # 60h 1 µs 60h Don’t care Valid* Don’t care Valid* Verify 40h Don’t care Status Sector protect: 100 µs Sector unprotect: 10 ms W E# O E# * For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0. 3/20/01; V.0.9.3 Alliance Semiconductor P. 21 of 25 AS29LV400 March 2001 ® AC test conditions +3.0V 1N3064 or equivalent 2.7KΩ Device under test 6.2KΩ CL * VSS 1N3064 or equivalent VSS VSS Test specifications Test Condition -70, -90, -80 -120 Output Load Unit 1 TTL gate Output Load Capacitance CL (including jig capacitance) 30 Input Rise and Fall Times 100 pF 5 ns 0.0-3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Erase and programming performance Limits Parameter Min Typical Max Unit - 1.0 15 sec Byte - 10 300 µs Word - 15 360 µs - 7. 2 27 sec - 100,000 - cycles Sector erase and verify-1 time (excludes 00h programming prior to erase) Programming time Chip programming time Erase/program cycles * * Erase/program cycle test is not verified on each shipped unit. Latchup tolerance Parameter Min Max Unit Input voltage with respect to VSS on A9, OE , and RE SET pin -1.0 +12.0 V Input voltage with respect to VSS on all DQ, address, and control pins -0.5 VCC+0.5 V Current -100 +100 mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. 3/20/01; V.0.9.3 Alliance Semiconductor P. 22 of 25 AS29LV400 March 2001 ® Recommended operating conditions Parameter Supply voltage Input voltage Symbol Min Max Unit VCC +2.7 +3.6 V VSS 0 0 V VIH 1.9 VCC + 0.3 V VIL –0.5 0.8 V Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage (Input or DQ pin) VIN –0.5 VCC+ 0.5 V Input voltage (A9 pin, OE , RES ET ) VIN –0.5 +12.5 V Power supply voltage VCC -0.5 +4.0 V Operating temperature TOPR –55 +125 °C Storage temperature (plastic) TSTG –65 +150 °C Short circuit output current IOUT 150 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TSOP pin capacitance Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 pF SO pin capacitance Symbol Parameter Test setup Typ Max Unit CIN Input capacitance VIN = 0 6 7.5 pF COUT Output capacitance VOUT = 0 8.5 12 pF CIN2 Control pin capacitance VIN = 0 8 10 pF Data retention Parameter Minimum pattern data retention time 3/20/01; V.0.9.3 Alliance Semiconductor Temp.(°C) Min Unit 150° 10 years 125° 20 years P. 23 of 25 AS29LV400 March 2001 ® Thin small outline package (TSOP-I) Package dimensions b e 48-pin 12×20 c A2 L pin 1 A pin 48 pin 24 D Min Max – 1.27 0.05 0.15 0.95 1.05 0.17 0.27 0.15 nominal 18.20 18.60 0.50 nominal 11.90 12.10 19.80 20.20 0.50 0.70 0° 5° A A1 A2 b c D e E Hd L α A1 Hd pin 25 48-pin α E Small Outline Plastic (SO) Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 JEDEC MO - 175 AA 44-pin SO Min (mm) Max (mm) A – 3.1 A1 0.05 – A2 2.5 2.9 b 0.25 0.45 c 0.09 0.25 d 28.0 28.4 e 12.4 12.8 E 1.27 (typical) He 16.05 (typical) l 0.73 3/20/01; V.0.9.3 1.3 e He SO 1 2 3 4 5 6 7 8 0–10° 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d A2 A A1 b l E Alliance Semiconductor P. 24 of 25 March 2001 AS29LV400 ® AS29LV400 ordering codes Package \ Access Time 70 ns (commercial/ industrial) 80 ns (commercial/ industrial) 90 ns (commercial/ industrial) 120 ns (commercial/ industrial) TSOP, 12×20 mm, 48-pin Top boot configuration AS29LV400T-70TC AS29LV400T-70TI AS29LV400T-80TC AS29LV400T-80TI AS29LV400T-90TC AS29LV400T-90TI AS29LV400T-120TC AS29LV400T-120TI TSOP, 12×20 mm, 48-pin Bottom boot configuration AS29LV400B-70TC AS29LV400B-70TI AS29LV400B-80TC AS29LV400B-80TI AS29LV400B-90TC AS29LV400B-90TI AS29LV400B-120TC AS29LV400B-120TI SO, 13.3 mm, 44-pin Top boot configuration AS29LV400T-70SC AS29LV400T-70SI AS29LV400T-80SC AS29LV400T-80SI AS29LV400T-90SC AS29LV400T-90SI AS29LV400T-120SC AS29LV400T-120SI SO, 13.3 mm, 44-pin Bottom boot configuration AS29LV400B-70SC AS29LV400B-70SI AS29LV400B-80SC AS29LV400B-80SI AS29LV400B-90SC AS29LV400B-90SI AS29LV400B-120SC AS29LV400B-120SI Shaded area indicates advance information. Avialability of SO package is TBD. AS29LV400 part numbering system AS29LV 400 3V Flash EEPROM prefix Device T= Top boot configuration number B= Bottom boot configuration 3/20/01; V.0.9.3 X –XXX X Package: Address S = SO access time T = TSOP Alliance Semiconductor X X Temperature range: C = Commercial: 0°C to 70°C I = Industrial: -40°C to 85°C Options: B = Burn-in H = High ISB (<1mA) Blank= Standard P. 25 of 25 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. 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