EL4583 ® Data Sheet November 12, 2010 Sync Separator, 50% Slice, S-H, Filter, HOUT Features The EL4583 extracts timing from video sync in NTSC, PAL, and SECAM systems, and non standard formats, or from computer graphics operating at higher scan rates. Timing adjustment is via an external resistor. Input without valid vertical interval (no serration pulses) produces a default vertical output. • Single supply, +5V operation Outputs are: composite sync, vertical sync, filter, burst/back porch, horizontal, no signal detect, level, and odd/even output (in interlaced scan formats only). The EL4583 sync slice level is set to the mid-point between sync tip and the blanking level. This 50% point is determined by two internal sample and hold circuits that track sync tip and back porch levels. It provides hum and noise rejection and compensates for input levels of 0.5V to 2.0VP-P. A built in filter attenuates the chroma signal to prevent color burst from disturbing the 50% sync slice. Cut off frequency is set by a resistor to ground from the Filter Cut Off pin. Additionally, the filter can be by-passed and video signal fed directly to the Video Input. The level output pin provides a signal with twice the sync amplitude which may be used to control an external AGC function. A TTL/CMOS compatible No Signal Detect Output flags a loss or reduction in input signal level. A resistor sets the Set Detect Level. • NTSC, PAL, and SECAM sync separation • Precision 50% slicing • Built-in programmable color burst filter • Decodes non-standard vertical • Horizontal sync output • Sync. pulse amplitude output • Same socket can be used for 8 Ld EL4581 • Low-power CMOS • Detects loss of signal • Resistor programmable scan rate • Few external components • Available in 16 Ld PDIP and 16 Ld SO (0.150”) packages • Pb-free plus anneal available (RoHS compliant) Applications • Video special effects • Video test equipment • Video distribution • Multimedia • Displays • Imaging The EL4583 is manufactured using Intersil’s high performance analog CMOS process. • Video data capture • Video triggers Ordering Information PART TAPE & PART NUMBER MARKING REEL PACKAGE PKG. DWG. # EL4583CN EL4583CN - 16 Ld PDIP EL4583CS EL4583CS - 16 Ld SO (0.150”) MDP0027 EL4583CS-T7 EL4583CS 7” 16 Ld SO (0.150”) MDP0027 EL4583CS-T13 EL4583CS 13” 16 Ld SO (0.150”) MDP0027 EL4583CSZ - 16 Ld SO (0.150”) MDP0027 (Pb-free) EL4583CSZ-T7 EL4583CSZ (Note) 7” 16 Ld SO (0.150”) MDP0027 (Pb-free) EL4583CSZ-T13 EL4583CSZ (Note) 13” 16 Ld SO (0.150”) MDP0027 (Pb-free) EL4583CSZ (Note) FN7173.3 EL4583 (16 LD SO, PDIP) TOP VIEW MDP0031 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 Pinout FILTER CUT OFF 1 SET DETECT LEVEL 2 COMPOSITE SYNC OUT 3 FILTER INPUT 4 VERTICAL SYNC OUT 5 DIGITAL GND 6 FILTER OUTPUT 7 COMPOSITE VIDEO INPUT 8 16 ANALOG GND 15 HORIZONTAL SYNC OUT 14 VDD 13 ODD/EVEN OUTPUT 12 RSET* 11 BURST/BACK PORCH OUTPUT 10 NO SIGNAL DETECT OUTPUT 9 LEVEL OUTPUT *NOTE: RSET must be a 1% register CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2002, 2003, 2005, 2006, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. EL4583 Absolute Maximum Ratings (TA = 25°C) VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications VDD = 5V, TA = 25°C, RSET = 681kΩ, RF = 22kΩ, RLV = 82kΩ PARAMETER DESCRIPTION IDD VDD = 5V (Note 1) Clamp Voltage Pins 4, 8, unloaded Discharge Current Pins 4, 8, with signal (VIN = 2V) Discharge Current Pins 4, 8, no signal (Note 2) MIN TYP MAX UNIT 1.3 2.5 4 mA 1.55 1.8 V 3 6 12 µA 10 µA Clamp Charge Current Pins 4, 8, VIN = 1V 2 3 4 mA Ref. Voltage VREF Pin 12, VDD = 5V (Note 3) 1.5 1.75 2 V Filter Reference Voltage, VRF Pin 1 0.35 0.5 0.65 V Level Reference Current Pin 2 (Note 4) 1.5 2.5 3.5 µA VOL Output Low Voltage IOL = 1.6mA 350 800 mV VOH Output High Voltage IOH = -40µA 4 IOH = -1.6mA 2.4 V 4 V NOTES: 1. No video signal, outputs unloaded. 2. At loss of signal (pin 10 high) the pull down current source switches to a value of 10µA. 3. Tested for VDD 5V ±5%. 4. Current sourced from pin 2 is VREF/RSET. Dynamic Specifications RF = 22kΩ, RSET = 681kΩ, VDD = 5V, Video Input = 1VP-P, TA = 25°C, CL = 15pF, IOH = -1.6mA, IOL = 1.6mA PARAMETER DESCRIPTION Horizontal Pulse Width, Pin 15, tH (Note 1) Vertical Sync Width, Pin 5, tVS (Note 2) MIN TYP MAX UNIT 3.8 5 6.2 µs 195 Burst/Back Porch Width, Pin 11, tB (Note 1) Filter Attenuation FIN = 3.6MHz (Note 3) 2.7 3.7 12 Comp. Sync Prop. Delay, tCS VIN (Pin 4) - comp sync 250 Input Dynamic Range p-p NTSC signal 0.4 Slice Level Input voltage = 1VP-P 40 50 µs 4.7 µs dB 400 ns 2 V 60 % VSLICE/VBLANK 40 50 60 Level Out, Pin 9 Input voltage = 1VP-P, pin 4 500 600 700 mV Vertical Sync Default Time, tVSD (Note 4) 27 36 57 µs Loss of Signal Time-Out Pin 10 400 600 800 µs Burst/Back Porch Delay, tBD (See Figure 4) 250 400 ns NOTES: 1. Width is a function of RSET. 2. C/S, vertical, back porch and H are all active low, VOH = 0.8V; vertical is 3H lines wide of NTSC signal. 3. Attenuation is a function of RF. See filter typical characteristics. 4. Vertical pulse width in absence of serrations on input signal. 2 FN7173.3 November 12, 2010 EL4583 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 PIN NAME PIN FUNCTION Filter Cut-Off A resistor RF connected between this input and ground determines the input filter characteristic. Increasing RF increases the filter 3.58MHz color burst attenuation. See the typical performance characteristics. Set Detect Level A resistor RLV connected between pin 2 and ground determines the value of the minimum signal which triggers the loss of signal output on pin 10. The relationship is VPMIN = 0.75RLV/RSET, where VPMIN is the minimum detected sync pulse amplitude applied to pin 4. See the typical performance characteristics. Composite This output replicates all the sync inputs on the input video. Sync Output Filter Input The filter is a 3 pole active filter with a gain of 2, designed to produce a constant phase delay of nominally 260ns with signal amplitude. Resistor RF on pin 1 controls the filter cut-off. An internal clamp sets the minimum voltage on pin 4 at 1.55V when the input becomes low impedance. Above the clamp voltage, an input current of 1µA charges the input coupling capacitor. With loss of signal, the current source switches to a value of 10µA, for faster signal recovery. Vertical Sync The vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the input Output signal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore be slightly more than 3H lines wide. Digital Ground This is the ground return for digital buffer outputs. 7 Filter Output Output of the active 3 pole filter which has its input on pin 4. It is recommended to ac couple the output to pin 8. 8 Video Input 9 10 11 Level Output This pin provides an analog voltage which is nominally equal to twice the sync pulse amplitude of the video input signal applied to pin 4. It therefore provides an indication of signal strength. No Signal Detect Output RSET 13 Odd/Even Output 14 VDD 5V 16 This is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below a predetermined amplitude as set by RLV on pin 2. There will be several horizontal lines delay before the output is initiated. Burst/Back The start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of serration Porch Output pulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse width is a function of RSET. This output can be used for d.c. restore functions where the back porch level is a known reference. 12 15 This input can be directly driven by the signal if it is desired to bypass the filter, for example, in the case of strong clean signals. This input is 6dB less sensitive than the filter input. The current through the resistor RSET determines the timing of the functions within the I.C. These functions include the sampling of the sync pulse 50% point, back porch output and the 2H eliminator. For faster scan rates, the resistor needs to be reduced inversely. For NTSC 15.7kHz scan rate RSET is 681k 1%. RSET must be a 1% resistor. Odd-even output is low for even field and high for odd field. The operation of this circuit has been improved for rejecting spurious noise pulses such as those present in VCR signals. The internal circuits are designed to have a high immunity to supply variations, although as with most I.C.s a 0.1µF decoupling capacitor is advisable. Horizontal This output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading edge Sync Output of the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signal during vertical blanking are eliminated with an internal 2H eliminator circuit. Analog Ground This is the ground return for the signal paths in the chips, RSET, RF and RLV. 3 FN7173.3 November 12, 2010 EL4583 Typical Performance Curves RSET vs Horizontal Frequency Back Porch Clamp On Time vs RSET Vertical Default Delay Time vs RSET Filter 3dB BW vs RF Level Out (Pin 9) vs Sync. Tip Amplitude Minimum Signal Detect vs RLV Filter Attenuation vs RF @ f = 3.58MHz Note 1: For RLV < 1000kΩ, no signal detect output (pin 10) will default high at minimum signal sensitivity specification, or at complete loss of signal. 4 FN7173.3 November 12, 2010 EL4583 Typical Performance Curves (Continued) Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1.8 2 1.54W PDIP16 1.4 1.136W 1.2 θJA=81°C/W Power Dissipation (W) Power Dissipation (W) 1.6 1.8 1 0.8 SO16 (0.150”) 0.6 θJA=110°C/W 0.4 0.2 1.786W 1.6 PDIP16 1.563W 1.4 θJA=70°C/W 1.2 1 SO16 (0.150”) θJA=80°C/W 0.8 0.6 0.4 0.2 0 0 0 25 50 75 85 100 Ambient Temperature (°C) 5 125 150 0 25 50 75 100 125 150 Ambient Temperature (°C) FN7173.3 November 12, 2010 EL4583 Timing Diagram NOTES: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). f. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync. FIGURE 1. 6 FN7173.3 November 12, 2010 EL4583 FIGURE 2. FIGURE 3. 7 FN7173.3 November 12, 2010 EL4583 FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL Description of Operation A simplified block schematic is shown in Figure 1. The following description is intended to provide the user with sufficient information to understand the effects of the external components and signal conditions on the outputs of the integrated circuit. The video signal is AC coupled to pin 4 via the capacitor C1, nominally 0.1µF. The clamp circuit A1 will prevent the input signal on pin 4 going more negative than 1.5V, the value of reference voltage VR1. Thus the sync tip, the most negative part of the video waveform, will be clamped at 1.5V. The current source I1, nominally 6µA, charges the coupling capacitor during the remaining portion of the H line, approximately 58µs for a 15.75kHz timebase. From I • t = C • V, the video time-constant can be calculated. It is important to note that the charge taken from the capacitor during video 8 must be replaced during the sync tip time, which is much shorter, (ratio of x 12.5). The corresponding current to restore the charge during sync will therefore be an order of magnitude higher, and any resistance in series with CI will cause sync tip crushing. For this reason, the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided. The user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 4 to the 5V supply. The maximum voltage across the resistance will be VDD less 1.5V, for black level. For a net discharge current greater than zero, the resistance should be greater than 450k. This will have the effect of increasing the time constant and reducing the degree of picture tilt. The current source I1 directly tracks reference current ITR and thus increases with scan rate adjustment, as explained later. FN7173.3 November 12, 2010 EL4583 The signal is processed through an active 3 pole filter (F1) designed for minimum ripple with constant phase delay. The filter attenuates the color burst by 12dB and eliminates fast transient spikes without sync crushing. An external filter is not necessary. The filter also amplifies the video signal by 6dB to improve the detection accuracy. The filter cut-off frequency is controlled by an external resistor from pin 1 to ground. Internal reference voltages (block VREF) with high immunity to supply voltage variation are derived on the chip. Reference VR4 with op-amp A2 forces pin 12 to a reference voltage of 1.7V nominal. Consequently, it can be seen that the external resistance RSET will determine the value of the reference current ITR. The internal resistance R3 is only about 6kΩ, much less than RSET. All the internal timing functions on the chip are referenced to ITR and have excellent supply voltage rejection. To improve noise immunity, the output of the 3 pole filter is brought out to pin 7. It is recommended to AC couple the output to pin 8, the video input pin. In case of strong clean video signal, the video input pin, pin 8, can be driven by the signal directly. Comparator C2 on the input to the sample and hold block (S/H) compares the leading and trailing edges of the sync. pulse with a threshold voltage VR2 which is referenced at a fixed level above the clamp voltage VR1. The output of C2 initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8µs to enable the actual sample of 2µs to be taken on the optimum section of the sync. pulse tip. The acquisition time of the circuit is about three horizontal lines. The double poly CMOS technology enables long time constants to be achieved with small high quality on-chip capacitors. The back porch voltage is similarly derived from the trailing edge of sync, which also serves to cut off the tip sample if the gate time exceeds the tip period. Note that the sample and hold gating times will track RSET through IOT. The vertical circuit senses C/S edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out with the longer vertical sync. pulse widths. The internal timing circuits are referenced to IOT and VR3, the time-out period being inversely proportional to the timing current. The vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out. In the absence of a serration pulse, an internal timer will default the start of vertical. The horizontal circuit senses C/S edges and produces the true horizontal pulses of nominal width 5µs. The leading edge is triggered from the leading edge of the input H sync, with the same prop. delay as composite sync. The half line pulses present in the input signal during vertical blanking are removed with an internal 2H eliminator circuit. The 2H eliminator initiates a time out period after a horizontal pulse is generated. The time out period is a function of IOT which is set by RSET. The back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse. The period of this pulse is again a function of IOT and will therefore track the scan rate set by RESET. The odd/even circuit (O/E) tracks the relationship of the horizontal pulses to the leading edge of the vertical output and will switch on every field at the start of vertical. Pin 13 is high during an odd field. Loss of video signal can be detected by monitoring the No Signal Detect Output pin 10. The VTIP voltage held by the sample and hold is compared with a voltage level set by RLV on pin 2. Pin 10 output goes high when the VTIP falls below RLV set value. VTIP voltage is also passed through an amplifier with gain of 2 and buffed to pin 9. This provides an indication of signal strength. This signal (Level Output) can be used for AGC applications. The 50% level of the sync tip is derived through the resistor divider R1 and R2, from the sample and held voltages VTIP and VBP and applied to the plus input of comparator C1. This comparator has built in hysteresis to avoid false triggering. The output of C2 is a digital 5V signal which feeds the C/S output buffer B1, the vertical, back porch and odd/even functions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN7173.3 November 12, 2010 EL4583 Block Diagram * NOTE: RSET must be a 1% resistor. FIGURE 5. STANDARD (NTSC INPUT) H. SYNC DETAIL 10 FN7173.3 November 12, 2010