a Precision Dual Voltage Regulator Controller ADM1052 FEATURES Two Independent Controllers on One Chip Two 2.525 V Outputs Shutdown Inputs to Control Each Channel 2.5% Accuracy Over Line, Load, and Temperature Low Quiescent Current Low Shutdown Current Works with External N-Channel MOSFETs for Low Cost “Hiccup Mode” Fault Protection No External Voltage or Current Setting Resistors Small, 8-Lead SO Package APPLICATIONS Desktop Computers Servers Workstations GENERAL DESCRIPTION The ADM1052 is a dual, precision, voltage regulator controller intended for power rail generation and active bus termination on personal computer motherboards. It contains a precision 1.2 V bandgap reference and two channels consisting of control amplifiers driving external power devices. Each channel has a shutdown input to turn off amplifier output and “Hiccup Mode” protection circuitry for the external power device. The ADM1052 operates from a 12 V supply. This gives sufficient headroom for the amplifiers to drive external N-channel MOSFETs, operating as source-followers, as the external series pass devices. This has the advantage that N-channel devices are cheaper than P-channel devices of similar performance, and the circuit is easier to stabilize than one using P-channel devices in a common-source configuration. FUNCTIONAL BLOCK DIAGRAM 3.3V VCC ADM1052 CONTROL AMPLIFIER BANDGAP REFERENCE 100F FORCE 1 VCC VOUT1 SENSE 1 2 100F 50A SHUTDOWN CONTROL SHDN1 HICCUP COMPARATOR 3.3V CONTROL AMPLIFIER 100F FORCE 2 VCC SENSE 2 VOUT2 2 100F 50A SHUTDOWN CONTROL SHDN2 HICCUP COMPARATOR VCC POWER-ON RESET CLK/DELAY GENERATOR CLOCK OSCILLATOR GND REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 (VCC = 12 V 6%, VIN = 3.3 V, TA = 0C to 70C, both channels, unless otherwise ADM1052–SPECIFICATIONS noted. See Test Circuit.) Parameter Min OUTPUT VOLTAGE Channel 1, Channel 2 OUTPUT VOLTAGE ACCURACY Load Regulation Line Regulation SHUTDOWN, SHDN1, SHDN2 Shutdown Input Low Voltage, V IL Shutdown Input High Voltage, V IH Supply Current, Normal Operation Supply Current, Shutdown Mode Max Unit Test Conditions/Comments V SHDN1, SHDN2 Floating +2.5 +5 +5 % mV mV VIN = 3.0 V to 3.6 V, IOUT = 10 mA to 1 A VIN = 3.3 V, IOUT = 10 mA to 1 A1 VIN = 3.0 V to 3.6 V, IOUT = 1 A1 5 dB V/µs µs µs kΩ V V 2.525 –2.5 –5 –5 CONTROL AMPLIFIER Control Amplifier Open-Loop Gain Control Amplifier Slew Rate Closed-Loop Settling Time Turn-On Time Sense Input Impedance 1 Force Output Voltage Swing, V F (High) Force Output Voltage Swing, V F (Low) HICCUP MODE Hiccup Mode Hold-Off Time Hiccup Mode Threshold Hiccup Comparator Glitch Immunity Hiccup Mode On-Time Hiccup Mode Off-Time Power-On Reset Threshold Typ 100 3 5 50 10 2 30 0.5 20 6 60 100 1.0 40 90 0.8 × VOUT 1.5 60 9 0.8 2.0 2.4 600 4.0 1000 ms V µs ms ms V V V mA µA IO = 10 mA to 2 A To 90% of Force High Output Level (CL = 470 pF) RL = 10 kΩ to GND RL = 10 kΩ to VCC Figure 2 Shutdown Inputs Floating Both Channels Shut Down NOTES 1 Guaranteed by design. Specifications subject to change without notice. –2– REV. A ADM1052 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS (TA = 25°C unless otherwise noted) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V SHDN1, SHDN2 to GND . . . . . . . . –0.3 V to (VCC + 0.3 V) SENSE1, SENSE2 to GND . . . . . . . . . . . . –0.3 V to +5.5 V FORCE1, FORCE2 . . . . . . . . Short-Circuit to GND or VCC Continuous Power Dissipation (TA = 70°C) . . . . . . . 650 mW 8-Lead SOIC . . . . . . . . . . . . (Derate 8.3 mW/°C above 70°C) Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Pin No. Mnemonic Function 1 FORCE 2 2 SENSE 2 3 SHDN2 4 5 GND SHDN1 6 SENSE 1 7 FORCE 1 8 VCC Output of Channel 2 control amplifier to gate of external N-channel MOSFET. Input from source of external MOSFET to inverting input of Channel 2 control amplifier, via output voltage-setting feedback resistor network. Digital Input. Active-low shutdown control with 50 µA internal pull-up. The output of Channel 2 control amplifier goes to ground when SHDN2 is taken low. Device Ground Pin. Digital Input. Active-low shutdown control with 50 µA internal pull-up. The output of Channel 1 control amplifier goes to ground when SHDN1 is taken low. Input from source of external MOSFET to inverting input of Channel 1 control amplifier, via output voltage-setting feedback resistor network. Output of Channel 2 control amplifier to gate of external N-channel MOSFET. 12 V Supply. THERMAL CHARACTERISTICS 8-Lead Small Outline Package: JA = 150°C/W ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1052JR 0°C to 70°C 8-Lead SOIC SO-8 12V PIN CONFIGURATION 3.3V 1F VCC PHD55N03LT FORCE 2 1 100F SENSE 2 2 ADM1052 8 VCC 7 FORCE 1 TOP VIEW SHDN2 3 (Not to Scale) 6 SENSE 1 FORCE 1 GND 4 5 SHDN1 VOUT1 SENSE 1 2 100F SHDN1 LEAVE OPEN OR CONNECT TO LOGIC SIGNALS IF SHUTDOWN REQUIRED 3.3V ADM1052 MTD3055VL SHDN2 100F FORCE 2 SENSE 2 GND VOUT2 2 100F Figure 1. Test Circuit CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM1052 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE ADM1052–Typical Performance Characteristics Tek Stop: 25.0MS/s [ T 56Acqs ] 2.55 T OUTPUT – V 2.54 T 2v 2.53 2.52 T 3v 2.51 1t 2.50 Ch1 500mV B W Ch2 20.0mV B W M 2.00s Ch1 Ch3 20.0mV B W 0 3.53V TPC 1. Line Transient Response, Channel 1 and Channel 2 0.2 0.4 0.6 0.8 1.0 CURRENT – A 1.2 1.4 1.6 1.8 TPC 4. Load Regulation, Channel 1 2.536 2.55 2.535 2.54 OUTPUT – V VOUT – V 2.534 2.533 2.532 2.53 2.52 2.531 2.51 2.530 2.529 2.9 2.50 3.0 3.1 3.2 3.3 VIN – V 3.4 3.5 3.6 0 3.7 0 2.541 –10 RIPPLE REJECTION – dB 2.542 2.540 VOUT – V 0.4 0.6 0.8 1.0 CURRENT – A 1.2 1.4 1.6 1.8 TPC 5. Load Regulation, Channel 2 TPC 2. Line Regulation, Channel 1 2.539 2.538 2.537 –20 –30 –40 –50 –60 2.536 2.535 2.9 0.2 –70 3.0 3.1 3.2 3.3 VIN – V 3.4 3.5 3.6 10 3.7 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 6. VCC Supply Ripple Rejection TPC 3. Line Regulation, Channel 2 –4– REV. A ADM1052 Tek Stop: Single Seq 50.0MS/s [ T 2.544 ] 2.542 2.538 1 2.536 T t OUTPUT – V 2.540 2.534 t 2.532 2.530 2.528 0 10 20 30 40 50 60 TEMPERATURE – C 70 80 Ch1 20.0mV B W 90 TPC 7. Regulator Output Voltage vs. Temperature Tek Stop: Single Seq 50.0MS/s [ T M 1.00s Ch1 –40mV TPC 10. Transient Response Channel 2, 10 mA to 2 A Output Load Step Tek Stop: Single Seq 50.0MS/s [ T ] ] t T t 1 t 1 T t Ch1 20.0mV B W M 1.00s Ch1 Ch1 20.0mV B W –45.0mV TPC 8. Transient Response Channel 1, 10 mA to 2 A Output Load Step Tek Stop: Single Seq 50.0MS/s [ T M 1.00s Ch1 37.6mV TPC 11. Transient Response Channel 2, 2 A to 10 mA Output Load Step Tek Stop: 10.0kS/s [ T ] 0Acqs ] Ch1 20.0mV B W M 1.00s Ch1 Ch1 10.0mV B W 5.2mV TPC 9. Transient Response Channel 1, 2 A to 10 mA Output Load Step REV. A t 1 t T t 1 t T M 5.00s Ch1 800mV TPC 12. Force Output In Hiccup Mode, Channel 1 –5– ADM1052 GENERAL DESCRIPTION “HICCUP MODE” FAULT PROTECTION The ADM1052 is a dual, precision, voltage regulator controller intended for power rail generation and active bus termination on personal computer motherboards. It contains a precision 1.2 V bandgap reference and two channels consisting of control amplifiers driving external power devices. Both channels have an output of nominally 2.525 V. Each channel has a shutdown input to turn off amplifier output and protection circuitry for the external power device. Hiccup mode fault protection is a simple method of protecting the external power device without the added cost of external sense resistors or a current sense pin on the ADM1052. In the event of a short-circuit condition at the output, the output voltage will fall. When the output voltage of a channel falls 20% below the nominal voltage, this is sensed by the hiccup comparator and the channel will go into hiccup mode, where the enable signal to the control amplifier is pulsed on and off with a 1:40 duty cycle. The ADM1052 operates from a 12 V VCC supply. The output is disabled until VCC climbs above the reset threshold (6 V–9 V). The output from the ADM1052 is used to drive external N-channel MOSFETs, operating as source-followers. This has the advantage that N-channel devices are cheaper than P-channel devices of similar performance, and the circuit is easier to stabilize than one using P-channel devices in a common-source configuration. To prevent the device inadvertently going into hiccup mode during power-up or during channel enabling, the hiccup mode is held off for approximately 60 ms on both channels. By this time the output voltage should have reached its correct value. In the case of power-up, the hold-off period starts when VCC reaches the power-on reset threshold of 6 V–9 V. In the case of channel enabling, the hold-off period starts when SHDN is taken high. Note that the hold-off timeout applies to both channels even if only one channel is disabled/enabled. The external power devices are protected by a “Hiccup Mode” circuit that operates if the circuit goes out of regulation due to an output short-circuit. In this case the power device is pulsed on/off with a 1:40 duty cycle to limit the power dissipation until the fault condition is removed. As the 3.3 V input to the drain of the MOSFET is not monitored, it should ideally rise at the same or a faster rate than VCC. At the very least it must be available in time for VOUT to reach its final value before the end of the power-on delay. If the output voltage is still less than 80% of the correct value after the poweron delay, the device will go into hiccup mode until the output voltage exceeds 80% of the correct value during a hiccup mode on-period. Of course, if there is a fault condition at the output during power-up, the device will go into hiccup mode after the power-up delay and remain there until the fault condition is removed. CIRCUIT DESCRIPTION CONTROL AMPLIFIERS The reference voltage is amplified and buffered by the control amplifiers and external MOSFETs, the output voltage of each channel being determined by the feedback resistor network between the sense input and the inverting input of the control amplifier. A power-on reset circuit disables the amplifier output until VCC has risen above the reset threshold (6 V–9 V). The effect of power-on delay is illustrated in Figure 2, which shows an ADM1052 being powered up with a fault condition. The output current rises to a very high value during the poweron delay, the device goes into hiccup mode, and the output is pulsed on and off at 1:40 duty cycle. When the fault condition is removed, the output voltage recovers to its normal value at the end of the hiccup mode off period. Each amplifier output drives the gate of an N-channel power MOSFET, whose drain is connected to the unregulated supply input and whose source is the regulated output voltage, which is also fed back to the appropriate sense input of the ADM1052. The control amplifiers have high current-drive capability so that they can quickly charge and discharge the gate capacitance of the external MOSFET, thus giving good transient response to changes in load or input voltage. The load current at which the ADM1052 will go into hiccup mode is determined by three factors: • The input voltage to the drain of the MOSFET, VIN SHUTDOWN INPUTS • The output voltage VOUT (–20%) Each channel has a separate shutdown input, which may be controlled by a logic signal and allows the output of the regulator to be turned on or off. If the shutdown input is held high or not connected, the regulator operates normally. If the shutdown input is held low, the enable input of the control amplifier is turned off and the amplifier output goes low, turning off the regulator. • The on-resistance of the MOSFET, RON IHICCUP = (VIN – (0.8 × VOUT))/RON It should be emphasized that the hiccup mode is not intended as a precise current limit but as a simple method of protecting the external MOSFET against catastrophic fault conditions such as output short circuits. –6– REV. A ADM1052 POR THRESHOLD 6V – 9V 12V SUPPLY VREF TURN-ON THRESHOLD 3.3V SUPPLY TO EXTERNAL MOSFET DRAIN GATE DRIVE TO EXTERNAL MOSFET MOSFET GATE THRESHOLD OUTPUT < 0.8 VREG FAULT REMOVED NORMAL OUTPUT VOLTAGE CHANNEL 1 OR CHANNEL 2 OUTPUT VOLTAGE DEVICE ENTERS HICCUP MODE HICCUP MODE HOLD-OFF TIME CHANNEL 1 OR CHANNEL 2 OUTPUT CURRENT FAULT CURRENT 2 AMPS OFF ON 1:40 DUTY CYCLE Figure 2. Power-On Reset and Hiccup Mode APPLICATIONS INFORMATION PCB LAYOUT For optimum voltage regulation, the loads should be placed as close as possible to the source of the output MOSFETs and feedback to the sense inputs should be taken from a point as close to the loads as possible. The PCB tracks from the loads back to the sense inputs should be separate from the output tracks and not carry any load current. Similarly, the ground connection to the ADM1052 should be made as close as possible to the ground of the loads, and the ground track from the loads to the ADM1052 should not carry load current. Correct and incorrect layout practice is illustrated in Figure 3. 12V 12V VIN 3.3V VCC VCC FORCE 1 FORCE 1 SENSE 1 SENSE 1 VIN 3.3V FORCE 2 I1 SENSE 2 GND FORCE 2 LOAD 1 VOUT2 SENSE 2 I2 VOUT1 VOUT1 I1 VOUT2 GND LOAD 2 LOAD 1 I1 + I2 VOLTAGE DROP IN GROUND LEAD INCORRECT CORRECT Figure 3. Correct and Incorrect Layout Practice REV. A –7– I2 LOAD 2 VOLTAGE DROP BETWEEN OUTPUT AND LOAD ADM1052 In practice, the amount of decoupling required will depend on the application. PC motherboards are notoriously noisy environments, and it may be necessary to employ distributed decoupling to achieve acceptable noise levels on the supply rails. 12V 3.3V 1F VCC 100F As previously discussed, the load current at which an output goes into hiccup mode depends on the on-resistance of the external MOSFET. If the on-resistance is too low this current may be very high. While the Test Circuit (Figure 1) shows the use of the lower resistance PHD55N03LT from Philips on Channel 1 and the use of the higher resistance MTD3055VL from Motorola on Channel 2, the MTD3055VL is, in fact, suitable for both channels. Similarly, the PHB11N06LT from Philips is also suitable for both channels. VOUT1 SENSE 1 2 100F SHDN1 LEAVE OPEN OR CONNECT TO LOGIC SIGNALS IF SHUTDOWN REQUIRED 3.3V ADM1052 100F SHDN2 C02127–0–1/01 (rev. A) CHOICE OF MOSFET FORCE 1 FORCE 2 THERMAL CONSIDERATIONS Heat generated in the external MOSFET must be dissipated and the junction temperature of the device kept within acceptable limits. The power dissipated in the device is, of course, the drain-source voltage multiplied by the load current. The required thermal resistance to ambient is given by VOUT2 SENSE 2 2 100F GND Figure 4. Typical Application Circuit JA = TJ(MAX) – TAMB(MAX)/(VDS(MAX) × IOUT(MAX)) Surface-mount MOSFETs such as those specified must rely on heat conduction through the device leads and the PCB. One square inch of copper (645 sq. mm) gives a thermal resistance of around 60°C/W for a SOT-223 surface-mount package and 80°C/W for a SO-8 surface-mount package. SUPPLY DECOUPLING The supply to the drain of an external MOSFET should be decoupled as close as possible to the drain pin of the device, with a 100 µF capacitor to ground. The output from the source of the MOSFET should be decoupled as close as possible to the source pin of the device. Decoupling capacitors should be chosen to have a low Equivalent Series Resistance (ESR). With the MOSFETs specified and two 100 µF capacitors in parallel, the circuit will be stable for load currents up to 2 A. The VCC pin of the ADM1052 should be decoupled with a 1 µF capacitor to ground, connected as close as possible to the VCC and GND pins. For higher power dissipation than can be accommodated by a surface-mount package D2PAK or TO-220 devices are recommended. These should be mounted on a heatsink with a thermal resistance low enough to maintain the required maximum junction temperature. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PRINTED IN U.S.A. 8-Lead Small Outline Package (Narrow Body, SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0196 (0.50) 45 0.0099 (0.25) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 8 0.0500 (1.27) 0.0098 (0.25) 0 0.0160 (0.41) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) –8– REV. A