ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. Description Features Guaranteed zero reading with zero input The ES5116 is low power monolithic CMOS 3 1/2 digit LCD display A/D converter. It contains the internal clock, voltage reference,seven-segment decoders, LCD display drivers and a back plane driver. The improved internal zener reference voltage circuit gives the analog common a small temperature coefficient of C typically. The high accuracy characteristics of the ES5116 perform very low linearity error and roll-over error. The high input impedance ( ) and low input leakage current (1pA typical) give the ES5116 a good application in the field of high impedance circuit measurement. The differential input and reference are suitable for measuring bridge transducer or ohms by using ratio-metric method. The dual slope conversion technique makes the ES5116 a good normal and common mode rejection ratio. With a suitable oscillator frequency, the ES5116 has a high rejection of 50Hz, 60Hz and 400Hz line frequency noise. With single power supply, a few passive components and a LCD display, ES5116 can be built as high performance panel meter. Existing Display hold, low battery flag integration and De-integration are four additional features. Low input leakage current (1pA typical) Internal Reference with low temperature drift ( C typically) Low noise (15uVp-p typical) Direct LCD display driver-no external components required Differential input and voltage reference Precision null detection with true polarity at zero Internal clock circuit No additional active circuits required Low Battery Indication Display-Hold Application 1. Digital panel meters 2. Digital multi-meters 3. Thermometers 4. Capacitance meters 5. pH meters 6. Photo-meters 1 July 21, 2003 IN HI COMMON 2 INT A/Z INT 10uA V+ REF LO REF HI DEH A/Z DE(1) DEH DEH DEH A/Z CAEF RINT V- INPUT HIGH CREF- 2.9V CREF+ BUFF V+ DISPLAY FONT INT HOLD INPUT LOW MOEDS INT DINT OSC1 OSC2 c b CONTROL LOGIC TENS LATCH 7 SECHEHT DECODE OSC3 Vin =1V UNITS 200 V- TEST V+ Low battery BACK PLANE Low battery detect 500 6.2V BAT 7 SECHEHT DECODE PHASE DRIVER d INTERNAL DIGITAL GROUND ++ FROM COMPARATOR OUTPUT CLOCK LCD 7 SECHEHT DECODE TO SWITCH DRIVERS DIGITAL GROUND 2mA TO SECON OUTPUT e 1b a g CONTROL LOGIC TO DIGITAL SECTION COHPARATOR A.Z INTEGRATOR 5mA TYPICAL SECHEHT f 1a CYRUSTEK CO. LO CAZ 6.2V IN AUTO ZERO CINT ES5116 3 1/2 DVM with hold and low battery indication Block Diagram July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. Pin Assignment 1 QFP-44pin package INT V- 40 BUFF COMMON 41 A.Z C-REF 42 INLO C+REF 43 INHI REFLO INTEN REFHI DEEN 44 39 38 37 36 35 34 1 2 3 OS3 4 HOLD 5 OS2 6 OS1 7 V+ 8 D1 9 C1 10 B1 11 ES5116Q TEST 12 A1 13 F1 14 G1 15 E1 16 D2 3 17 C2 18 B2 19 A2 20 F2 21 E2 33 LB 32 G2 31 C3 30 A3 29 G3 28 BP 27 POL 26 AB4 25 E3 24 F3 23 B3 22 D3 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. 2 SSOP-48pin package 1 48 OS1 OS2 HOLD OS3 TEST INTEN DEEN REFHI NC NC REFLO C-REF C+REF COMMON INHI INLO A.Z. BUFF INT VLB G2 C3 A3 ES5116V V+ D1 NC NC C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP G3 24 25 Pin Description Pin No. Symbol Type DEEN O 1 2 INTEN O 3 TEST I 4 OS3 – 5 HOLD I 6 OS2 – 7 OS1 – 8 V+ – 9 D1 O 10 C1 O 11 B1 O 12 A1 O 13 F1 O 14 G1 O 15 E1 O 16 D2 O 17 C2 O 18 B2 O 19 A2 O continued on next page Description De-integration status flag. Integration status flag. Pull high to V+ all LCD segments will be activated. Crystal oscillator connection. Hold pin, pull high to hold display. Crystal oscillator connection. Crystal oscillator connection. Positive supply voltage. Connecting to battery positive terminal. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. LCD segment line. 4 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. continued from previous page Pin No. Symbol Type Description 20 F2 O LCD segment line. 21 E2 O LCD segment line. 22 D3 O LCD segment line. 23 B3 O LCD segment line. 24 F3 O LCD segment line. 25 E3 O LCD segment line. 26 AB4 O LCD segment line. 27 POL O LCD segment line. 28 BP O LCD segment line. 29 G3 O LCD segment line. 30 A3 O LCD segment line. 31 C3 O LCD segment line. 32 G2 O LCD segment line. 33 LB O Low-battery flag segment driver. 34 V– Negative supply voltage. Connecting to battery negative terminal. 35 INT O Integration cycle output. 36 BUFF O Integration resistor connection for buffer output. 37 A.Z – Auto-zero capacitor connection. 38 INLO – Low analog input signal connection. 39 INHI – High analog input signal connection. 40 COMMON – Set the common-mode voltage for the system. 41 C+REF – Positive capacitor connection for on-chip DC-DC converter. 42 C-REF – Negative capacitor connection for on-chip DC-DC converter. 43 REF LO I Low differential reference input connection. 44 REF HI I High differential reference input connection. Note: 1. Pin No. of QFP-44 pin package. Absolute Maximum Ratings Characteristic Supply Voltage ( to ! ) Analog Input Voltage (either input) Reference Input Voltage (either input) Clock Input Power Dissipation(plastic package) Operating Temperature Storage Temperature Lead Temperature (soldering,10sec) Rating 12V to to TEST to 800mW C to "# C $% & C to ' C ( # C Electrical Characteristics 5 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. Parameter Zero Input Reading Symbol – Ratio-metric Reading – Linearity (Max.deviation from best straight line fit) roll-over Error – Common Mode Rejection Ratio Low battery flag Noise – Input Leakage Current Zero Reading Drift – – Analog COMMON Voltage (with respect to V ) – Analog COMMON Temperature Coefficient – Segment Drive Voltage Back plane Drive Voltage Supply Current (Does not include COMMON current) – – – – – – Test Condition Min. *),+.-/ 0 Full- -000.0 Scale=200.0mV )54 =*687:9 , 999 *687:9 =100mV full-Scale=200mV or -1 Full-Scale=2.000V -1 $;*)54 = "<*)54 = 200.0mV <>? = 1 1V,<)@4 =0V – Full-Scale=200.0mV V+ to V6.7 JLK)54 M -A 0CBEDFHGIG;$ – GIN<-O( 3 P0 – *)54Q-R 0 )54 0 , – C<=SUT <= "#V C 25K Between 2.8 Common and Positive Supply 25K Between – Common and , C<=TA<= #V C 4 to =9V to 4 – *)54 =0V Typ. 12 3 Max. +000.0 Units Digital Reading 999/1000 1000 Digital Reading 12 ( 1 Counts 12 ( +1 Counts 50 – uV/V 7.0 15 7.3 – V uVp-p 1 0.2 10 1 pA uV/ C 3.0 3.2 V 60 75 ppm/ C 5 5 0.6 6 6 0.75 V V mA Functional Description 1 Analog Common The COMMON pin is used to set the common-mode voltage for the system which the input signals are floating. In most of the applications, INLO, REFLO and COMMON pins are usually connected. It can remove common-mode voltage concerns. In other applications, INLO does not connect with COMMON. The ES5116 generates a common mode voltage, which has the high CMRR (86dB typical.) Nevertheless, it should be care to prevent the output of the integrator from saturation. The COMMON pin is also used as a voltage reference. It outputs a voltage which is around 2.9 volts below the positive supply. The COMMON voltage has a low output impedance of '& typically. The analog COMMON is connected internally to an NMOS which can sink 30mA. This NMOS will hold the COMMON voltage at 2.9 volts when an external load attempts to pull the COMMON voltage toward the positive supply. The source current of COMMON is only 10uA, so it is easy to pull COMMON voltage to a more negative voltage. When the total supply voltage is large enough to cause the zener to regulate(>7V,) the COMMON voltage will have a low temperature coefficient less than WP C typically. This voltage can be used to generate the reference voltage. 2 Reference Voltage For an 1000 counts reading, the input signal must be equal to the reference voltage. As a result, it requires the input signal be twice the reference voltage for a 2000 counts full-scale reading. Thus, for the 200.0 mV and 2.000V full-scale, the reference voltage should equal 100.0mV and 1.000V, In some applications the full-scale input voltage may be different to 200 mV or 2.000 V. For example, in the 600 mV full-scale applications, the reference voltage should be set to 300 mV. 6 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. The differential reference should be used during the measurement of resistor by the ratio-metric method and when a digital reading of zero is desired for Vin - X 0, a compensating offset voltage can be applied between COMMON and INLO, and the voltage of being measured is connected between COMMON and INHI. 3 System Timing The oscillator frequency is divided by four prior to clocking the internal decade counters. The signal integration takes a fixed 1000 counts time period which is equal to 4000 clock pulses. The back plane drive signal is derived by dividing oscillator frequency by 800. To make a maximum noise rejection of line frequency(60Hz or 50Hz,) the signal integration period should be a multiple of the line frequency period. For 60Hz-noise rejection, oscillator frequencies of 120KHz, 80KHz, 60KHz, 48KHz, 40KHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 100KHz, 50KHz, 40KHz, etc. would be suitable. For all ranges of frequency Rosc should be 100K , Cosc is selected from the approximate equation f = 0.45/RC. For 48KHz clock (3reading/second), Cosc=100pF. 4 Integrating Resistor The input buffer amplifier and integrator are designed with class A output stages.The output stage idling current is 100 uA. Both of them can supply 20uA drive currents with negligible linearity errors. The integrating resistor is chosen to remain linear drive region in the output stage. It should not be so large that the leakage current of printed circuit board will induce errors. The recommended integrating resistor value for the 200 mV and 2 V full-scale are 47K and 470 K respectively. 5 Integrating Capacitor The integrating capacitor should be selected to maximize integrator output voltage swing without causing output saturation. For 3 readings/second (48KHz clock,) a 0.22uF value of Y[Z]\U^ is suggested. If a different oscillator frequency is used, Y_Z]\U^ must be changed in inverse proportion to maintain the nominal 1 2V integrator swing. The integrating capacitor must have low dielectric absorption to minimize roll-over error. An inexpensive polypropylene capacitor is re commented. 6 Auto-Zero Capacitor The auto-zero capacitor size has some influence on system noise. A 0.47uF capacitor is recommended for 200mV full scale. A 0.047uF capacitor is adequate for 2V full scale applications. A mylar type dielectric capacitor is adequate. 7 Reference Voltage Capacitor The reference voltage used to ramp the integrator output voltage back to zero during the reference integrate cycle is stored on Y_`badc . A 0.1uF value capacitor is acceptable when INLO is connected with COMMON. A mylar type dielectric capacitor is adequate. 8 TEST The TEST pin is tied to the internally generated digital ground through a 500 resistor. Its potential is 5V less than V+. The TEST pin load should be no more than 1 mA. If TEST is pulled high to V+, all segments plus the minus sign will be actived. It may destroy the LCD display as keeping in this mode for several minutes . 9 Segment Drivers For 3 readings/second (48KHz clock) the BP frequency is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven in the same frequency/amplitude. They are in phase with BP when the segment should be OFF, but out of phase when ON. The polarity indication is "ON" for negative voltage inputs. 7 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. 10 Integration Status(INTEN) The INTEN is an output signal of the converter, it keeps on "high" during the signal integration phase. 11 De-Integration Status(DEEN) The DEEN is an output signal of the converter, it keeps on "high" during the reference de-integration phase. 12 Hold When the hold pin is connected to V+ the conversion result will not be update. The conversion is still free running during hold mode. 13 Low Battery Flag(LB) When the supply voltage (V+ to V-) is less then 6.9 Volt, The LCD segment of Low Battery Flag is turned on. 0.22u 47K 0.47u 0.01u 0.1u 1M 24K 1K 44 43 42 41 40 39 38 37 36 35 34 SET 100.0mV 9V + IN Test Circuit 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 100K ES5116Q 100P 1 2 3 4 5 6 7 8 9 10 11 LCD DISPLAY Clock Frequency 48KHz (3 readings/sec) 8 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. Application Circuit 0.22u 47K 0.47u 0.01u 0.1u 1M 24K 1K 44 43 42 41 40 39 38 37 36 35 34 SET 100.0mV 9V + IN 1. This circuit uses analog COMMON voltage as reference voltage.Values here are for 200.0mV full scale,3readings/sec. 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 100K ES5116Q 100P 1 2 3 4 5 6 7 8 9 10 11 LCD DISPLAY Clock Frequency 48KHz (3 readings/sec) 9 July 21, 2003 ES5116 3 1/2 DVM with hold and low battery indication CYRUSTEK CO. 0.22u 470K 0.047u 0.1u 0.01u 1M 24K 25K 44 43 42 41 40 39 38 37 36 35 34 SET 1V 9V + IN 2. The values of this circuit are for 2.000V full scale,3 readings/sec. 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 100K ES5116Q 100P 1 2 3 4 5 6 7 8 9 10 11 LCD DISPLAY Clock Frequency 48KHz (3 readings/sec) 10 July 21, 2003