SPC500A1 512KB SOUND CONTROLLER GENERAL DESCRIPTION The SPC500A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 512K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 120 sec speech duration @ 7KHz sampling rate) and 128-byte working SRAM. It includes two Timer/Counters, 23 Software Selectable I/Os, two 8-bit current outputs D/A (or one PWM audio output) and serial interface I/O port. It provides Multi-Duty-Cycle output for remote control purposes. processing, melody and speech can be mixed into one output. For audio It operates over a wide voltage range of 2.4V - 5.5V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 2.2V. Volume control is provided. In addition, the SPC500A1 has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 8.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) – 6 clock cycles (max.). The SPC500A1 includes, not only the latest technology, but also the full commitment and technical support of Sunplus. FEATURES 8-bit microprocessor Low Voltage Reset Provides 512K-byte ROM for program and Volume control function audio data 128-byte working SRAM BLOCK DIAGRAM Software-based audio processing Wide operating voltage: 2.4V – 3.4V@ 5.0MHz 512K-byte ROM 8-bit RISC controller Two Timers TimeBase INT control 128-byte SRAM 3.6V – 5.5V@ 8.0MHz AUD1 Two 8-bit D/A (current) or Supports Crystal Resonator or Rosc XI Rosc (with Mask option) Low Voltage Reset CLK OSC XO Max. CPU clock: 5.0MHz@3V, 8.0MHz@5V PWM output AUD2 Serial interface I/O Two 12-bit timer/counters 23 Standby mode (Clock Stop mode) for power IOA3-0 (I/O) savings. Max. 2A @ 5V PINS GENERAL IOB3-0 (I/O) I/O PORT IOC6-0 (I/O) IOD7-0 (I/O) 500ns instruction cycle time @ 4.0MHz CPU clock APPLICATION FIELD 6 INT sources Intelligent education toys Key wake -up function Ex. Pattern to voice (animal, car, color, etc.) Provides 23 general I/Os Serial interface I/O Spelling (English or Chinese) Approx. 120 sec speech Math High end toy controller @ 7KHz sampling rate with ADPCM Talking instrument controller One PWM audio output (single speaker) General speech synthesizer Two DA output Industrial controller Multi-duty cycle mode Sunplus Technology Co., Ltd. 1 Rev.: 1.0 1999.11.04 SPC500A1 FUNCTION DESCRIPTIONS CPU The 8-bit microprocessor of SPC500A1 is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). SPC500A1 is able to perform with 8.0MHz (max.) depending on the application specifications. OSCILLATOR The SPC500A1 supports AT-cut parallel resonant oscillated Crystal / Resonator or RC Oscillator or external clock sources by mask option (select one from those three types). The design of application circuit should follow the vendors’ specifications or recommendations. The diagrams listed below are typical X’TAL/ROSC circuits for most applications: SPC500A1 XI/R SPC500A1 XO XI/R XO VDD Rosc 20 pf 20 pf (a) Crystal or Ceramic Resonator Connections (b) RC Oscillator Connections MASK OPTION The SPC500A1 has the following mask option: Supports Crystal Resonator or Rosc (with mask option). ROM AREA The SPC500A1 provides a 512K-byte ROM that can be defined as the program area, audio data area, or both. To access ROM, users should program the BANK SELECT Register, choose bank, and access address to fetch data. RAM AREA The SPC500A1 total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF. VOLUME CONTROL FUNCTION The SPC500A1 contains a volume control function that provides an 8-step volume controller to control current D/A output. A volume control function selector (Enable/Disable) register and controller register is provided. Sunplus Technology Co., Ltd. 2 Rev.: 1.0 1999.11.04 SPC500A1 MAP OF MEMORY AND I/Os *I/O PORT: *MEMORY MAP (From ROM view) - PORT IOA $0004 IOB $0005 $00000 HW register, I/Os $00080 USER RAM and STACK - I/O CONFIG $0000 $00100 $0001 UNUSED $00200 *NMI SOURCE: - INTA (from TIMER A) SUNPLUS TEST PROGRAM $00600 USER’S PROGRAM & DATA AREA ROM BANK #0 *INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) $08000 ROM BANK #1 $10000 ROM BANK #2 - CPU CLK / 1024 - CPU CLK / 8192 $18000 - CPU CLK / 65536 - EXT INT ROM BANK #15($0F) $7FFFF Sunplus Technology Co., Ltd. 3 Rev.: 1.0 1999.11.04 SPC500A1 I/O PORT CONFIGURATIONS* Input/Output IOA port : IOA3 - IOA0 Input/Output IOB port : IOB3 -IOB0 V DD logic_1 input data control 100K output output data data buffer or OD-NMOS control OD : Open Drain OD : Open Drain Input/Output IOC port : IOC3 - IOC0 Input/Output IOC port : IOC6 - IOC4 V DD logic_3 control V DD logic_4 control 100K output 100K output data buffer or OD-NMOS input data buffer or OD-NMOS input data OD : Open Drain OD : Open Drain Input/Output IOD port : IOD3 - IOD0 Input/Output IOD port : IOD7 - IOD4 input data output 70K logic_2 input data data OD-NMOS or buffer input data OD-PMOS or buffer output data logic_5 OD-PMOS or buffer data 70K logic_6 control control OD : Open Drain OD : Open Drain 70K *Values shown are for VDD = 5.0V test conditions only. Sunplus Technology Co., Ltd. 4 Rev.: 1.0 1999.11.04 SPC500A1 POWER SAVINGS MODE The SPC500A1 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. RAM and I/Os will remain in their previous states until being awakened. In such a mode, Port IOD7-0 is the only wake-up source in the SPC500A1. After the SPC500A1 is awakened, the internal CPU will go to the RESET State (Tw 65536 x T1) and then continue processing the program. Wakeup Reset will not affect RAM or I/Os (See FIG.1). Sleep Wake-up T1 CPU CLK Tw Reset FIG. 1 T1 = 1 / ( FCPU ), Tw 65536 x T1 LOW VOLTAGE RESET The SPC500A1 provides a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (See FIG.2). T1 CPU CLK VDD 2.2V T2 TW RESET T2 2 * T1 (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2 Sunplus Technology Co., Ltd. 5 Rev.: 1.0 1999.11.04 SPC500A1 TIMER/COUNTER The SPC500A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded upcounters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user’s pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. Clock source of Timer/Counter can be selected as follows: Timer/Counter TMA TMB Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 12-BIT COUNTER T/64, T/8192, T/65536 or EXT CLK 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 SPEECH AND MELODY Since the SPC500A1 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. frequency. For speech synthesis, the SPC500A1 can provide NMI for accurate sampling Users can record or synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of the control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the SPC500A1 provides the dual tone mode. After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output. SERIAL INTERFACE I/O The SPC500A1 provides serial interface I/O mode for those applications requiring large ROM/RAM. Serial Interface I/O Port can be used to read/write data from/to extra memory. The interface I/O Register is the control register for programming interface I/O. MULTI-DUTY CYCLE MODE The SPC500A1 provides three output waveforms, 1/2, 1/3, and 1/4 duty cycles. The Control Register should be used to select 1/2, 1/3 or 1/4 duty cycle and the IOA2 should be programmed as the multi-duty cycle output port. Users can use the combinations of these duty cycles for remote-control purposes. Sunplus Technology Co., Ltd. 6 Rev.: 1.0 1999.11.04 SPC500A1 1/2, 1/3, 1/4 duty cycle outputs Clock 1/2 duty cycle 1/3 duty cycle 1/4 duty cycle Sunplus Technology Co., Ltd. 7 Rev.: 1.0 1999.11.04 SPC500A1 PIN DESCRIPTIONS* Mnemonic PIN No. Type Description VDD 11,15 I Positive supply for logic and I/O pins VSS 1,10 I Ground reference for logic and I/O pins XI 13 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) XO 12 O Oscillator crystal output TEST 17 I TEST MODE RESET 2 I This pin is an active low reset to the chip AUD1 14 O AUDIO OUTPUT AUD2 16 Port A is an 4-bit bi-directional programmable Input / Output port with Pull- IOA0 30 I/O high or Open-drain option. As inputs, Port A can be in either the Pure or IOA1 31 I/O Pull-high states. IOA2 32 I/O NMOS types (Sink current). IOA3 33 I/O IOA0: Serial programming clock output As outputs, Port A can be either Buffer or Open-drain IOA2: Multi-duty cycle output **See note 1 and 2 below. Port B is an 4-bit bi-directional programmable Input / Output port with PullIOB0 26 I/O low or Open-drain option. As inputs, Port B can be in either the Pure or IOB1 27 I/O Pull-low states. As outputs, Port B can be either Buffer or Open-drain IOB2 28 I/O NMOS types (Sink current). IOB3 29 I/O **See note 1 and 2 below. Port C is an 7-bit bi-directional Input / Output port with Pull-high or Open- IOC0 3 I/O drain option. IOC1 4 I/O states. As outputs Port C can be a Buffer type or Open-drain NMOS type IOC2 5 I/O (sink current). IOC3 6 I/O IOC0: Serial programming Data IOC4 7 I/O IOC1: Can also be selected as an external interrupt PIN IOC5 8 I/O IOC2: EXT COUNT IN IOC6 9 I/O **See note 1 and 2 below. Sunplus Technology Co., Ltd. As inputs, Port C can be in either the Pure or Pull-high 8 Rev.: 1.0 1999.11.04 SPC500A1 Mnemonic PIN No. Type Description Port D is an 8-bit bi-directional programmable Input / Output port with Pull- IOD0 18 I/O low or Open-drain option. As inputs, Port D can be either Pure or Pull-low IOD1 19 I/O states. As outputs, Port D can be either Buffer or Open-drain PMOS type IOD2 20 I/O (send current). IOD3 21 I/O (Port D can be software programmed for wake up I/O PIN) IOD4 22 I/O (Programmable I/O, Key change, Wake up I/O) IOD5 23 I/O IOD6 24 I/O IOD7 25 I/O **See note 1 and 2 below. * Refer to SPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified, Buffer output, Open Drain PMOS output <send>, Open Drain NMOS output <sink>. ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Ratings DC Supply Voltage V+ < 7V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0 to +60 TSTO -50 to +150 Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. AC CHARACTERISTICS ( TA = 25 ) Limit Characteristics CPU Clock Symbol FCPU Sunplus Technology Co., Ltd. Unit Test Condition Min. Typ. Max. - 3.58 5.0 MHz VDD = 3V - 4.0 8.0 MHz VDD = 5V 9 Rev.: 1.0 1999.11.04 SPC500A1 DC CHARACTERISTICS ( TA = 25 , VDD = 3V ) Limit Characteristics Symbol Unit Min. Typ. Max. Test Condition Operating Voltage VDD 2.4 - 3.4 V Operating Current IOP - 1.5 2.0 mA FCPU = 3.0MHz @ 3V, no load Standby Current ISTBY - - 2.0 A VDD = 3V Audio output current IAUD - -1.5 - mA VDD = 3V, one-channel Input High Level VIH 2.0 - - V VDD = 3V Input Low Level VIL - - 0.8 V VDD = 3V IOH -1.0 - - mA IOL 2.0 - - mA RIN - 100 - Kohm Output High I IOA,IOB,IOC,IOD Output Sink I IOA,IOB,IOC,IOD Input Resistor IOB,IOD For 2-battery VDD = 3V VOH = 2V VDD = 3V VOL = 0.8V Pull Low VDD = 3V DC CHARACTERISTICS ( TA = 25 , VDD = 5V ) Limit Characteristics Symbol Unit Min. Typ. Max. Test Condition Operating Voltage VDD 3.6 - 5.5 V Operating Current IOP - 4.0 5.0 mA FCPU = 4.0MHz @ 5V, no load Standby Current ISTBY - - 2.0 A VDD = 5V Audio output current IAUD - -3.0 - mA VDD = 5V, one-channel Input High Level VIH 3.0 - - V VDD = 5V Input Low Level VIL - - 0.8 V VDD = 5V IOH -1.0 - - mA IOL 4.0 - - mA RIN - 70 - Kohm Output High I IOA,IOB,IOC,IOD Output Sink I IOA,IOB,IOC,IOD Input Resistor IOB,IOD Sunplus Technology Co., Ltd. 10 For 3-battery VDD = 5V VOH = 4.2V VDD = 5V VOL = 0.8V Pull Low VDD = 5V Rev.: 1.0 1999.11.04 SPC500A1 The relationship between the Rosc and the FCPU VDD = 5.0V , Ta = 25 6.0 5.0 FCPU ( MHz ) VDD = 3.0V , Ta = 25 4.0 3.0 2.0 1.0 0.0 0 200 400 600 800 Rosc ( Kohms ) Frequency vs. VDD Frequency vs. Temperature Frequency normalized to 25 4 Rosc=100Kohms 1.02 FCPU ( MHz ) FCPU/FCPU(25) 1.04 VDD=5.0V 1.00 VDD=3.0V 3 Rosc = 100 Kohms 2 1 Rosc = 360 Kohms 0.98 0 2.0 0.96 0 10 20 30 40 50 Temperature () 60 70 5.0 6.0 3.0 4.0 5.0 VDD ( Volts ) Operating current vs. Frequency vs. VDD 5.0 IOP ( m A ) 4.0 VDD = 5V 3.0 2.0 1.0 VDD = 3V 0.0 0.0 1.0 2.0 3.0 4.0 FCPU ( MHz ) Sunplus Technology Co., Ltd. 11 Rev.: 1.0 1999.11.04 1999.11.04 C3 C4 20p 20p R1 Resistor Speaker XO IOA3 - 0 IOA (I/O) IOC6 - 0 C1 + 0.47F Q1 8050D XI IOA (I/O) IOC6 - 0 AUD1 SPC500A1 AUD1 IOB3 - 0 IOD (I/O) RESET VSS Application Circuit Note (1) 50K C5 RESET IOD (I/O) VSS C2 + 0.47F Q2 8050D C4 0.1 Speaker RESET R2 VDD AUD2 IOD7 - 0 C6 0.1 Speaker VDD VDD IOB(I/O) AUD2 IOD7 - 0 APPLICATION CIRCUIT NOTES SPC500A1 VDD VDD 0.1 C1 + 0.47F Q1 8050D IOC (I/O) IOB3 - 0 R1 XO IOA3 - 0 IOC (I/O) IOB(I/O) Speaker 12 XI VDD Rev.: 1.0 VDD VDD VDD 50K C3 RESET 0.1 SPC500A1 Application circuit (D/A Output) Q2 8050D C2 + 0.47F Sunplus Technology Co., Ltd. SPC500A1 X’TAL/CERAMIC OSC R1 Resistor Speaker 20p 20p Speaker VDD XO XI VDD SCL IOA0 IOA1 IOA2 IOA3 IOC0 CSB SDA VSS C1 + 0.47F Q1 8050D VDD SCL CSB SDA IOB(I/O) IOD (I/O) VSS 50K C5 RESET 0.1 VDD IOB(I/O) IOD (I/O) VSS C4 0.1 Speaker RESET R2 Q2 8050D C2 + 0.47F AUD2 IOD7-0 RESET VDD VDD IOC(I/O) AUD2 IOD7-0 AUD1 IOB3-0 C6 0.1 Speaker Q1 8050D SPC500A1 IOC6-1 VDD R1 IOC0 VDD IOB3-0 C1 + 0.47F IOA3 VSS IOC(I/O) XO IOA0 IOA1 IOA2 AUD1 SPC500A1 IOC6-1 SPRS 256A XI 13 VDD Application Circuit Note (2) Rev.: 1.0 C4 C3 SPRS 256A VDD 1999.11.04 VDD VDD VDD 50K C3 RESET 0.1 SPC500A1 Application circuit with Serial Interface I/O Application Q2 8050D C2 + 0.47F Sunplus Technology Co., Ltd. SPC500A1 X’TAL/CERAMIC OSC C3 C4 20p 20p XI 1999.11.04 R1 Resistor XO XI XO IOA3-0 IOA3-0 IOA (I/O) IOA (I/O) IOC6-0 AUD1 AUD1 IOC (I/O) IOC (I/O) Speaker ~16 SPC500A1 IOB3-0 IOB3-0 VDD IOB(I/O) VDD IOB(I/O) AUD2 AUD2 IOD7-0 IOD7-0 0.1 IOD (I/O) 0.1 IOD (I/O) VSS VSS RESET R1 VDD Speaker ~16 SPC500A1 14 IOC6-0 RESET R2 VDD 50K 50K Application Circuit Note (3) Rev.: 1.0 VDD C5 C3 RESET 0.1 RESET 0.1 SPC500A1 Application circuit (PWM Output) Sunplus Technology Co., Ltd. SPC500A1 X’TAL/CERAMIC OSC C3 C4 20p 20p VDD XO XI VDD IOA0 IOA1 IOA2 IOA3 IOC0 SCL SDA VSS SPRS 256A Speaker ~16 SDA VDD IOB(I/O) 0.1 IOD7-0 IOD (I/O) R1 AUD2 0.1 IOD (I/O) VSS VSS RESET R2 VDD 50K 50K Application Circuit Note (4) VDD IOB(I/O) IOD7-0 RESET VDD Speaker ~16 IOC(I/O) IOB3-0 AUD2 AUD1 SPC500A1 IOC6-1 IOC(I/O) IOB3-0 XO IOA0 IOA1 IOA2 IOA3 IOC0 VSS AUD1 SPC500A1 IOC6-1 VDD SCL CSB 15 XI CSB 1999.11.04 R1 Resistor VDD SPRS 256A Rev.: 1.0 VDD C5 C3 RESET 0.1 RESET 0.1 SPC500A1 Application circuit with Serial Interface I/O Application Sunplus Technology Co., Ltd. SPC500A1 X’TAL/CERAMIC OSC SPC500A1 PAD ASSIGNMENT AND LOCATIONS PAD Assignment Chip Size: 2550m x 3380m This IC substrate should be connected to VSS Note: To ensure that the IC functions properly, bond all VDD, VSS, AVDD and AVSS pins. Ordering Information Product Number Package Type SPC500A1-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z). NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product. Sunplus Technology Co., Ltd. 16 Rev.: 1.0 1999.11.04 SPC500A1 PAD Locations Pad No Pad Name X Y 1 VSS -1116 -1041 2 RESET -1130 -1317 3 IOC6 -1130 -1473 4 IOC5 -1130 -1624 5 IOC4 -1130 -1779 6 IOC3 -814 -1774 7 IOC2 -659 -1774 8 IOC1 -507 -1774 9 IOC0 -352 -1774 10 VSS -201 -1802 11 VDD -51 -1743 12 XO 144 -1802 13 XI 361 -1802 14 AUD1 663 -1781 15 VDD 1090 -1791 16 AUD2 1063 -1457 17 TEST 1121 -1174 18 IOD7 1121 -1023 19 IOD6 1121 -864 20 IOD5 1121 -713 21 IOD4 1121 -555 22 IOD3 1121 -403 23 IOD2 1121 -245 24 IOD1 1121 -93 25 IOD0 1121 65 26 IOB3 1121 217 27 IOB2 1121 375 28 IOB1 1121 527 29 IOB0 1121 685 30 IOA3 1121 836 31 IOA2 1121 992 32 IOA1 1121 1143 33 IOA0 1121 1298 Sunplus Technology Co., Ltd. 17 Rev.: 1.0 1999.11.04 SPC500A1 DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Sunplus Technology Co., Ltd. 18 Rev.: 1.0 1999.11.04