LTC1955 Dual Smart Card Interface with Serial Control DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1955 provides all necessary supervisory and power control functions for two smart cards, two S.A.M. cards or a combination of S.A.M. and smart cards. It provides a charge pump for battery powered applications as well as all necessary level shifting circuitry. Compatible with ISO7816-3 and EMV Electrical Specifications Power Management and Control for Two Smart Cards Control/Status Serial Port May be Daisy-Chained for Multicard Applications Automatic Shutdown on Electrical Faults Buck/Boost Charge Pump Generates 5V, 3V or 1.8V Outputs (Smart Card Classes A, B and C)* Independent 5V/3V/1.8V Level Control for Both Cards Automatic Level Translation Supervisory Functions Prevent Smart Card Faults Low Operating Current: 250µA Typical Ultralow Shutdown Current >10kV ESD on Smart Card Pins Small 32-Pin 5mm × 5mm QFN Package The card voltages can be independently set to 1.8V, 3V or 5V. Both card interfaces include a card detection channel with automatic debounce circuitry. To reduce wiring costs, the LTC1955 interfaces to a microcontroller via a simple 4-wire serial interface. Multiple devices may be connected in daisy-chain fashion so that the number of wires to the card socket board is independent of the number of sockets. Status data is returned over the same interface. Extensive security features ensure proper deactivation sequencing in the event of a supply fault or a smart card electrical fault. The smart card pins can withstand greater than 10kV ESD in-situ with no additional components. The LTC1955 is available in a small 5mm × 5mm QFN package. U APPLICATIO S ■ ■ ■ ■ ■ ■ Handheld Payment Terminals Pay Telephones ATM Machines POS Terminals Computer Keyboards Multiple S.A.M. Sockets , LTC and LT are registered trademarks of Linear Technology Corporation. *U.S. Patent No. 6,411,531 U TYPICAL APPLICATIO 180k 240k 23 1 12,13 Deactivation Sequence INPUT POWER 0.1µF 4.7µF 9, 10 DVCC VBATT LTC1955 C8A GND C4A RST A 5V/DIV 24 27 CLK A 5V/DIV 4-WIRE COMMAND INTERFACE 28 26 25 CARD DETECT UNDERV 2 PRES A I/O A FAULT RST A CLK A DIN VCCA DOUT SCLK PRES B LD 3 4 5 6 7 SMART CARD 8 21 1µF I/O A 5V/DIV 29 VCCA 5V/DIV 10µs/DIV 1955 G11.eps 4-WIRE CARD INTERFACE 30 32 31 22 DATA I/O B RIN RST B SYNC CLK B ASYNC VCCB 20 19 18 C+ 14 C– 11 VENDOR CARD 17 NC/NO 1µF CPO 1955 TA01 15 4.7µF 1µF sn1955 1955fs 1 LTC1955 W W U W ABSOLUTE AXI U RATI GS (Note 1) VBATT, DVCC, CPO, FAULT, UNDERV to GND ....................................... –0.3V to 6.0V PRES A/PRES B, DATA, RIN, SYNC, ASYNC, LD, DIN, SCLK to GND ............... –0.3V to (DVCC + 0.3V) I/O A .......................................... –0.3V to (VCCA + 0.3V) I/O B .......................................... –0.3V to (VCCB + 0.3V) IVCCA/IVCCB ........................................................................... 80mA VCCA/VCCB Short-Circuit Duration .................... Indefinite Operating Ambient Temperature Range (Note 4) .............................................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125°C DVCC 1 PRES A 2 ORDER PART NUMBER LD SCLK DIN DOUT DATA RIN ASYNC SYNC U W U PACKAGE/ORDER I FOR ATIO 32 31 30 29 28 27 26 25 PIN 1 24 FAULT TOP VIEW 23 UNDERV C8A 3 22 NC/NO C4A 4 21 PRES B LTC1955EUH I/O A 5 20 I/O B RST A 6 19 RST B CLK A 7 18 CLK B UH PART MARKING VCCA 8 17 VCCB 1955 NC CPO C+ PVBATT SVBATT C– PGND SGND 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD PLASTIC QFN TJMAX = 150°C, θJA = 34°C/W EXPOSED PAD IS SGND Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 5.5 V 250 350 400 500 µA µA 0.75 1.75 µA 5.5 V Input Power Supply VBATT Operating Voltage ● IPVBATT + ISVBATT Operating Current VCCA = 5V, VCCB = 0V, ICCA = 0µA VCCA = VCCB = 5V, ICCA = ICCB = 0µA ● ● IPVBATT + ISVBATT Shutdown Current No Cards Present, VCPO = 0V ● 2.7 DVCC Operating Voltage ● 1.7 IDVCC Operating Current ● 10 25 µA IDVCC Shutdown Current ● 0.5 1.5 µA ROLCP 5V Mode Open-Loop Output Resistance VBATT = 3.075V, ICPO = ICCA + ICCB = 120mA, (Note 3) ● 5.7 8.5 Ω CPO Turn On Time ICCA/B = 0mA, 10% to 90% 0.6 1.5 ms Charge Pump ● sn1955 1955fs 2 LTC1955 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted. SYMBOL CONDITIONS MIN TYP MAX UNITS 4.65 2.75 1.65 5.0 3.0 1.8 5.35 3.25 1.95 V V V Smart Card Supplies VCCA, VCCB VCCA/B Output Voltage 5V Mode, 0 < ICCA/B < 60mA 3V Mode, 0 < ICCA/B < 50mA 1.8V Mode, 0 < ICCA/B < 30mA ● ● ● VCCA/B Turn On-Time ICCA/B = 0mA, 10% to 90% ● 0.8 1.5 ms Undervoltage Detection Relative to Nominal Output ● –9 –5 – 2.5 % Overcurrent Detection 5V Mode ● 65 100 135 mA ● 20 35 60 ms ● 1.25 2.5 µA ICCA/B = 0mA, CVCCA/B = 1µF ● 20 250 µs Low Level Output Voltage (VOL), (Note 2) Sink Current = – 200µA ● 0.2 V High Level Output Voltage (VOH), (Note 2) Source Current = 200µA ● Rise/Fall Time, (Note 2) Loaded with 50pF, 10% to 90% ● 16 ns Smart Card Detection Debounce Time ( PRES A/B to PRES A, PRES B Pull-Up Current Deactivation Time ( D15/D7) VNC/NO = 0V VPRESA/B = 0 RST to VCC = 0.4V) CLK A, CLK B CLK A, CLK B Frequency, (Note 2) ● VCCA/B – 0.2 V 10 MHz RST A, RST B, C4A, C8A Low Level Output Voltage (VOL), (Note 2) Sink Current = – 200µA ● 0.2 V High Level Output Voltage (VOH), (Note 2) Source Current = 200µA ● Rise/Fall Time, (Note 2) Loaded with 50pF, 10% to 90% ● 100 ns Low Level Output Voltage (VOL), (Note 2) Sink Current = –1mA (VDATA = 0V) ● 0.3 V High Level Output Voltage (VOH), (Note 2) Source Current = 20µA (VDATA = VDVCC) ● 0.85 • VCCA/B Rise/Fall Time, (Note 2) Loaded with 50pF, 10% to 90% ● Short Circuit Current, (Note 2) VDATA = 0V ● Sink Current = – 500µA (VI/OA/B = 0V) ● High Level Output Voltage (VOH) Source Current = 20µA (VI/OA/B = VCCA/B) ● Rise/Fall Time Loaded with 50pF, 10% to 90% ● VCCA/B – 0.2 V I/O A, I/O B V 5 500 ns 10 mA 0.3 V 500 ns 0.15 • DVCC V DATA Low Level Output Voltage (VOL) 0.8 • DVCC V RIN, DIN, SCLK, LD, SYNC, ASYNC, NC/NO Low Input Threshold (VIL) ● High Input Threshold (VIH) ● 0.85 • DVCC Input Current (IIH/IIL) ● –1 V 1 µA 0.3 V DOUT Low Level Output Voltage (VOL) Sink Current = – 200µA ● High Level Output Voltage (VOH) Source Current = 200µA ● DVCC – 0.3 ● 1.17 V UNDERV Threshold Leakage Current VUNDERV = 3.3V ● 1.23 1.29 V 50 nA sn1955 1955fs 3 LTC1955 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 0.005 0.3 V 1 µA FAULT Low Level Output Voltage (VOL) Sink Current = – 200µA ● Leakage Current VFAULT = 5.5V ● SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Serial Port Timing tDS DIN Valid to SCLK Setup ● 8 ns tDH DIN Valid to SCLK Hold ● 8 ns tDD DOUT Output Delay ● 15 tL SCLK Low Time CLOAD = 15pF ● 50 ns tH SCLK High Time ● 50 ns tLW LD Pulse Width ● 50 ns tCL SCLK to LD ● 50 ns tLC LD to SCLK ● 0 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This specification applies to all three smart card voltage classes: 1.8V, 3V and 5V. Note 3: ROLCP ≡ (2VBATT – VCPO)/ICPO; VCPO will depend upon total load (ICCA + ICCB) and minimum supply voltage VBATT. See Figure 6. 60 ns Note 4: The LTC1955E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. U W TYPICAL PERFOR A CE CHARACTERISTICS No Load Supply Current vs VBATT 600 6.0 VCCA = VCCB = 5V 400 VCCA = 1.8V, VCCB = 0V 300 200 100 0 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) 5.1 5.5 1955 G01 5.5 7.0 DVCC = VBATT = 5.5V VCCX = 5V OUTPUT RESISTANCE (Ω) SHORT-CIRCUIT CURRENT (mA) TA = 25°C ICCA = ICCB = 0µA 500 SUPPLY CURRENT (µA) Charge Pump Open-Loop Output Resistance vs Temperature (2VIN – VCPO) / ILOAD(MAX) I/O X Short-Circuit Current vs Temperature 5.0 4.5 4.0 3.5 –40 –15 10 35 TEMPERATURE (°C) 60 85 1955 G02 6.5 VIN = 2.7V VCPO = 4.9V 6.0 5.5 5.0 4.5 –40 –15 10 35 TEMPERATURE (°C) 60 85 1955 G03 sn1955 1955fs 4 LTC1955 U W TYPICAL PERFOR A CE CHARACTERISTICS VCCX Overcurrent Shutdown Threshold vs Temperature Card Detection Debounce Time vs VBATT Supply Voltage 180 VCCX = 1.8V 140 VCCX = 3V 120 I/O A, I/O B LOW OUTPUT VOLTAGE (V) 55 DEBOUNCE TIME (ms) LOAD CURRENT (mA) 0.16 60 VBATT = 3.3V VCPO = 5.75V 160 TA = 85°C 50 TA = 25°C 45 40 TA = –40°C 35 100 30 VCCX = 5V –15 10 35 TEMPERATURE (°C) 60 25 2.7 85 3.1 3.5 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 1955 G04 9 0.14 VCCX = 3V 0.12 VCCX = 5V 0.10 0.08 SUPPLY CURRENT (µA) 8 3 2 85 VDVCC = VBATT 2.5 4 60 1.0 VDVCC = VBATT 5 10 35 TEMPERATURE (°C) DVCC Shutdown Current vs Supply Voltage 3.0 VBATT = 3.1V TA = 25°C 6 –15 1955 G06 VBATT Shutdown Current vs Supply Voltage 7 VCCX = 1.8V 1955 G05 VBATT Quiescent Current [IBATT – 2 (ICCA + ICCB)] vs Load Current 10 VDATA = 0V IOL = –1mA VBATT = 2.7V 0.06 –40 5.5 0.8 SUPPLY CURRENT (µA) 80 –40 VBATT QUIESCENT CURRENT (mA) Bidirectional Channel (I/O A, I/O B) Low Output Level vs Temperature TA = –40°C 2.0 TA = 25°C 1.5 1.0 TA = 85°C TA = –40°C 0.6 0.4 TA = 25°C, 85°C 0.2 0.5 1 0 10µ 100µ 1m 10m LOAD CURRENT (A) 100m 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 1955 G07 5.5 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VDVCC SUPPLY VOLTAGE (V) 1955 G09 1955 G08 Charge Pump and LDO Activation 5.5 Deactivation Sequence Data – I/O Channel, CL = 50pF RST A 5V/DIV VCPO 5V/DIV I/O A 2V/DIV CLK A 5V/DIV VCCA 5V/DIV I/O A 5V/DIV I/O A 5V/DIV DATA 2V/DIV VCCA 5V/DIV 1ms/DIV 1955 G10 10µs/DIV 1955 G11.eps 100ns/DIV 1955 G12 sn1955 1955fs 5 LTC1955 U U U PI FU CTIO S SVBATT: Power. Supply voltage for analog sections of the LTC1955. PVBATT: Power. Supply voltage for the charge pump. DVCC: Power. Reference voltage for the control logic. SGND: Ground. Signal ground for analog sections of the LTC1955. PGND: Ground. Power ground for the charge pump. This pin should be connected directly to a low impedance ground plane. CPO: Charge Pump. CPO is the output of the charge pump. When one or both of the smart cards requires power, the charge pump will charge CPO to either 3.7V or 5.35V depending on what smart card voltages are required. A low impedance 4.7µF X5R or X7R ceramic capacitor is required on CPO. C +, C –: Charge Pump. Charge pump flying capacitor pins. A 1µF X5R or X7R ceramic capacitor should be connected from C + to C –. DATA: Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to both smart cards. One, both or neither of the cards may be selected to communicate via the DATA pin. If several LTC1955s are connected in parallel, the DATA pin can be made high impedance by selecting neither card. The C4A and C8A synchronous card pins can be selected to connect to the DATA pin via the serial port (see Table 4). RIN: Input. The RIN pin supplies the RST signal to both smart cards. It is level shifted and transmitted directly to the RST pin of a selected card socket. When a card is deselected, the RST A/RST B pin for that channel is latched at its current state. SYNC: Input. The SYNC pin provides the clock input for synchronous smart cards. When a synchronous card is selected, its CLK pin follows SYNC directly. When a synchronous card is deselected, the CLK A/CLK B pin for that channel is latched at its current state. ASYNC: Input. The ASYNC pin provides the clock input for asynchronous cards and should be connected to a free running clock. The clock signal to the smart card can be a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC. Asynchronous cards can also be placed in clock stop mode with the clock stopped either high or low. DIN: Input. Input for the serial port. Command data is shifted into DIN synchronously with SCLK. DIN can be connected directly to a microcontroller or the DOUT pin of another LTC1955 for daisy chained operation. DOUT: Output. Output for the serial port. Smart card status data is shifted out of DOUT synchronously with SCLK. DOUT can be connected directly to a microcontroller or the DIN pin of another LTC1955 for daisy chained operation. SCLK: Input. The SCLK pin clocks the serial port. Each new data bit is received on the rising edge of SCLK. SCLK should be left high during idle times and should not be clocked when LD is low. LD: Input. The falling edge of this pin loads the current state of the shift register into the command register. Command changes to both smart card channels will be updated on the falling edge of LD. The rising edge of LD latches status information from the smart card channels into the shift register for the next read/write cycle. NC/NO: Input. This pin controls the activation level of the PRES A/PRES B pins. When it is high (DVCC), the PRES pins are active high. When it is low (GND), the PRES pins are active low. When a ground side N.O. switch is used, the NC/NO pin should be grounded. When a ground side N.C. switch is used, the NC/NO pin should be connected to DVCC. Note: If an N.C. switch is used, a small current (several microamperes) will flow through the switch whenever a smart card is not present. For ultralow power consumption in shutdown, an N.O. switch is optimum. sn1955 1955fs 6 LTC1955 U U U PI FU CTIO S PRES A/PRES B: Card Socket. The PRES A/PRES B pins are used to detect the presence of the smart cards. They can be connected to either normally open or normally closed detection switches on the smart card acceptor’s sockets. The NC/NO pin should be set appropriately. These pins have a pull-up current source on-chip so no external components are required. C4A/C8A: Card Socket. These pins connect to the C4 and C8 pins of synchronous memory cards on smart card socket A. The signal for these pins is unidirectional and can only be sent to the card. Data for C4A and C8A is transmitted via the DATA pin and may be selected in place of I/OA via the serial port (see Table 4). When either C4A or C8A is selected, it will follow the DATA pin. When it is deselected, it will remain latched at its current state. I/O A/I/O B: Card Socket. The I/O A/I/O B pins connect to the I/O pins of the respective smart card sockets. When a smart card is selected, its I/O pin connects to the DATA pin. When a smart card is deselected, its I/O A/I/O B pin returns to the idle state (H). RST A/RST B: Card Socket. These pins should be connected to the RST pins of the respective smart card sockets. The RST A/RST B signals are derived from the RIN pin. When a card is selected, its RST pin follows RIN. When a card is deselected, the RST A/RST B pin for that channel holds the current value on RIN. CLK A/CLK B: Card Socket. The CLK A/CLK B pins should be connected to the CLK pins of the respective smart card sockets. The CLK A/CLK B signals can be derived from either the SYNC input or the ASYNC input depending on which type of card is being accessed. The card type is selected via the serial port (see Tables 1 and 3). VCCA, VCCB: Card Socket. The VCCA/VCCB pins should be connected to the VCC pins of the respective smart card sockets. The activation of a VCCA/VCCB pin is controlled by the serial port (see Tables 1 and 2) and can be set to 0V, 1.8V, 3V or 5V. The voltage levels of the two card sockets are controlled independently for maximum flexibility. FAULT: Output. The FAULT pin can be used as an interrupt to a microcontroller to indicate when a fault has occurred. It is an open drain output, which is logically equivalent to D4 + D5 + D12 + D13. (See Table 1) UNDERV: Input. The UNDERV pin provides security by supplying a precision undervoltage threshold for external supply monitoring. An external resistive voltage divider programs the desired undervoltage threshold. Once UNDERV falls below 1.23V, the LTC1955 automatically begins the deactivation sequence on any channel that is active. If external supply monitoring is not required, the UNDERV pin should be connected to either SVBATT or DVCC. sn1955 1955fs 7 LTC1955 W BLOCK DIAGRA CHARGE PUMP C+ C– PGND 14 11 10 SVBATT PVBATT 12 13 CPO 15 CHARGE PUMP VCCB 17 LDO B 8 VCCA LDO A I/O B 20 SMART CARD SOCKET B 5 I/O A CLOCK CONTROL LOGIC CLK B 18 RST B 19 PRES B 21 τ 4 C4A SMART CARD SOCKET A 3 C8A RESET CONTROL LOGIC 7 CLK A 6 RST A DATA 29 SMART CARD COMMUNICATIONS ASYNC 31 τ 2 PRES A SYNC 32 22 NC/NO RIN 30 24 FAULT STATUS DATA 9 SGND DIN 27 SERIAL PORT COMMAND/STATUS DATA DOUT 28 DIGITAL SUPPLY 1 DVCC SHIFT REGISTER SCLK 26 LD 25 – 23 UNDERV COMMAND LATCH + 1.23V + – 1955 BD sn1955 1955fs 8 LTC1955 U OPERATIO Serial Port The microcontroller compatible serial port provides all of the command and control inputs for the LTC1955 as well as the status of the two smart cards. Data on the DIN input is loaded on the rising edge of SCLK. D15 is loaded first and D0 last. At the same time the command bits are being shifted into the DIN input, the status bits are being shifted out of the DOUT output. The status bits are presented to DOUT on the rising edge of SCLK. Once all bits have been clocked into the shift register, the command data is loaded into the command latch by bringing LD low. At this time the command latch is updated and the LTC1955 will begin to act on the new command set. When LD is low, the shift register is transparent to the status data of the two smart card channels. The status data is latched into the shift register on the rising edge of LD. SCLK should be held in the high state when idle and should only be clocked when LD is high. Likewise LD should only be brought high when SCLK is high. Figure 2 shows the operation of the serial port. Multiple LTC1955s may be daisy-chained together by connecting the DOUT pin of one LTC1955 to the DIN pin of another. Figure 7 shows an example of multiple LTC1955s daisy chained together. The maximum clock rate for the serial port is 10MHz. The serial port controls the following parameters of each smart card socket: • Selection/deselection of a smart card • VCC voltage level of each card (5V/3V/1.8V/0V) • Operating mode of asynchronous cards (clock stop high, low, ÷1, ÷2, ÷4 or ÷8) • Selection of the I/O, C4 or C8 pins for card socket A The serial port provides the following status data: • It indicates the presence or absence of the smart cards. • It indicates the readiness of the smart card VCC supplies. Communication with a smart card is disabled until its power supply voltage has reached the final value. • It indicates fault status. In the event of an electrical or ATR fault, the fault is reported. For electrical faults, the LTC1955 will automatically deactivate the smart card. Table 1 illustrates the command inputs and status outputs associated with each bit of the serial data word. Three voltage options are available from the LTC1955: 5V, 3V and 1.8V. Bits D0, D1 (card B) and D8, D9 (card A) determine which voltage is selected. Setting both control bits of a channel to 0 deactivates that channel and sets the smart card supply voltage to 0V. If both channels are deactivated, the LTC1955 is in shutdown. Table 2 shows the operation of the supply control bits. The CLK A/CLK B pins to the smart cards can be programmed for various modes. Both synchronous and asynchronous cards are supported. There are several options available with asynchronous cards. Table 3 shows how all clock options are obtained using bits D5–D7 (card B) and D13–D15 (card A). The default state of the LTC1955 on power up is synchronous mode. • Clock mode of each card (synchronous or asynchronous) tLC tDS tDH tH tDD tL tCL tLW SCLK DIN X D15 D14 D2 D1 D0 X LD DOUT D15 D14 D13 D1 D0 D15 FROM INPUT D15 1955 F02 Figure 2. Serial Port Timing Diagram sn1955 1955fs 9 LTC1955 U OPERATIO Table 1. Serial Port Commands CARD B CARD A STATUS OUTPUT BIT COMMAND INPUT 0 D0 VCCB Options 0 D1 (See Table 2) 0 D2 Card B Select/Deselect 0 D3 Data Pull-Up Defeat Card B Electrical Fault D4 Reserved (Always Set to “0”) Card B ATR Fault D5 Card B Clock Options Card B VCC Ready D6 (See Table 3) Card B Present D7 0 D8 VCCA Options 0 D9 (See Table 2) 0 D10 Card A Select/Deselect 0 D11 Card A Communications Card A Electrical Fault D12 Options (See Table 4) Card A ATR Fault D13 Card A Clock Options Card A VCC Ready D14 (See Table 3) Card A Present D15 Table 2. VCC and Shutdown Options D9 D1 D8 D0 Status (Card A) Status (Card B) 0 0 VCC = 0V (Shutdown) 0 1 VCC = 1.8V 1 0 VCC = 3V 1 1 VCC = 5V Table 3. Clock Options D7 D15 D6 D14 D5 D13 Clock Mode Card B Clock Mode Card A 0 0 0 Synchronous Mode 0 0 1 Unused 0 1 0 Asynchronous Stop Low 0 1 1 Asynchronous Stop High 1 0 0 Asynchronous ÷1 1 0 1 Asynchronous ÷2 1 1 0 Asynchronous ÷4 1 1 1 Asynchronous ÷8 To receive status data from the serial port, a read/write operation must be performed. When polling for the presence of a smart card on both channels, the input word should be set to $0000 since this is the shutdown command for the LTC1955. However, consider the example where some operation is already being performed on channel A. If, for example, the previous command was $BE00 (VCCA set to 3V, card selected, I/O A connected to DATA and CLK A set to ASYNC÷2), then the commands for this channel must be rewritten to the serial port each time. To poll for the presence of a card on channel B, or even the VCCA READY status, then $BE00 should be rewritten on each new read/write cycle. Once a card is detected on channel B, the commands for channel B can be changed but the $BExx should continue to be rewritten for channel A. Bidirectional Channels The bidirectional channels are level shifted to the appropriate VCCA/B voltages at the I/O A/I/O B pins. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts an L, then the transistor will convey the L to the other side. Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the I • R drop of the pass transistor. When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, the voltage on its I/O A/I/O B pin will return to the idle state (H) and the DATA side of that channel will become high impedance. If both cards are deselected, the DATA pin will be high impedance. Both cards may be deselected at the same time to allow communication with a second LTC1955. Card channel A includes provision for unidirectional communication with the C4 and C8 pins of the smart card. The C4, C8 and I/O pins of card A are individually multiplexed to the DATA pin using bits D11 and D12 as shown in Table␣ 4. sn1955 1955fs 10 LTC1955 U OPERATIO Table 4. Card A Communications Options D12 D11 Card A Communication Mode 0 0 Nothing Selected 0 1 C4A Connected to DATA Pin 1 0 C8A Connected to DATA Pin 1 1 I/O A Connected to DATA Pin Note that if a reset is initiated with both cards selected, then both may give an answer to reset and collide on the DATA line. No damage will occur but data could be lost or corrupted. Dynamic Pull-Up Current Sources The current sources on the bidirectional pins (DATA, I/O A/ I/O B) are dynamically activated to achieve a fast rise time with a relatively small static current*. Once a bidirectional pin is relinquished, a small start up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. LOCAL SUPPLY + ISTART BIDIRECTIONAL PIN VREF – dv dt 1955 F03 Figure 3. Dynamic Pull-Up Current Sources Clock Channels As described in the section Serial Port, the LTC1955 supports both synchronous and asynchronous smart cards. On start-up, or when bits D13-D15 for card A and bits D5-D7 for card B are set to 0s, the clock channel is in synchronous mode. The remaining modes are used for asynchronous cards. In synchronous mode the CLK A/CLK B pins follow the SYNC pin for a channel that is selected. If a channel is deselected (via the serial port) the CLK A/CLK B line for that channel is latched at its current value. In asynchronous mode the CLK A/CLK B pins follow either the ASYNC pin (÷1 mode) or a divided version of this pin. The CLK A/CLK B pins can also be stopped high or low. The available divider ratios include ÷2, ÷4 and ÷8. When switching between divider ratios, the internal selection circuitry ensures that no spikes or glitches appear on the CLK A/CLK B pins. Consequently, it may take up to 8 clock pulses for the clock frequency change command to take affect. Synchronization circuitry ensures that no glitches occur when entering or exiting one of the stop modes. For example, when entering stop low mode, the selection circuitry waits for the next falling edge of the respective CLK A/CLK B signal to make the change. Likewise if stop high is selected it will occur on the next rising edge. Deselection of an asynchronous card does not affect its CLK A/CLK B pin. Its clock can be started, stopped or its divider ratio changed at any time. To clean up the duty cycle of the incoming clock in asynchronous applications, any of the clock divider modes ÷2, ÷4 or ÷8 will yield a very nearly 50% duty cycle. Additional synchronization circuitry prevents glitches from occurring when switching between synchronous mode and asynchronous mode. Because of this circuitry, two edges (a falling edge followed by a rising edge) are necessary at the CLK pin to switch modes from asynchronous to synchronous. For example, if clock stop mode is engaged, the clock channel will not change modes until clock stop mode is disengaged. Any combination of cards, synchronous or asynchronous, can be used as both channels can be set to any of the clock modes or divider ratios independently. Both SYNC and ASYNC inputs are independently level shifted to the appropriate voltage for the CLK A/CLK B pins (5V, 3V, 1.8V). Reset Channels When a card is selected, the reset channels provide a level shifted path from the RIN pin to the RST A/RST B pins. When a card is deselected its RST A/RST B pin is latched at the current value of RIN. *U.S. Patent No. 6,356,140 sn1955 1955fs 11 LTC1955 U OPERATIO Smart Card Detection Circuits The PRES A/PRES B pins are used to detect the presence of a smart card. An automatic debounce circuit waits until a smart card has been present for a continuous period of typically 35ms. Once a valid card indication exists, the status bit for that channel is updated and may be polled by cycling data through the serial port. The DOUT pin (equivalent to D15) of the serial port can be used to indicate the presence of a card on channel A in real time if LD is held low. The PRES A/PRES B pins have built-in pull-up current sources so no external components are required for switch detection. The pull-up current sources are designed to have a small current when the pin voltage is below approximately 1V but somewhat higher current when the pin voltage reaches 1V. This helps maintain low power dissipation when a card is present and yet fast response time to a card removal. The PRES A/PRES B pins can be configured to respond to either normally open or normally closed switches via the NC/NO pin. Activation/Deactivation For maximum flexibility, the activation sequencing of the smart card is left to the application programmer. Upon activation, to comply with relevant smart card standards, none of the smart card signal pins will be allowed to go high before the smart card supply voltage (VCCA/VCCB) has reached its final value. Deactivation can be achieved either manually or automatically. An electrical fault condition will trigger the automatic deactivation. Manual deactivation may be performed under software control by setting the smart card pins to 0V in the desired sequence via the control pins (SYNC, ASYNC, RIN, DATA and the serial port). For most applications this will be cumbersome and the built-in deactivation will be used instead. Automatic Deactivation The built-in deactivation sequence can be executed via the serial port simply by setting the appropriate control bits (D0 and D1 or D8 and D9) to 0. The deactivation sequence is outlined below. 1. The RST A/RST B pin for that channel is immediately brought low. 2. The deactivation of the CLK A/CLK B pins depends upon which type of card is used: If the smart card was set to asynchronous mode then the CLK A/CLK B pin will be latched low on its next falling edge. If no falling edges occur within 5µs (min) then the CLK A/CLK B line is forced low. If the smart card was set to synchronous mode then the CLK A/CLK B pin is immediately latched at its current value (either high or low) and then forced low after a duration of 5µs (min). During the 5µs timeout period changes on SYNC will be ignored. 3. The I/O A/I/O B, C4A and C8A pins for that channel are brought low. 4. The VCCA/VCCB pin is brought low. If an error occurs on one smart card, operation of the other card is unaffected. sn1955 1955fs 12 LTC1955 U OPERATIO Electrical Fault Detection Several types of faults are detected by the LTC1955. They include VCCA/VCCB undervoltage, VCCA/VCCB overcurrent, CLK A/CLK B, RST A/RST B, C8A, C4A short circuit, card removal during a transaction, failed answer to reset (ATR), supply undervoltage or UNDERV and chip overtemperature. To prevent false errors from plaguing the microcontroller, the electrical faults are acted upon only after a 5µs (min) timeout period. Card removal during transaction faults initiate the deactivation sequence immediately. VCCA/VCCB under voltage faults are determined by comparing the actual output voltage with the internal reference voltage. If the output is more than ~5% below its set point for the entire timeout period, the fault is reported and the deactivation sequence is initiated. VCCA/VCCB overcurrent faults are detected by comparing the output current of the LDOs with an internal reference level. If the current of an LDO is more than 100mA (typ) for the entire timeout period, the fault is reported and the deactivation sequence is initiated. CLK A/CLK B and RST A/RST B faults are detected by comparing the outputs of these pins with their expected signals. If the signal on a pin is incorrect for the entire timeout period, the fault is reported and the deactivation sequence is initiated. The clock channels are a special case. Since they can have a free running clock, the error indication is accumulated over a longer period of time without being cleared. Even though the clock may be running, an error will still be detected. An overtemperature fault is detected by sensing the junction temperature of the IC. If the junction temperature exceeds approximately 150°C for the entire timeout period, the fault is reported by setting both fault bits (D4 and D12) and the deactivation sequence is initiated. A card removal fault is determined as soon as the PRES A/ PRES B pin is high (for NC/NO = 0). Once this occurs the fault is reported and the deactivation sequence is initiated. Short circuits on the I/O A/I/O B lines will not be detected by the fault detection hardware; however, a short circuit from these lines to their respective VCCA/VCCB pins will be compliant with the maximum current limits set by applicable standards (<15mA). Answer to Reset (ATR) Fault Detection Answer to Reset faults are detected by an internal counter that is started once the RST A/B line goes high. If the DATA pin remains high for 40,000 clock cycles, the ATR fault bit for a given channel is set in the serial port’s status register (see Table 1) and the FAULT pin is brought low. An ATR fault can not occur if the clock mode of a channel is set to synchronous. ATR faults will only occur for asynchronous smart cards. ATR faults are cleared by bringing the RST A/B pin low for the faulted channel. This will also clear the FAULT pin to the Hi-Z state (assuming no other errors are causing FAULT to be low). An ATR fault will not automatically deactivate a card channel. It is the application programmer’s responsibility to check the status register for ATR faults and deactivate the smart card channel in accordance with smart card standards. Generally the application has 50ms (EMV 2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to deactivate the card. Once the LTC1955 receives the deactivation command, it will shut down a card channel in less than 250µs. Using the FAULT Pin The FAULT pin can be used as an interrupt to a microcontroller. It is an open-drain output and generally requires a pull-up resistor. The FAULT pin will go low when either an electrical fault or an answer to reset fault occurs on either channel. Thus there are four possible faults that can cause it to indicate a problem. The serial port’s status register must be polled to find out what type of fault occured and on which channel. The FAULT pin is logically equivalent to D4+D5+D12+D13 (see Table 1). If no card is present, and the application software attempts to power up a card socket, an automatic fault will result on that channel. sn1955 1955fs 13 LTC1955 U W U U APPLICATIO S I FOR ATIO 10kV ESD Protection All smart card pins (CLK A/CLK B, RST A/RST B, I/O A/ I/O␣ B, C4A, C8A and VCCA/VCCB) can withstand over 10kV of human body model ESD in-situ. In order to ensure proper ESD protection, careful board layout is required. The PGND and SGND pins should be tied directly to a ground plane. The VCCA/VCCB capacitors should be located very close to the VCCA/VCCB pins and tied immediately to the ground plane. Capacitor Selection Warning: A polarized capacitor such as tantalum or aluminum should never be used for the flying capacitor since its voltage can reverse upon start up of the LTC1955. Low ESR ceramic capacitors should always be used for the flying capacitor. A total of six capacitors are required to operate the LTC1955. An input bypass capacitor is required at PVBATT, SVBATT and DVCC. Output bypass capacitors are required on each of the smart card VCCA/VCCB pins. A charge pump flying capacitor is required from C + to C – and a charge storage capacitor is required on the charge pump out pin CPO. (i.e., minimum inductance). The PVBATT/SVBATT nodes should be especially well bypassed. The capacitor for this node should be directly adjacent to the QFN package. The CPO and flying capacitors should be very close as well. The LTC1955 can tolerate more distance between the LDO capacitors and the VCCA/B pins. Figure 4 shows an example of a tight printed circuit board using single layer copper. For best performance a multilayer board can be used and should employ a solid ground plane on at least one layer. The following capacitors are recommended for use with the LTC1955: Type Value Case Size Murata P/N CIN CPO X5R 4.7µF 0805 GRM40-034 X5R 475K 6.3 CFLY VCCA/B X5R 1µF 0603 GRM39 X5R 105K 6.3 CDVCC X5R 0.1µF 0402 GRM36 X5R 104K 10 To prevent excessive noise spikes due to charge pump operation, low ESR (equivalent series resistance) multilayer ceramic capacitors are strongly recommended. There are several types of ceramic capacitors available each having considerably different characteristics. For example, X7R/X5R ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. Y5V ceramic capacitors have apparently higher packing density but poor performance over their rated voltage or temperature ranges. Under certain voltage and temperature conditions, Y5V and X7R/X5R ceramic capacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. Placement of the capacitors is critical for correct operation of the LTC1955. Because the charge pump generates large current steps, all of the capacitors should be placed as close to the LTC1955 as possible. The low impedance nature of multilayer ceramic chip capacitors will minimize voltage spikes but only if the power path is kept very short VCCA GND VBATT VCCB 1955 F04 Figure 4. Optimum Single Layer PCB Layout sn1955 1955fs 14 LTC1955 U W U U APPLICATIO S I FOR ATIO Interfacing to a Microcontroller Daisy-Chained Operation The serial port of the LTC1955 can be connected directly to a 68HC11 style microcontroller’s serial port. The microcontroller should be configured as the master device and its clock’s idle state should be set to high (MSTR = 1, CPOL␣ = 1 and CPHA = 0 for the MC68HC11 family). Figure␣ 4 shows the recommended configuration and direction of data flow. Note that an additional I/O line is necessary for LD to load the data once it has shifted around the loop. Command data is latched into the command register on the falling edge of the LD signal. The LTC1955 will begin to act on new command data as soon as LD goes low. Any general purpose microcontroller I/O line can be configured to control the LD pin. For applications requiring more than two card sockets, the serial port of the LTC1955 is designed to be easily daisychained. The DOUT pin of one LTC1955 can be connected directly to the DIN pin of another LTC1955. Rather than sending two 8-bit bytes before asserting LD, the microcontroller should send two 8-bit bytes per device. LD should only be asserted after all devices have been updated. Figure 7 shows three LTC1955s cascaded in daisy chain fashion. In this case the microcontroller would write six 8-bit bytes before asserting the LD pin. Alternatively, if two serial ports are available on the microcontroller, then two LTC1955s can be controlled independently. The status of the LTC1955 is returned over the serial port. Status data is latched into the shift register on the rising edge of the LD pin. Whenever the system is waiting for status data from the LTC1955, its LD pin should be held low. µCONTROLLER MOSI If the DATA lines of two or more LTC1955s are connected together, the static pull-up current will be the sum of the devices. The static current can be brought back to the level of a single LTC1955 by setting bit D3 on all but one of the LTC1955s to 1 (see Table 1). Bit D3 disables the pull-up current source on the DATA pin. This will help prevent VOL problems in multiple LTC1955 applications when driving the DATA or I/O pins low. LTC1955 DIN CARD A MISO DOUT SCK SCLK CARD B I/O LD 1955 F05 Figure 5. Microcontroller Interface sn1955 1955fs 15 LTC1955 U W U U APPLICATIO S I FOR ATIO Using S.A.M. Cards Using the UNDERV Pin For applications using one or more installed S.A.M. cards, the PRES A/PRES B pins for those sockets must be grounded before operation of the card can occur (assuming NC/NO is grounded). The PRES A/PRES B pull-up current is designed for very low consumption, but ultralow current can be achieved in shutdown by using a microcontroller output to pull down on the PRES A/PRES B pins only when communication is necessary. The fault detection circuitry will not allow a card socket to be operated unless a card is detected. The UNDERV pin can be used to add protection against a supply undervoltage fault. By using two external programming resistors, the undervoltage detection can be set to an arbitrary level (Figure 8). To ensure that the smart cards are properly shut down, there must be sufficient energy available in the input bypass capacitor to run one or both smart cards until the deactivation cycle begins. It can take approximately 30µs from the detection of a fault until the deactivation sequence begins. It is desirable to maintain the VBATT supply at 2.7V or greater during this period. Asynchronous Channel A Card Detection Since the shift register is transparent when LD is held low, DOUT is the same as D15. Recall from Table 1 that D15 indicates the status of the card detection channel for channel A. Thus, it is not necessary to perform an entire read/write operation to determine the card detection status of channel A. With LD low, DOUT can be used to generate a real time card detection interrupt. This could be useful for one S.A.M. card, one smart card applications. Inter Card Communication Communication is possible directly from one card socket to the other when both cards are selected at the same time. This can be achieved by the following sequence of actions. 1) Start with both cards off and deselected 2) Activate the supply of the slave card 3) Select the slave card only 4) Initiate a reset on the slave card 5) Deselect the slave card 6) Activate the supply of the master card 7) Select the master card only 8) Initiate a reset on the master card 9) Select both cards Consider the following (worst-case) example: 1) The UNDERV pin is programmed to trip below 3.1V. 2) It is possible to have both cards activated at 5V and drawing 60mA. Since the output voltage is programmed to 5V, the charge pump will be acting as a voltage doubler. With two cards drawing 60mA each, the input current will be 2 • (60mA + 60mA) or about 240mA. Allowing the VBATT supply to droop from 3.1V to 2.7V during the 30µs timeout period, the input capacitance would need to be at least 240mA / [(3.1V – 2.7V) / 30µs] or 18µF. Thermal Management To minimize power dissipation, the LTC1955 will actively decide whether to step up or down depending on the required output voltages and available input voltage. However, for optimum efficiency, the LTC1955 should be powered from a 3.3V supply. If the input voltage is above 3.6V, and both cards are drawing maximum current, there can be substantial power dissipation in the LTC1955. If the junction temperature increases above approximately 150°C, the thermal shutdown circuitry will automatically deactivate both channels. To reduce the maximum junction temperature, a good thermal connection to the PC board is recommended. Zero Shutdown Current Although the LTC1955 is designed to have very low shutdown current, it can still draw over a microampere on sn1955 1955fs 16 LTC1955 U W U U APPLICATIO S I FOR ATIO both DVCC and VBATT when in shutdown. For applications that require virtually zero shutdown current, the DVCC pin can be grounded. This will reduce the VBATT current to well under a single microampere. Internal logic ensures that the LTC1955 is in shutdown when DVCC is grounded. Note, however, that all of the logic signals that are referenced to DVCC (DIN, SCLK, LD, DATA, RIN, SYNC, ASYNC and NC/NO) will have to be at 0V as well to prevent ESD diodes to DVCC from being forward biased. Operation at Higher Supplies If a 5.5V to 6V supply voltage is available, it is possible to achieve some power savings by bypassing the charge pump. The higher supply can be connected directly to the CPO pin. As long as the voltage on CPO is higher than that at which it ordinarily regulates (5.35V or 3.7V depending on voltage selections) the charge pump’s oscillator will not run. This configuration can give considerable power savings since the charge pump is not being used. A voltage source is still needed on both DVCC and SVBATT/ PVBATT in this configuration. Recall that DVCC sets the logic reference level for all the control and smart card communication pins. The voltage on SVBATT/PVBATT can be any convenient level that meets the parameters in the Electrical Characteristics table. The 5.5V to 6V supply can be left permanently connected to CPO but there will be approximately 5µA of current flow into CPO when the LTC1955 is in shutdown. Charge Pump Strength Under low VBATT conditions, the amount of current available to the smart cards is limited by the charge pump. Figure 6 shows how the LTC1955 can be modeled as a Thevenin equivalent circuit to determine the amount of current available given the effective input voltage, 2VBATT and the effective open-loop output resistance, ROLCP. From Figure 6, the available current is given by: ICCA + ICCB ≤ 2VBATT – VCPO ROLCP ROLCP is dependent on a number of factors including the switching term, 1/(fOSC • CFLY), internal switch resistances and the nonoverlap period of the switching circuit. However, for a given ROLCP, the minimum CPO voltage can be determined from the following expression: VCPO ≥ 2VBATT – (ICCA + ICCB )ROLCP The LDOs have been designed to meet all applicable smart card standards for VCC with VCPO as low as 5.13V. Given this information, trade-offs can be made by the user with regard to total consumption (ICCA + ICCB) and minimum supply voltage. ROLCP CPO + – 2VBATT LDO A VCCA LDO B VCCB 1955 F06 Figure 6. Equivalent Open-Loop Circuit Changing the Smart Card Supply Voltage Although the LTC1955 control system will allow the smart card voltage to be changed from one value to the next without an interim power down, this is not recommended. When changing from a higher voltage to a lower voltage there will generally not be a problem; however, changing from a lower voltage to a higher voltage will result in both an undervoltage condition and an overcurrent condition on that channel. The likely result is that the channel will automatically deactivate. Applicable smart card standards specify that the smart card supply be powered to zero before applying a new voltage. Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC1955 or smart card system. Generally a 100Ω resistor and a 20pF capacitor will accomplish this as shown in Figure 9. sn1955 1955fs 17 LTC1955 U W U U APPLICATIO S I FOR ATIO 1µF 4.7µF 12, 13 INPUT POWER FAULT 4-WIRE COMMAND INTERFACE 4-WIRE CARD INTERFACE 11 14 C– C+ VBATT 9, 10 GND 1 DVCC 23 UNDERV 24 FAULT 27 DIN 28 DOUT 26 SCLK 25 LD 29 DATA 30 RIN 32 SYNC 31 ASYNC 21 PRES B 2 PRES A SMART CARD VENDOR CARD LTC1955 CPO 15 4.7µF 1µF 4.7µF 12, 13 11 14 C– C+ VBATT 9, 10 GND 1 DVCC 23 UNDERV 24 FAULT 27 DIN 28 DOUT 26 SCLK 25 LD 29 DATA 30 RIN 32 SYNC 31 ASYNC 21 PRES B 2 PRES A SMART CARD VENDOR CARD LTC1955 CPO 15 4.7µF 1µF 4.7µF 12, 13 11 C– VBATT 9, 10 GND 1 DVCC 23 UNDERV 24 FAULT 27 DIN 28 DOUT 26 SCLK 25 LD 29 DATA 30 RIN 32 SYNC 31 ASYNC 14 C+ 21 PRES B 2 PRES A VENDOR CARD VENDOR CARD LTC1955 CPO 15 4.7µF 1955 F07 Figure 7. Multiple LTC1955s Daisy Chained Together sn1955 1955fs 18 LTC1955 U U W U APPLICATIO S I FOR ATIO MAIN SUPPLY R1 UNDERV 100Ω VTRIP = 1.23V (1 + R1/R2) 100Ω 23 20pF C3 CLK X 100Ω LTC1955 20pF C2 RST X R2 LTC1955 C7 I/O X SMART CARD SOCKET 20pF C1 VCCX 1µF C5 0.1µF 1955 F08 1955 F09 Figure 8. Setting the Undervoltage Trip Point Figure 9. Additional Components for Improved Compliance Testing U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.57 ±0.05 5.35 ±0.05 4.20 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.23 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 0.40 ± 0.10 31 32 PIN 1 TOP MARK 1 2 3.45 ± 0.10 (4-SIDES) (UH) QFN 0102 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 0.23 ± 0.05 0.50 BSC sn1955 1955fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1955 U TYPICAL APPLICATIO 0.1µF FAULT 0.1µF 17 4 RXEN DREN VCC 16 21 45 47k 19 37 1 1k MOD B VDD VRH XIRQ 4 5 262k 180k 0.1µF 47k RESET 23 DVCC 3 4.7µF + Li-ION 12, 13 UNDERV VBATT VCC18 VCC3 VCCA RST LTC1348CG 36 1 MC68L11E9PB2 RST LTC1728ES5-1.8 GND 24 FAULT LTC1955EUH 2 DB9 RD 2 7 TD 3 8 DR1OUT DR1IN RX1IN RX1OUT 25 40 24 39 PD1 (TXD) IRQ PD0 (RXD) (MOSI) PD3 41 43 (SCK) PD4 44 (SS) PD5 (MISO) PD2 GND 5 0.1µF 0.1µF 5 C1+ 27 C3 + 6 C1 – C3 – 2 C2 + 3 C2 – 26 C8 4 C4 5 C7 6 7 CLK A 8 VCCA C2 C4A 38 42 3 C8A 27 I/O A DIN RST A 28 DOUT 26 SCLK 25 LD 1µF PB1 (IC3) PA0 PC0 24 31 8 32 9 30 1 29 28 ASYNC I/O B SYNC RST B RIN CLK B DATA VCCB 1 0.1µF V GND 28 15 VRL VSS MODA EXTAL 18 20 22 26 XTAL C7 19 18 C2 CARD B C3 C1 17 0.1µF C5 C 27 20 1µF PRES B V 2 0.1µF (2MHz) E – 0.1µF C5 PRES A PB0 + CARD A C3 C1 – C 11 + CPO 14 0.1µF GND 15 21 NC/NO 9, 10 22 4.7µF 10M 8.000MHz 27pF 1µF 27pF 1955 TA02 Battery Powered RS232 to Dual Smart Card Interface RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1755/LTC1756 ISO 7816-3 and EMV Compatible Smart Card Interface VOUT = 3V/5V, VIN = 2.7V to 6V, SSOP-16/-24 Package LTC1555 SIM Power Supply and Level Translator Step-Up/Step-Down Charge Pump VOUT = 3V/5V, VIN = 2.7V to 10V, SSOP-16/-20 Package LTC1555L-1.8 SIM Power Supply and Level Translator Step-Up/Step-Down Charge Pump VOUT = 1.8V/3V/5V, VIN = 2.6V to 6V, SSOP-16 Package LTC4555 SIM Power Supply and Level Translator VOUT = 1.8V/3V, VIN = 3V to 6V, 3mm × 3mm QFN Package sn1955 1955fs 20 Linear Technology Corporation LT/TP 0303 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2002