74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 • • • • • • DW OR N PACKAGE (TOP VIEW) Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 1Q 2Q 3Q GND GND GND GND 4Q 5Q 6Q 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 CLR 1D 2D 3D VCC VCC 4D 5D 6D CLK description This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The 74AC11174 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X QO EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 logic symbol† 20 CLR CLK 1D 2D 3D 4D 5D 6D 11 logic diagram (positive logic) R CLR 20 C1 19 1D 1 18 2 17 3 14 8 13 9 12 10 1Q CLK 2Q 3Q 11 19 1D 1D C1 4Q 1Q R 5Q 6Q 1 2D 18 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1D C1 2 2Q R 17 3D 1D C1 3 3Q R 4D 14 1D C1 8 4Q R 13 5D 1D C1 9 5Q R 6D 12 1D C1 10 6Q R absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V MIN NOM MAX 3 5 5.5 V 3.85 0.9 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current 1.35 VCC = 5.5 V Input transition rise or fall rate TA Operating free-air temperature V V –4 –24 mA –24 VCC = 3 V VCC = 4.5 V VCC = 5.5 V ∆t/∆v V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V VCC = 5.5 V Low-level output current V 2.1 3.15 VCC = 3 V VCC = 4.5 V IOL UNIT 12 24 mA 24 0 10 ns/ V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 µA VOH MIN TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 IOL = – 24 mA A 5.5 V 4.94 IOH = – 75 mA† 5.5 V IOL = 12 mA IOL = 24 mA II ICC TA = 25°C 5.5 V IOH = – 4 mA IOL = 50 µA VOL VCC MAX UNIT V 4.8 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† 5.5 V VI = VCC or GND VI = VCC or GND, 5.5 V ± 0.1 ±1 µA 5.5 V 8 80 µA IO = 0 Ci VI = VCC or GND 5V 4 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.65 pF 2–3 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 CLR low tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ CLK high or low Data CLR inactive 80 MIN MAX UNIT 0 80 MHz 4.5 4.5 6 6 7 7 1.5 1.5 0 0 ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ 100 MIN MAX UNIT 0 100 MHz CLR low 4 4 CLK high or low 5 5 Data 4.5 4.5 CLR inactive 1.5 1.5 0 0 ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN fmax tPHL tPLH tPHL 80 Any Q CLR CLK Any Q TA = 25°C TYP MAX 105 MIN MAX 80 UNIT MHz 3.9 10 13.5 3.9 14.8 2.4 7.5 9.2 2.4 10.8 3.4 9.6 12.7 3.4 14 ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPHL CLR Any Q tPLH tPHL CLK Any Q PARAMETER fmax MIN TA = 25°C TYP MAX MIN MAX 100 125 2.9 6.5 9.8 100 2.9 2.1 4.9 6.8 2.1 7.6 2.7 6.2 9.2 2.7 10.1 UNIT MHz 10.7 ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 2–4 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 29 pF 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) VCC 500 Ω Input 50% 50% 0V VOLTAGE WAVEFORMS LOAD CIRCUIT VCC Input (see Note B) Timing Input (see Note B) VCC 50% 0V th tsu Data Input 50% 50% 0V tPHL tPLH In-Phase Output 50% VCC VCC 50% tPLH tPHL 50% 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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