TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 D D D D D D D D D D D D D DWB PACKAGE (TOP VIEW) Single 5-V Power Supply Sample Rates (Fs) up to 48 kHz 18-Bit Resolution Pulse-Width-Modulation (PWM) Output De-emphasis Filter for Sample Rates of 32, 37.8, 44.1, and 48 kHz Mute With Zero-Data-Detect Flags Digital Attenuation to – 60 dB Total Harmonic Distortion of 0.004% Maximum Total-Channel Dynamic Range of 96 dB Minimum Serial-Port Interface Differential Architecture CMOS Technology 2s-Complement Data Format INIT TEST ATT SHIFT LATCH 256FSO TEST DGND TEST BCK DATA LRCK MUTEL MUTER 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DVDD L1 AVDDL L2 AGNDL XGND XIN XOUT XVDD AGNDR R2 AVDDR R1 DVDD description The TMS57014A is a stereo oversampled-sigma-delta digital-to-analog converter (DAC) designed for use in systems such as compact disks, digital audio tapes, multimedia, and video cassette recorders. The device provides high-resolution signal conversion. This device consists of two identical synchronous conversion paths for left and right audio channels. Other overhead functions provide on-chip timing and control. Additional features include muting, attenuation, de-emphasis, and zero-data detection. Control words (16-bit) from a host controller or processor implement these functions. The TMS57014A is characterized for operation from 0°C to 70°C. AVAILABLE OPTION† PACKAGE TA SMALL OUTLINE (DWB) 0°C to 70°C TMS57014ADWBLE † Available on tape and reel (LE) only. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 functional block diagram INIT XIN XOUT 256FSO 1 22 21 6 ATT SHIFT LATCH 3 4 5 Serial Control Timing and Control 13 14 MUTEL MUTER Attenuation Interpolation Filter DATA 11 10 BCK LRCK 12 Serial Data Interface Zero-Data Detect Zero-Data Detect Interpolation Filter 2 POST OFFICE BOX 655303 De-emphasis Filter DAC Modulator 27 25 L1 L2 16 18 R1 R2 Left Channel Right Channel De-emphasis Filter • DALLAS, TEXAS 75265 DAC Modulator TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 Terminal Functions TERMINAL NAME ATT NO. I/O DESCRIPTION 3 I Serial control data. ATT is a 16-bit word configured as LSB first (see Tables 2, 3, and 4). AVDDL AVDDR 26 I Analog power supply (left channel) 17 I Analog power supply (right channel) AGNDL 24 I Analog ground (left channel) AGNDR 19 I Analog ground (right channel) BCK 10 I Bit clock input. BCK clocks serial audio data into the device. DATA 11 I Audio data input. DATA can be configured as 16 or 18 bits with MSB or LSB first. DATA is 2s complement. DVDD 15, 28 I Digital supply DGND 8 I Digital ground INIT 1 I Reset. When INIT is brought low, the device is reset. The device is activated on the rising edge of INIT. The LRCK signal must be applied to the device for a reset to occur. LATCH 5 I Serial-control data latch. Control data loads into the internal registers when LATCH is brought low. LRCK 12 I Left /right clock. LRCK signifies whether the serial data is associated with the left-channel DAC (when high) or the right-channel DAC (when low). MUTEL 13 O Left-channel mute flag active. When the left channel is mute or the data through the channel remains at zero for the system-register selected time, MUTEL is brought low. MUTER 14 O Right-channel mute flag active. When the right channel is mute or the data through the channel remains at zero for the system-register selected time, MUTER is brought low. L1 27 O Left PWM output 1 L2 25 O Left PWM output 2 R1 16 O Right PWM output 1 R2 18 O Right PWM output 2 SHIFT 4 I Shift clock. SHIFT clocks the control data into the internal registers. TEST 2, 7, 9 I All TEST inputs should be tied low. XIN 22 I Master clock in. XIN derives all the key logic signals of the device. XIN runs at 512 Fs, where Fs is the sample rate. XOUT 21 O Master clock out XVDD XGND 20 I Power supply for clock section 23 I Ground for clock section 6 O System clock out. 256FSO reflects the master clock input divided by 2. The rate is 256Fs, where Fs is the sample rate. 256FSO detailed description The TMS57014A incorporates an interpolation impulse-response filter (FIR) and oversampled modulator. The pulse-width modulation (PWM) digital output feeds into an external low-pass filter to recover the analog audio signal. Two control registers configure the device, the attenuation register controls the attenuation range and the system register controls additional functions (see register set section). reset/ initialization When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling frequency (Fs) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive for a maximum of five LRCK periods after the rising edge of INIT. At this point, internal clocks are synchronous with LRCK and the PWM output is valid (see Figure 1). The LRCK signal must be applied for proper initialization. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 reset/ initialization (continued) 5 periods max 120 Cycles of Fs INIT Internal Reset LRCK Figure 1. Reset Timing Relationships timing and control The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is shown in Table 1. The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate master-clock frequency. Some of the functions of the converter, such as the de-emphasis filter, operate only at the frequencies in Table 1. Table 1. Master Clock to Sample Rate Comparison XIN (MHz) 256FSO (MHz) LRCK (kHz) 24.5760 12.2880 48.0 22.5792 11.2896 44.1 19.3536 9.6768 37.8 16.3840 8.1920 32.0 digital-audio data interface The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB first as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16-bit data or 36 Fs for 18-bit data where Fs is the sample rate. Figure 2 illustrates the input timing. BCK DATA (16-bit) DATA (18-bit) LRCK ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 17 16 15 14 1 0 15 14 1 0 Left Channel ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 17 Right Channel Figure 2. Audio-Data Input Timing 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 15 14 1 15 14 1 ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ 0 0 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 serial-control interface This device uses the least-significant-bit-first format. Therefore, for a 16-bit word, D15 is the most significant bit and D0 is the least significant bit. Unless otherwise specified, all values are in 2s-complement format. serial-control-data input The 16-bit control-data input implements the device-control functions. The TMS57014A has two registers for this data: the system register and the attenuation register. The system register contains most of the system configuration information, and the attenuation register controls audio output level, de-emphasis, and mute. Figure 3 illustrates the input timing for ATT, SHIFT, and LATCH. The data loads internally on the falling edge of LATCH. The shift clock should be high for the LATCH setup time before LATCH goes low. SHIFT ATT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 LSB 14 15 MSB LATCH Figure 3. Control-Data-Input Timing mute When mute is activated, the output PWM becomes zero data (50% duty cycle). The two mute flags, MUTEL and MUTER, are independently set low based on the data in the respective channel being zero. This function becomes active under the following conditions: 1. When the zero-data detector detects that the input data has been zero for 2500 cycles of Fs or 12 500 cycles of Fs (as selected in the control registers), output is 50% duty cycle. 2. When the MUTE register value is set high by means of the serial-control data. 3. When INIT is active (low), output is 50% duty cycle. zero-data detect After the input data remains zero for 2500 or 12 500 cycles of Fs as set by the system register (D4, D5), the channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The zero-detect register value in the serial-control data selects the detection period. The mute flag returns high immediately when nonzero input data is received. de-emphasis filter Four sets of de-emphasis-filter coefficients support four sampling rates (Fs): 32, 37.8, 44.1, and 48 kHz. Internal register values select the filter coefficients. The internal register values enable or disable the filter. Figure 4 illustrates the de-emphasis characteristics. Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the de-emphasis characteristics shown in Figure 4. This device provides reconstruction of the original frequency response. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 de-emphasis filter (continued) Response – dB 10 0 – 10 De-emphasis 3.18 (50 µs) 10.6 (15 µs) Frequency – kHz Figure 4. De-emphasis Characteristics digital attenuation A value selected in the internal attenuation register determines the attenuation of the digital-audio-data input. The attenuation value is 11 bits long with a valid range of hex values from 400h to 000h. A data value of 001h corresponds to an attenuation value of – 60 dB and a data value of 400h corresponds to 0 dB. The attenuation function is nonlinear (see equation 1). Figure 5 illustrates the attenuation function in dB. The default attenuation value is 400h. Attenuation + 20 log ǒ Ǔ attenuation data 1024 (1) 0 Attenuation – dB – 10 – 20 – 30 – 40 – 50 – 60 1024 896 768 640 512 384 256 128 0 Attenuation Data (decimal values) Figure 5. Digital Attenuation Characteristics 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 register set Table 2 contains the register-set selection. Tables 3 and 4 list the bit functions. Table 2. Register-Set Selection BITS DESCRIPTION 15 14 0 0 Attenuation register 0 1 System register 1 x Invalid condition† † Bit 15 should always be set to 0 when writing data for proper operation. Table 3. Attenuation-Register Bit Functions BITS‡ FUNCTION 13 12 11 10 – 0 0 — — — De-emphasis off 1 — — — De-emphasis on — 0 — — Channel mute off — 1 — — Channel mute on — — 0 — Bit 11 must be low — — — 0 Digital attenuation, mute — — — 1 — — — 2 Digital attenuation, – 60.2 dB§ Digital attenuation, – 54.2 dB§ — — — 3 Digital attenuation, – 50.7 dB§ — — — ... — — — 1FF — — — 200 Digital attenuation, – 6.04 dB§ Digital attenuation, – 6.02 dB§ — — — 201 Digital attenuation, – 6.00 dB§ — — — ... — — — 3FF Digital attenuation, – 0.01 dB§ Digital attenuation, 0.00 dB§ — — — 400 ‡ Default value = 0400h § The attenuation values shown are typical values. Refer to the digital attenuation section for a description of the attenuation function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 Table 4. System-Register Bit Functions BITS† FUNCTION 13 12 11 – 6 5 4 3–2 1 0 0 — — — — — — — MSB first, audio data 1 — — — — — — — LSB first, audio data — 0 — — — — — — 16-bit, audio data — 1 — — — — — — 18-bit, audio data — — 0 — — — — — Bits 11– 6 must be low — — — 0 — — — — Zero data detect period (2500 cycles of Fs) — — — 1 — — — — Zero data detect period (12500 cycles of Fs) — — — — 0 — — — Bit 4 must be low — — — — — 0 — — De-emphasis – 44.1 kHz — — — — — 1 — — De-emphasis – 48.0 kHz — — — — — 2 — — De-emphasis – 37.8 kHz — — — — — 3 — — De-emphasis – 32.0 kHz — — — — — — 0 — LRCK and PWM are not synchronized — — — — — — 1 — LRCK and PWM synchronized — — — — — — — 0 Bit 0 must be low † Default value = 0000h interpolation filter The interpolation filter used prior to the DAC increases the digital-data rate from the LRCK speed to the oversampled rate by interpolating with a ratio of 1:32. The oversampling modulator receives the output of this filter with de-emphasis as an option. DAC modulator The DAC is a third-order modulator with 32 times oversampling. The DAC provides high-resolution, low-noise performance using a 15-value PWM output as shown in Figure 6. Noise Power – dB APB(max)¶ Quantization Noise Power With Noise Shaping Audio Signal Noise Excluded by Low-Pass Filter Quantization Noise Power Without Noise Shaping 0 0 fB§ 0.1 0.2 0.3 0.4 0.5 Normalized Analog-Output Frequency (fO/Fs‡) ‡ fO is the output frequency at the low-pass filter output (VO) shown in Figure 7. § fB is the highest frequency of interest within the baseband. ¶ APB(max) is the passband maximum amplitude. Figure 6. Oversampling Noise Power With and Without Noise Shaping 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 PWM output (L2 – L1 and R2 – R1) The L 2 – L1 and the R2 – R1 output pairs are PWM signals with the L 2 – L1 differential pulse duration determining the left-channel analog voltage and the R2 – R1 differential pulse duration determining the right-channel analog voltage. Each DAC left and right output consists of 15 levels of PWM and provides a differential signal as the input to two external differential amplifiers configured as a low-pass filter to produce the left and right audio outputs (see Figure 7). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Analog supply voltage range, left and right, AVDDL, AVDDR (see Note 1) . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Digital supply voltage range, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Clock supply voltage range, XVDD (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range, VO: L1, L 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDDL + 0.3 V R1, R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDDR + 0.3 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Case temperature for 10 seconds, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values for maximum ratings are with respect to AGNDL and AGNDR respectively. 2. Voltage values for maximum ratings are with respect to DGND. 3. Voltage values for maximum ratings are with respect to XGND. recommended operating conditions (see Note 4) MIN NOM MAX UNIT Analog supply voltage, left and right, AVDDL, AVDDR 4.75 5 5.25 V Digital supply voltage, DVDD 4.75 5 5.25 V Clock supply voltage, XVDD 4.75 5 5.25 V High level input voltage, High-level voltage VIH Low level input voltage, Low-level voltage VIL XIN 0.9 VDD 0.76 VDD All other digital inputs V XIN 0.1 VDD All other digital inputs 0.24 VDD Load resistance at PWM, RL 10 Master clock frequency at XIN Operating free-air temperature, TA V kΩ 16.3 24.6 MHz 0 70 °C NOTE 4: DVDD, AVDDL, XVDD and AVDDR tied together represents VDD. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) digital interface, AVDD = DVDD = 5 V ± 5% (see Note 4) PARAMETER TEST CONDITIONS 256FSO VOH L1, L 2, R1, R2 High level output voltage High-level XOUT MUTEL, MUTER 256FSO VOL L1, L 2, R1, R2 Low level output voltage Low-level XOUT MUTEL, MUTER TYP† MIN IO = – 0.4 mA IO = – 12 mA VDD – 0.5 VDD – 0.5 IO = – 1.2 mA IO = – 1 mA VDD – 0.5 VDD – 0.5 MAX UNIT V IO = 0.4 mA IO = 12 mA 0.4 IO = 1.2 mA IO = 1 mA 0.5 0.5 V 0.4 IIH IIL High-level input current, any digital input ±1 ±5 µA Low-level input current, any digital input ±1 ±5 µA Ci Input capacitance Co Output capacitance † All typical values are at TA = 25°C. NOTE 4: DVDD, AVDDL, XVDD and AVDDR tied together represents VDD. 5 pF 5 pF supplies, AVDD = DVDD = 5 V ± 5%, no load PARAMETER Analog power supply current TEST CONDITIONS MIN TYP† AVDDL and AVDDR are shorted together Digital power supply current MAX UNIT 15 mA 15 mA Total device supply current over operating temperature range Power dissipation † All typical values are at TA = 25°C. 60 mA 350 mW DAC modulator, AVDD = DVDD = 5 V ± 5%, sample rate (Fs) = 44.1 kHz, full-scale input sine wave at 1 kHz, TA = 25°C, bandwidth is 20 Hz to 20 kHz PARAMETER TEST CONDITIONS Resolution See Note 5 Signal-to-noise ratio A-weighted, 20 Hz to 20 kHz, See Figure 10, Table 5, and Note 5 TYP† MIN MAX 18 De-emphasis not selected UNIT bits 96 100 Total harmonic distortion 20 Hz to 20 kHz, See Note 5 † All typical values are at TA = 25°C. NOTE 5: These specifications are measured at the output (VO) of the low-pass filter shown in Figure 7. 0.003% dB 0.004% filter characteristics, AVDD = DVDD = 5 V ± 5%, de-emphasis disabled PARAMETER Pass-band ripple Stop-band attenuation TEST CONDITIONS Sample rate (Fs) = 48 kHz kHz, See Note 5 Pass band (– 3 dB) (DAC) Stop band TYP† – 0.002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 0.002 dB 75 dB 0 See Note 5 Group delay † All typical values are at TA = 25°C. NOTE 5: These specifications are measured at the output (VO) of the low-pass filter shown in Figure 7. 10 MIN 0.46 Fs 0.54 Fs kHz kHz 29 / Fs s TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 timing requirements (see Figures 8 and 9 and Note 6) MIN tw1 tsu1 Pulse duration, BCK th1 tsu2 th2 tw2 tsu3 th3 tw3 tsu4 MAX UNIT 160 ns Setup time, DATA before BCK↑ 20 ns Hold time, DATA after BCK↑ 20 ns Setup time, LRCK before BCK↑ 50 ns Hold time, LRCK after BCK↑ 50 ns 100 ns Setup time, ATT before SHIFT↑ 20 ns Hold time, ATT after SHIFT↑ 20 ns Pulse duration, LATCH 100 ns Setup time, LATCH before SHIFT↑ 100 ns tw2 + 20 ns Pulse duration, SHIFT th4 Hold time, LATCH after SHIFT↑ NOTE 6: All timing measurements were taken at the VDD/2 voltage level. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION 22 kΩ 4700 pF 15 V 100 pF 10 kΩ 5.6 kΩ L2 (R2) 2 560 pF 3 560 pF _ 8 6 _ 1 1.5 kΩ 1.5 kΩ 5 + + 4 NE5532 1200 pF 8 7 22 µF NE5532 4 100 Ω 220 kΩ VO (BNC) AVSSL (AVSSR) L1 (R1) 10 kΩ – 15 V 5.6 kΩ AGNDL (AGNDR) AGNDL (AGNDR) 100 pF 22 kΩ AGNDL (AGNDR) Figure 7. Analog Low-Pass Filter Recommended for Measuring the Dynamic Specifications of the TMS57014A tsu2 tw1 tw1 tsu1 th1 th2 BCK DATA 1 ÎÎÎÎÎÎ 0 LRCK Figure 8. Audio-Data Serial Timing tsu3 th3 SHIFT tw2 ATT 14 tw2 15 0 LATCH th4 Figure 9. Control-Data Serial Timing 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tw3 tsu4 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION Table 5. A-Weighted Data FREQUENCY A WEIGHTING (dB) FREQUENCY A WEIGHTING (dB) 25 – 44.6 ± 2 800 – 0.1 ± 1 31.5 – 39.2 ± 2 1000 0 ±0 40 – 34.5 ± 2 1250 0.6 ± 1 50 – 30.2 ± 2 1600 1.0 ± 1 63 – 26.1 ± 2 2000 1.2 ± 1 80 – 22.3 ± 2 2500 1.2 ± 1 100 – 19.1 ± 1 3150 1.2 ± 1 125 – 16.1 ± 1 4000 1.0 ± 1 160 – 13.2 ± 1 5000 0.5 ± 1 200 – 10.8 ± 1 6300 – 0.1 ± 1 250 – 8.6 ± 1 8000 – 1.1 ± 1 315 – 6.5 ± 1 10000 – 2.4 ± 1 400 – 4.8 ± 1 12500 – 4.2 ± 2 500 – 3.2 ± 1 16000 – 6.5 ± 2 630 – 1.9 ± 1 10 Attenuation – dB 0 – 10 – 20 – 30 – 40 – 50 20 100 1k 10 k 20 k f – Signal Frequency – Hz Figure 10. A-Weighted Function POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 APPLICATION INFORMATION circuit and layout considerations The designer should follow these guidelines for the best device performance. D D D D D Separate digital and analog ground planes should be used. All digital device functions should be over the digital ground plane, and all analog device functions should be over the analog ground plane. The ground planes should be connected at only one point to the direct power supply, and this is usually at the connector edge of the board. A single crystal-controlled clock should synchronously generate all digital signals All power supply lines should include a 0.1-µF and a 1-µF capacitor. When clock noise is excessive, a toroidal inductance of 10 µH should be placed in series with XVDD before connecting to DVDD. The digital input control signals should be buffered when they are generated off the card. Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This minimizes any high-frequency coupling to the analog output. PCB footprint Figure 11 shows the printed-circuit-board (PCB) land pattern for the TMS57014A small-outline package. W P L1 L L2 S L2 L L1 P S W L L1 L2 1.27 9.53 0.76 1.55 0.64 0.91 NOTE A: All linear dimensions are in millimeters. Figure 11. Land Pattern for PCB Layout 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995 MECHANICAL DATA DWB (R-PDSO-G28) PLASTIC SMALL-OUTLINE PACKAGE 0,51 0,35 1,27 28 0,25 M 15 7,90 7,30 10,60 9,80 0,15 NOM 1 14 Gage Plane 17,80 17,20 0,25 0°– 8° 0,70 0,30 Seating Plane 2,80 MAX 0,05 MIN 0,15 4040259 / B 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated