19-0381; Rev 1; 6/96 KIT ATION E EVALU AILABL V A L A MANU Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface ________________________Applications Industrial-Control Systems Robotics Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications Functional Diagram appears at end of data sheet. ____________________________Features ♦ 12-Bit Resolution, 1/2LSB Linearity ♦ Single +5V Operation ♦ Software-Selectable Input Ranges: ±10V, ±5V, 0V to 10V, 0V to 5V ♦ Fault-Protected Input Multiplexer (±16.5V) ♦ 8 Analog Input Channels ♦ 6µs Conversion Time, 100ksps Sampling Rate ♦ Internal or External Acquisition Control ♦ Internal 4.096V or External Reference ♦ Two Power-Down Modes ♦ Internal or External Clock ______________Ordering Information PART TEMP. RANGE MAX197ACNI 0°C to +70°C PIN-PACKAGE 28 Narrow Plastic DIP MAX197BCNI 0°C to +70°C 28 Narrow Plastic DIP MAX197ACWI 0°C to +70°C 28 Wide SO MAX197BCWI 0°C to +70°C 28 Wide SO MAX197ACAI 0°C to +70°C 28 SSOP MAX197BCAI 0°C to +70°C 28 SSOP MAX197BC/D 0°C to +70°C Dice* Ordering Information continued at end of data sheet. *Dice are specified at TA = +25°C, DC parameters only. __________________Pin Configuration TOP VIEW CLK 1 28 DGND CS 2 27 VDD WR 3 26 REF RD 4 25 REFADJ HBEN 5 SHDN 6 MAX197 24 INT 23 CH7 D7 7 22 CH6 D6 8 21 CH5 D5 9 20 CH4 D4 10 19 CH3 D3/D11 11 18 CH2 D2/D10 12 17 CH1 D1/D9 13 16 CH0 D0/D8 14 15 AGND DIP/SO/SSOP/Ceramic SB ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX197 _______________General Description The MAX197 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation, yet accepts signals at its analog inputs that may span both above the power-supply rail and below ground. This system provides 8 analog input channels that are independently software programmable for a variety of ranges: ±10V, ±5V, 0V to +10V, or 0V to +5V. This increases effective dynamic range to 14 bits, and provides the user flexibility to interface 4mA-to-20mA, ±12V, and ±15V powered sensors to a single +5V system. In addition, the converter is overvoltage tolerant to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, a 100ksps throughput rate, software-selectable internal or external clock and acquisition, 8+4 parallel interface, and an internal 4.096V or an external reference. A hardware SHDN pin and two programmable powerdown modes (STBYPD, FULLPD) are provided for lowcurrent shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays. The MAX197 employs a standard microprocessor (µP) interface. A three-state data I/O port is configured to operate with 8-bit data buses, and data-access and bus-release timing specifications are compatible with most popular µPs. All logic inputs and outputs are TTL/CMOS compatible. The MAX197 is available in 28-pin DIP, wide SO, SSOP, and ceramic SB packages. For a different combination of ranges (±4V, ±2V, 0V to 4V, 0V to 2V), see the MAX199 data sheet. For 12-bit bus interface, see the MAX196 and MAX198 data sheets. MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +7V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) CH0–CH7 to AGND ..........................................................±16.5V Continuous Power Dissipation (TA = +70°C) Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW Wide SO (derate 12.50mW/°C above +70°C)..............1000mW SSOP (derate 9.52mW/°C above +70°C) ......................762mW Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW Operating Temperature Ranges MAX197_C_ _ .......................................................0°C to +70°C MAX197_E_ _.....................................................-40°C to +85°C MAX197_M_ _ ..................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note 1) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL ±1/2 MAX197B ±1 ±1 Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching MAX197A ±3 MAX197B ±5 MAX197A ±5 MAX197B ±0.1 Bipolar ±0.5 Unipolar Bipolar LSB LSB LSB ±10 Unipolar Gain Error (Note 2) Gain Temperature Coefficient (Note 2) Bits MAX197A LSB MAX197A ±7 MAX197B ±10 MAX197A ±7 MAX197B LSB ±10 Unipolar 3 Bipolar 5 ppm/°C DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p, fSAMPLE = 100ksps) Signal-to-Noise + Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR MAX197A 70 MAX197B 69 Up to the 5th harmonic dB -85 80 -78 dB dB Channel-to-Channel Crosstalk 50kHz, VIN = ±5V (Note 3) -86 dB Aperture Delay External CLK mode/external acquisition control 15 ns <50 ps Aperture Jitter External CLK mode/external acquisition control Internal CLK mode/internal acquisition control (Note 4) 10 ns 2 _______________________________________________________________________________________ Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 µs ANALOG INPUT Track/Hold Acquisition Time fCLK = 2.0MHz Small-Signal Bandwidth -3dB rolloff ±10V range 5 ±5V range 2.5 0V to 10V range 2.5 0V to 5V range Unipolar Bipolar Unipolar Input Current Bipolar Input Dynamic Resistance Input Capacitance 1.25 0 Input Voltage Range (See Table 1) MHz 10 0 5 -10 10 -5 V 5 0V to 10V range 720 0V to 5V range 360 -10V to 10V range -1200 -5V to 5V range -600 720 µA 360 Unipolar 21 Bipolar 16 (Note 5) kΩ 40 pF INTERNAL REFERENCE REF Output Voltage VREF REF Output Tempco TC VREF TA = +25°C 4.076 4.096 Output Short-Circuit Current Load Regulation 0mA to 0.5mA output current (Note 6) Capacitive Bypass at REF 2.465 With recommended circuit (Figure 1) Buffer Voltage Gain V ppm/°C 30 mA 7.5 mV 4.7 REFADJ Output Voltage REFADJ Adjustment Range 4.116 40 µF 2.500 2.535 V ±1.5 % 1.6384 V/V REFERENCE INPUT (Buffer disabled, reference input applied to REF pin) Input Voltage Range Input Current Input Resistance REFADJ Threshold for Buffer Disable 2.4 4.18 V Normal or STANDBY power-down mode VREF = 4.18V FULL power-down mode Normal or STANDBY power-down mode 10 kΩ FULL power-down mode 5 MΩ 400 µA 1 VDD - 50mV V _______________________________________________________________________________________ 3 MAX197 ELECTRICAL CHARACTERISTICS (continued) MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.25 V POWER REQUIREMENTS Supply Voltage VDD 4.75 Normal mode, bipolar ranges Supply Current IDD 18 Normal mode, unipolar ranges 6 Standby power-down (STBYPD) 700 Full power-down mode (FULLPD) (Note 7) Power-Supply Rejection Ratio (Note 8) PSRR 10 850 120 ±1/2 External reference = 4.096V ±1/2 Internal reference mA µA LSB TIMING Internal Clock Frequency fCLK External Clock Frequency Range fCLK tACQI Acquisition Time tACQE Conversion Time tCONV CCLK = 100pF 1.25 1.56 0.1 Internal acquisition External CLK 3.0 Internal CLK 3.0 External acquisition (Note 9) After FULLPD or STBYPD MHz 5.0 µs 5 External CLK 6.0 Internal CLK, CCLK = 100pF 6.0 Internal CLK, CCLK = 100pF MHz 2.0 3.0 7.7 External CLK Throughput Rate 2.00 10.0 100 62 Bandgap Reference Start-Up Time Power-up (Note 10) 200 Reference Buffer Settling CREF = 4.7µF To 0.1mV REF bypass capacitor fully discharged CREF = 33µF 60 µs ksps µs 8 ms DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11) Input High Voltage VINH Input Low Voltage VINL 2.4 Input Leakage Current IIN VIN = 0V or VDD Input Capacitance CIN (Note 5) V 0.8 V ±10 µA 15 pF 0.4 V 15 pF DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT) Output Low Voltage VOL VDD = 4.75V, ISINK = 1.6mA Output High Voltage VOH VDD = 4.75V, ISOURCE = 1mA Three-State Output Capacitance COUT (Note 5) 4 VDD - 1 _______________________________________________________________________________________ V Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Pulse Width tCS 80 ns WR Pulse Width tWR 80 ns CS to WR Setup Time tCSWS 0 ns CS to WR Hold Time tCSWH 0 ns CS to RD Setup Time tCSRS 0 ns CS to RD Hold Time tCSRH 0 CLK to WR Setup Time tCWS 100 ns CLK to WR Hold Time tCWH 50 ns ns Data Valid to WR Setup tDS 60 Data Valid to WR Hold tDH 0 RD Low to Output Data Valid tDO Figure 2, CL = 100pF (Note 12) 120 ns HBEN High or HBEN Low to Output Valid tDO1 Figure 2, CL = 100pF (Note 12) 120 ns 70 ns 120 ns RD High to Output Disable tTR RD Low to INT High Delay tINT1 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: (Note 13) ns ns Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±10V input range. External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground "on" channel; sine wave applied to all "off" channels. Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Guaranteed by design. Not tested. Use static loads only. Tested using internal reference. PSRR measured at full-scale. External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD = high control byte. Not subject to production testing. Provided for design guidance only. All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V. tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. tTR is defined as the time required for the data lines to change by 0.5V. _______________________________________________________________________________________ 5 MAX197 TIMING CHARACTERISTICS __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY FFT PLOT ftone = 10kHz fsample = 100kHz -20 0.050 0.000 -40 -60 -80 -0.050 -100 -0.100 -0.150 -120 1000 3000 2000 4000 25 50 VDD = 5V ±0.25V 0.2 PSRR (LSB) VREF (V) 4.090 AV = 1.6384 +2.5V INTERNAL REFERENCE REFADJ 120Hz 0 100Hz -0.2 -0.6 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE 0.33 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) MAX197-6 0.18 0.16 0.14 0.12 0.10 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) 100 -0.4 REF 4.080 0.20 10 INPUT FREQUENCY (kHz) 0.4 4.095 CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB) 1 POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE MAX197-4 4.100 6 10.5 FREQUENCY (kHz) REFERENCE OUTPUT VOLTAGE (VREF) vs. TEMPERATURE -55 -35 -15 11.0 10.0 0 DIGITAL CODE 4.085 11.5 MAX197-7 0 FSAMPLE = 100kHz MAX197-5 AMPLITUDE (dB) 0.150 0.100 12.0 EFFECTIVE NUMBER OF BITS 0.200 MAX197-2 0 MAX197-1 0.250 MAX197-3 INTEGRAL NONLINEARITY vs. DIGITAL CODE INTEGRAL NONLINEARITY (LSB) MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface 0.32 0.31 0.30 0.29 0.28 0.27 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) _______________________________________________________________________________________ Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface PIN NAME FUNCTION 1 CLK Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode, place a capacitor from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with CCLK = 100pF. 2 CS Chip Select, active low. 3 WR When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle. 4 RD If CS is low, a falling edge on RD will enable a read operation on the data bus. 5 HBEN Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus; when low, the 8 LSBs are available on the bus. 6 SHDN Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low. 7–10 D7–D4 Three-State Digital I/O 11 D3/D11 Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high). 12 D2/D10 Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high). 13 D1/D9 Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high). 14 D0/D8 Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB. 15 AGND 16–23 CH0–CH7 24 INT 25 REFADJ Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect to VDD when using an external reference at the REF pin. 26 REF Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. 27 VDD +5V Supply. Bypass with 0.1µF capacitor to AGND. 28 DGND Analog Ground Analog Input Channels INT goes low when conversion is complete and output data is ready. Digital Ground +5V +5V 3k MAX197 510k 100k DOUT REFADJ DOUT 3k CLOAD CLOAD 0.01µF 24k a. High-Z to VOH and VOL to VOH Figure 1. Reference-Adjust Circuit b. High-Z to VOL and VOH to VOL Figure 2. Load Circuits for Enable Time _______________________________________________________________________________________ 7 MAX197 ______________________________________________________________Pin Description MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface _______________Detailed Description Converter Operation The MAX197, a multi-range, fault-tolerant ADC, uses successive approximation and internal input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. The parallel-output format provides easy interface to microprocessors (µPs). Figure 3 shows the MAX197 in its simplest operational configuration. Analog-Input Track/Hold In the internal acquisition control mode (control bit D5 set to 0), the T/H enters its tracking mode on WR’s rising edge, and enters its hold mode when the internally timed (6 clock cycles) acquisition interval ends. A low impedance input source, which settles in less than 1.5µs, is required to maintain conversion accuracy at the maximum conversion rate. In the external acquisition control mode (D5 = 1), the T/H enters its tracking mode on the first WR rising edge and enters its hold mode when it detects the second WR rising edge with D5 = 0. See the External Acquisition section. Input Bandwidth The ADC’s input tracking circuitry has a 5MHz smallsignal bandwidth. When using the internal acquisition 1 CLK DGND mode with an external clock frequency of 2MHz, a 100ksps throughput rate can be achieved. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended (MAX274/MAX275 continuous-time filters). Input Range and Protection Figure 4 shows the equivalent input circuit. With VREF = 4.096V, the MAX197 can be programmed for input ranges of ±10V, ±5V, 0V to 10V, or 0V to 5V by setting the appropriate control bits (D3, D4) in the control byte (see Tables 2 and 3). The full-scale input voltage depends on the voltage at REF (Table 1). When an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V < VREF < 4.18V). Table 1. Full Scale and Zero Scale RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE 0 to 5 0 — VREF x 1.2207 0 to 10 0 — VREF x 2.4414 ±5 — -VREF x 1.2207 VREF x 1.2207 ±10 — -VREF x 2.4414 VREF x 2.4414 28 BIPOLAR 100pF 2 µP CONTROL INPUTS 3 4 5 6 7 8 9 10 MAX197 VDD CS WR REFADJ RD HBEN SHDN D7 D6 D5 D4 11 D3/D11 12 D2/D10 13 D1/D9 14 D0/D8 µP DATA BUS Figure 3. Operational Diagram 8 REF INT CH7 CH6 CH5 CH4 CH3 CH2 24 0.1µF UNIPOLAR 4.7µF 5.12k OUTPUT STATUS 23 OFF 12.5k 22 CH_ 21 CHOLD S2 19 T/H OUT ON 20 ANALOG INPUTS 8.67k 18 CH1 17 16 CH0 AGND +4.096V 26 25 VOLTAGE REFERENCE S1 +5V 27 S3 HOLD TRACK TRACK 15 S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH Figure 4. Equivalent Input Circuit _______________________________________________________________________________________ S4 HOLD Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface Output Data Format The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When reading the output data, CS, and RD must be low. When HBEN is low, the lower eight bits are read. When HBEN is high, the upper four MSBs are available and the output data bits D4–D7 are either set low (in unipolar mode) or set to the value of the MSB (in bipolar mode) (Table 6). Digital Interface Input data (control byte) and output data are multiplexed on a three-state parallel interface. This parallel I/O can easily be interfaced with a µP. CS, WR, and RD control the write and read operations. CS is the standard chipselect signal, which enables a µP to address the MAX197 as an I/O port. When high, it disables the WR and RD inputs and forces the interface into a high-Z state. Table 2. Control-Byte Format D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD RNG BIP A2 A1 A0 BIT NAME 7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 4). DESCRIPTION 5 ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition 4 RNG 3 BIP 2, 1, 0 A2, A1, A0 Selects the full-scale voltage magnitude at the input (Table 3). Selects unipolar or bipolar conversion mode (Table 3). These are address bits for the input mux to select the “on” channel (Table 5). Table 3. Range and Polarity Selection BIP RNG Table 4. Clock and Power-Down Selection PD1 PD0 INPUT RANGE (V) 0 0 0 to 5 0 1 0 to 10 1 0 ±5 1 1 ±10 DEVICE MODE 0 0 Normal Operation / External Clock Mode 0 1 Normal Operation / Internal Clock Mode 1 0 Standby Power-Down (STBYPD); clock mode is unaffected 1 1 Full Power-Down (FULLPD); clock mode is unaffected Table 5. Channel Selection A2 A1 A0 CH0 0 0 0 ∗ 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ∗ ∗ ∗ ∗ ∗ ∗ ∗ _______________________________________________________________________________________ 9 MAX197 Input Format The control byte is latched into the device, on pins D7–D0, during a write cycle. Table 2 shows the controlbyte format. The input channels are overvoltage protected to ±16.5V. This protection is active even if the device is in power-down mode. Even with VDD = 0V, the input resistive network provides current-limiting that adequately protects the device. MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface Writing a new control byte during conversion cycle will abort conversion and start a new acquisition interval. Table 6. Data-Bus Output PIN HBEN = LOW D0 B0 (LSB) B8 HBEN = HIGH D1 B1 B9 D2 B2 B10 D3 B3 B11 (MSB) D4 B4 B11 (BIP = 1) / 0 (BIP = 0) D5 B5 B11 (BIP = 1) / 0 (BIP = 0) D6 B6 B11 (BIP = 1) / 0 (BIP = 0) D7 B7 B11 (BIP = 1) / 0 (BIP = 0) Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3µs with fCLK = 2MHz) ends. See Figure 5. External Acquisition Use the external acquisition timing mode for precise control of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR’s rising edge (Figure 6). However, if the second control byte contains ACQMOD = 1, an indefinite acquisition interval is restarted. The address bits for the input mux must have the same values on the first and second write pulses. Powerdown mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode). How to Start a Conversion Conversions are initiated with a write operation, which selects the mux channel and configures the MAX197 for either unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external. The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode. tCS CS tACQI tCSWS tCSRH tCSRS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D7–D0 ACQMOD ="0" tINT1 INT RD HBEN tD0 HGH-Z DOUT tTR tD01 HIGH / LOW BYTE VALID HIGH / LOW BYTE VALID Figure 5. Conversion Timing Using Internal Acquisition Mode 10 ______________________________________________________________________________________ HGH-Z Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface MAX197 tCSRS tCS tCSRH CS tCSWS tWR tACQI tCSHW tCONV WR tDH tDS D7–D0 CONTROL BYTE ACQMOD = "1" CONTROL BYTE ACQMOD = "0" tINT1 INT RD HBEN tD01 tD0 HIGH / LOW BYTE VALID DOUT tTR HIGH / LOW BYTE VALID Figure 6. Conversion Timing Using External Acquisition Mode Clock Modes The MAX197 operates with either an internal or an external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clock mode is selected, changing these bits to program power-down will not affect the clock mode. In each mode, internal or external acquisition can be used. At power-up, external clock mode is selected. Internal Clock Mode Select internal clock mode to free the µP from the burden of running the SAR conversion clock. To select this mode, write the control byte with D7 = 0 and D6 = 1. A 100pF capacitor between the CLK pin and ground sets this frequency to 1.56MHz nominal. Figure 7 shows a linear relationship between the internal clock period and the value of the external capacitor used. INTERNAL CLOCK PERIOD (ns) How to Read a Conversion A standard interrupt signal, INT, is provided to allow the device to flag the µP when the conversion has ended and a valid result is available. INT goes low when conversion is complete and the output data is ready (Figures 5 and 6). It returns high on the first read cycle or if a new control byte is written. 2000 1500 1000 500 0 0 50 100 150 200 250 300 350 CLOCK PIN CAPACITANCE (pF) Figure 7. Internal Clock Period vs. Clock Pin Capacitance ______________________________________________________________________________________ 11 MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface External Clock Mode Select external clock mode by writing the control byte with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR timing relationships in internal and external acquisition modes, with an external clock. A 100kHz to 2.0MHz external clock with 45% to 55% duty cycle is required for proper operation. Operating at clock frequencies lower than 100kHz will cause a voltage droop across the hold capacitor, and subsequently degrade performance. ACQUISITION STARTS CONVERSION STARTS ACQUISITION ENDS CLK tCWS WR ACQMOD = "0" tCWH WR GOES HIGH WHEN CLK IS HIGH ACQUISITION ENDS ACQUISITION STARTS CONVERSION STARTS CLK WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS LOW Figure 8a. External Clock and WR Timing (Internal Acquisition Mode) ACQUISITION ENDS ACQUISITION STARTS CONVERSION STARTS CLK tCWS tDH WR ACQMOD = "0" ACQMOD = "1" WR GOES HIGH WHEN CLK IS HIGH ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWH tDH WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW ACQMOD = "0" Figure 8b. External Clock and WR Timing (External Acquisition Mode) 12 ______________________________________________________________________________________ Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface Power-On Reset At power-up, the internal power-supply circuitry sets INT high and puts the device in normal operation/external clock mode. This state is selected to keep the internal clock from loading the external clock driver when the part is used in external clock mode. Internal or External Reference The MAX197 can operate with either an internal or an external reference. An external reference can be connected to either the REF pin or to the REFADJ pin (Figure 9). To use the REF input directly, disable the internal buffer by tying REFADJ to VDD. Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01µF capacitor to AGND. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at the REF pin from a 2.5V reference. external reference at REF must be able to deliver 400µA DC load currents, and must have an output impedance of 10Ω or less. If the reference has higher input impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor to AGND. With an external reference voltage of less than 4.096V at the REF pin or less than 2.5V at the REFADJ pin, the increase in the ratio of the RMS noise to the LSB value (FS / 4096) results in performance degradation (loss of effective bits). REF VDD AV = 1.638 Internal Reference The internally trimmed 2.50V reference is gained through the REFADJ buffer to provide 4.096V at REF. Bypass the REF pin with a 4.7µF capacitor to AGND and the REFADJ pin with a 0.01µF capacitor to AGND. The internal reference voltage is adjustable to ±1.5% (±65 LSBs) with the reference-adjust circuit of Figure 1. REF MAX197 2.5V Figure 9b. External Reference, Reference at REF REF AV = 1.638 4.7µF CREF REFADJ 25 0.01µF 2.5V Figure 9a. Internal Reference 26 MAX197 AV = 1.638 REFADJ 10k 25 10k 26 4.7µF CREF 4.096V 4.7µF CREF REFADJ External Reference At REF and REFADJ, the input impedance is a minimum of 10kΩ for DC currents. During conversions, an 26 MAX197 25 2.5V 0.01µF 10k 2.5V Figure 9c. External Reference, Reference at REFADJ ______________________________________________________________________________________ 13 MAX197 __________Applications Information MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface Power-Down Mode To save power, you can put the converter into lowcurrent shutdown mode between conversions. Two programmable power-down modes are available, in addition to a hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte. When software power-down is asserted, it becomes effective only after the end of conversion. In all power-down modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes. The device returns to normal operation on the first WR falling edge during write operation. For hardware-controlled (FULLPD) power-down, pull the SHDN pin low. When hardware shutdown is asserted, it becomes effective immediately and the conversion is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7µF capacitor at the REF pin. This is a “DC” state that does not degrade after power-down of any duration. Therefore, you can use any sampling rate with this mode, without regard to start-up delays. However, in FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF and AGND to maintain the reference voltage between conversion and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate and add 50µs for settling time. Throughput rates of 10ksps offer typical supply currents of 470µA, using the recommended 33µF capacitor value. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX197 down after each conversion without requiring any start-up time on the next conversion. OUTPUT CODE OUTPUT CODE FULL-SCALE TRANSITION 11... 111 FS 1 LSB = 4096 1 LSB = 011... 111 011... 110 11... 110 11... 101 000... 001 000... 000 111... 111 00... 011 100... 010 00... 010 100... 001 00... 001 100... 000 00... 000 0 1 2 FS 3 INPUT VOLTAGE (LSB) Figure 10. Unipolar Transfer Function 14 FS - 3/2 LSB -FS 0V INPUT VOLTAGE (LSB) Figure 11. Bipolar Transfer Function ______________________________________________________________________________________ +FS - 1 LSB 2FS 4096 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface Layout, Grounding, and Bypassing Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Digital ground lines can run between digital signal lines to minimize interference. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1µF and 4.7µF capacitors to AGND to minimize high- and low-frequency fluctuations. If the supply is excessively noisy, connect a 5Ω resistor between the supply and V DD , as shown in Figure 12. _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX197AENI -40°C to +85°C 28 Narrow Plastic DIP MAX197BENI MAX197AEWI MAX197BEWI MAX197AEAI MAX197BEAI MAX197AMYI MAX197BMYI -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Narrow Ceramic SB** 28 Narrow Ceramic SB** ** Contact factory for availability and processing to MIL-STD-883. ___________________Chip Topography WR CLK V DD CS DGND V CC REF RD REFADJ HBEN INT SHDN D7 CH7 0.231" (5.870mm) CH6 SUPPLY CH5 GND +5V D6 CH4 D5 D4 4.7µF R* = 5Ω CH3 D3 CH2 0.1µF ** D1 D2 VDD AGND DGND +5V MAX197 DGND DIGITAL CIRCUITRY CH0 D0 AGND CH1 0.144" (3.659mm) TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED TO GND * OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE Figure 12. Power-Supply Grounding Connection ______________________________________________________________________________________ 15 MAX197 Transfer Function Output data coding for the MAX197 is binary in unipolar mode with 1LSB = (FS / 4096) and twos-complement binary in bipolar mode with 1LSB = ((2 x |FS|) / 4096). Code transitions occur halfway between successive-integer LSB values. Figures 10 and 11 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, refer to Table 1. MAX197 Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface _________________________________________________________Functional Diagram REF CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 REFADJ AV = 1.638 SIGNAL CONDITIONING BLOCK & OVERVOLTAGE TOLERANT MUX 10k +2.5V REFERENCE T/H CHARGE REDISTRIBUTION 12-BIT DAC COMP 12 SUCCESSIVEAPPROXIMATION REGISTER CLK CS WR RD SHDN CLOCK CONTROL LOGIC & LATCHES 4 8 4 8 MUX 8 8 THREE-STATE, BIDIRECTIONAL I/O INTERFACE INT HBEN MAX197 VDD AGND DGND D0–D7 8-BIT DATA BUS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.