LT1969 Dual 700MHz, 200mA, Adjustable Current Operational Amplifier U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 700MHz Gain Bandwidth ±200mA Minimum IOUT Adjustable Quiescent Current Low Distortion: –72dBc at 1MHz, 4VP-P, 25Ω, AV = 2 Stable in AV ≥ 10, Simple Compensation for AV < 10 ±4.3V Minimum Output Swing, VS = ±6V, RL = 25Ω Stable with 1000pF Load 6nV/√Hz Input Noise Voltage 2pA/√Hz Input Noise Current 4mV Maximum Input Offset Voltage 4µA Maximum Input Bias Current 400nA Maximum Input Offset Current ±4.5V Minimum Input CMR, VS = ±6V Specified at ±6V, ±2.5V U APPLICATIO S ■ ■ ■ ■ DSL Modems xDSL PCI Cards USB Modems Line Drivers The LT®1969 is an adjustable current version of the popular LT1886, a 200mA minimum output current, dual op amp with outstanding distortion performance. The adjustable current feature is highly desirable in applications where minimum power dissipation is required while still being able to provide adequate line termination. At nominal supply current, the amplifiers are gain of 10 stable and can easily be compensated for lower gains. The LT1969 features balanced high impedance inputs with 4µA input bias current and 4mV maximum input offset voltage. Single supply applications are easy to implement and have lower total noise than current feedback amplifier implementations. The output drives a 25Ω load to ±4.3V with ±6V supplies. On ±2.5V supplies, the output swings ±1.5V with a 100Ω load. The amplifier is stable with a 1000pF capacitive load making it useful in buffer and cable driver applications. The LT1969 is manufactured on Linear Technology’s advanced low voltage complementary bipolar process and is available in a thermally enhanced MS10 package , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Single 12V Supply ADSL Modem Line Driver 12V ADSL Modem Line Driver Distortion 0.1µF –60 + 1/2 LT1969 – 909Ω 10k 20k *COILCRAFT X8390-A OR EQUIVALENT 1:2* 100Ω 100Ω 1µF 10k 20k 1µF 100Ω 909Ω CTRL1 CTRL2 – 6 7 12.4Ω 0.1µF IN – 1/2 LT1969 + VS = 12V AV = 10 f = 200kHz 100Ω LINE 1:2 TRANSFORMER 12.4Ω 13k 49.9k IQ ON = 14mA IQ LOW POWER = 2mA IQ STANDBY = 600µA STANDBY ON LOGIC OUTPUT STANDBY LOW POWER ON HARMONIC DISTORTION (dBc) IN + –70 HD2 –80 –90 –100 HD3 0 2 4 6 8 10 12 LINE VOLTAGE (VP-P) 14 16 1969 TA01b 1969 TA01a 1 LT1969 U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) Total Supply Voltage (V + to V –) ........................... 13.2V Input Current (Note 2) ....................................... ±10mA Input Voltage (Note 2) ............................................ ±VS Maximum Continuous Output Current (Note 3) DC ............................................................... ±100mA AC ............................................................... ±300mA Operating Temperature Range (Note 10) – 40°C to 85°C Specified Temperature Range (Note 9) .. – 40°C to 85°C Maximum Junction Temperature ......................... 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW V+ OUTA –INA +INA V– 1 2 3 4 5 10 9 8 7 6 OUTB –INB +INB CTRL2 CTRL1 LT1969CMS MS10 PART MARKING MS10 PACKAGE 10-LEAD PLASTIC MSOP LTTN TJMAX = 150°C, θJA = 110°C/W (NOTE 4) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±6V, VCM = 0V, nominal mode with a 13k resistor from CTRL1 to V – and a 49.9k resistor from CTRL2 to V –, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 5) MIN TYP MAX 1 4 5 mV mV ● Input Offset Voltage Drift IOS (Note 8) ● Input Offset Current 3 17 µV/°C 150 400 600 nA nA 1.5 4 6 µA µA ● IB Input Bias Current ● en Input Noise Voltage f = 10kHz in Input Noise Current f = 10kHz RIN Input Resistance VCM = ±4.5V Differential CIN Input Capacitance PSRR AVOL 2 pA/√Hz MΩ kΩ 2 pF ● ● 4.5 5.9 – 5.2 VCM = ±4.5V ● 77 98 Minimum Supply Voltage Guaranteed by PSRR ● Power Supply Rejection Ratio VS = ±2V to ±6.5V 86 ● 80 78 dB dB 5.0 4.5 12 ● V/mV V/mV 4.5 4.0 12 ● V/mV V/mV 4.85 4.70 5 ● ±V ±V 4.30 4.10 4.6 ● ±V ±V 4.30 4.10 4.5 ● ±V ±V Common Mode Rejection Ratio Large-Signal Voltage Gain VOUT = ±4V, RL = 100Ω Output Swing RL = 100Ω, 10mV Overdrive RL = 25Ω, 10mV Overdrive IOUT = 200mA, 10mV Overdrive 2 nV/√Hz 10 35 VOUT = ±4V, RL = 25Ω VOUT 6 5 Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR UNITS – 4.5 V V dB ±2 V LT1969 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±6V, VCM = 0V, nominal mode with a 13k resistor from CTRL1 to V – and a 49.9k resistor from CTRL2 to V –, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS ISC Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) (Note 3) SR Slew Rate AV = –10 (Note 6) Full Power Bandwidth 4V Peak (Note 7) GBW Gain Bandwidth f = 1MHz tr, tf Rise Time, Fall Time AV = 10, 10% to 90% of 0.1V, RL = 100Ω Overshoot AV = 10, 0.1V, RL = 100Ω 1 % Propagation Delay AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100Ω 2.5 ns Settling Time 6V Step, 0.1% 50 ns Harmonic Distortion HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω –75/–63 –85/–71 dBc dBc IMD Intermodulation Distortion AV = 10, f = 0.9MHz, 1MHz, 14dBm, RL = 100Ω/25Ω –81/–80 dBc ROUT Output Resistance AV = 10, f = 1MHz IS Supply Current Per Amplifier CTRL1 Voltage 13k to V –, Measured with Respect to tS MIN 100 TYP mA mA 200 V/µs 8 MHz 700 MHz 4 Minimum Supply Current Ω 7 8.25 8.50 mA mA 0.77 0.74 0.97 ● 1.25 1.30 V V 0.87 0.80 1.05 ● 1.18 1.25 V V 300 800 1100 µA µA 49.9k to V –, Measured with Respect to V – per Amplifier; CTRL1, CTRL2 Open ● Maximum Supply Current ns 0.1 V– UNITS 700 500 ● CTRL2 Voltage MAX per Amplifier; CTRL1 or CTRL2 Shorted to V – 13 mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±2.5V, VCM = 0V, nominal mode with a 13k resistor from CTRL1 to V – and a 49.9k resistor from CTRL2 to V –, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 5) MIN TYP MAX 1.5 5 6 mV mV 5 17 µV/°C 100 350 550 nA nA 1.2 3.5 5.5 µA µA ● Input Offset Voltage Drift IOS (Note 8) ● Input Offset Current ● IB Input Bias Current ● UNITS en Input Noise Voltage f = 10kHz 6 nV/√Hz in Input Noise Current f = 10kHz 2 pA/√Hz RIN Input Resistance VCM = ±1V Differential 20 50 MΩ kΩ CIN Input Capacitance 2 pF Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR Common Mode Rejection Ratio VCM = ±1V 10 ● ● 1 ● 75 2.4 –1.7 91 –1 V V dB 3 LT1969 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±2.5V, VCM = 0V, nominal mode with a 13k resistor from CTRL1 to V – and a 49.9k resistor from CTRL2 to V –, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS AVOL Large-Signal Voltage Gain VOUT = ±1V, RL = 100Ω MIN TYP 5.0 4.5 10 ● V/mV V/mV 4.5 4.0 10 ● V/mV V/mV 1.50 1.40 1.65 ● ±V ±V 1.35 1.25 1.50 ● ±V ±V 0.87 0.80 1 ● ±V ±V 500 400 mA mA VOUT = ±1V, RL = 25Ω VOUT Output Swing RL = 100Ω, 10mV Overdrive RL = 25Ω, 10mV Overdrive IOUT = 200mA, 10mV Overdrive (Note 3) MAX UNITS ISC Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) SR Slew Rate AV = –10 (Note 6) 100 V/µs Full Power Bandwidth 1V Peak (Note 7) 16 MHz GBW Gain Bandwidth f = 1MHz 530 MHz tr, tf Rise Time, Fall Time AV = 10, 10% to 90% of 0.1V, RL = 100Ω 7 ns Overshoot AV = 10, 0.1V, RL = 100Ω 5 % Propagation Delay AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100Ω 5 ns Harmonic Distortion HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω –75/– 64 – 80/– 66 dBc dBc IMD Intermodulation Distortion AV = 10, f = 0.9MHz, 1MHz, 5dBm, RL = 100Ω/25Ω – 77/– 85 dBc ROUT Output Resistance AV = 10, f = 1MHz Channel Separation VOUT = ±1V, RL = 25Ω 50 ● IS Supply Current 82 80 Per Amplifier 0.2 Ω 92 dB dB 5 6.00 6.25 mA mA ● CTRL1 Voltage CTRL2 Voltage Minimum Supply Current 13k to V –, Measured with Respect to V– 0.77 0.74 0.95 ● 1.25 1.30 V V 0.87 0.80 1.03 ● 1.18 1.25 V V 250 650 750 µA µA 49.9k to V –, Measured with Respect to V– per Amplifier; CTRL1, CTRL2 Open ● Maximum Supply Current per Amplifier; CTRL1 or CTRL2 Shorted to V – Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to the device. θJA is specified for a 2500mm2 test board covered with 2 oz copper on both sides. Note 5: Input offset voltage is exclusive of warm-up drift. 4 11.5 mA Note 6: Slew rate is measured between ±2V on a ±4V output with ±6V supplies, and between ±1V on a ±1.5V output with ±2.5V supplies. Falling slew rate is guaranteed by correlation to rising slew rate. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/2πVP. Note 8: This parameter is not 100% tested. Note 9: The LT1969C is guaranteed to meet specified performance from 0°C to 70°C. The LT1969C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. Note 10: The LT1969C is guaranteed functional over the operating temperature range of –40°C to 85°C. LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS – – 13k resistor from CTRL1 to V and a 49.9k resistor from CTRL2 to V V+ 20 3.0 –0.1 12 VS = ±2.5V 10 8 6 4 –0.2 –0.3 1.5 1.0 0.5 2 50 25 0 75 TEMPERATURE (°C) 100 V– 125 2 4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V) INPUT VOLTAGE NOISE (nV/√Hz) INPUT BIAS CURRENT (µA) 2.0 1.5 VS = ±6V 1.0 VS = ±2.5V 50 25 75 0 TEMPERATURE (°C) 100 10 10 en in 1 10 100 OUTPUT SHORT-CIRCUIT CURRENT (mA) RL = 100Ω –1.0 150mA 200mA –1.5 1.5 200mA 1.0 150mA V– –50 –25 RL = 100Ω 50 25 75 0 TEMPERATURE (°C) 1.5 100 125 1969 G45 200mA 1.0 RL = 100Ω 150mA 0.5 Output Short-Circuit Current vs Temperature VS = ±2.5V 200mA 150mA –1.5 50 25 75 0 TEMPERATURE (°C) 100 Settling Time vs Output Step 6 VS = ±6V 900 SOURCE VS = ±6V 800 700 600 4 SOURCE VS = ±2.5V 500 400 300 200 SINK VS = ±6V SINK VS = ±2.5V 10mV 1mV 10mV 1mV 2 0 –2 –4 100 0 –50 –25 125 1969 G44 1000 –0.5 RL = 100Ω –1.0 1969 G04 Output Saturation Voltage vs Temperature + VS = ±6V –0.5 V– –50 –25 1 100k 1k 10k FREQUENCY (Hz) 1969 G43 0.5 V+ 100 TA = 25°C AV = 101 125 6 1969 G03 INPUT CURRENT NOISE (pA/√Hz) 2.5 –4 –2 0 2 4 INPUT COMMON MODE VOLTAGE (V) Output Saturation Voltage vs Temperature 100 3.0 V –6 14 Input Noise Spectral Density IB = (IB+ – IB–)/2 0 –50 –25 VS = ±2.5V 1.0 1969 G02 Input Bias Current vs Temperature 0.5 VS = ±6V 1.5 0 0 1969 G01 3.5 2.0 0.5 TA = 25°C ∆VOS > 1mV OUTPUT SATURATION VOLTAGE (V) 14 2.5 INPUT BIAS CURRENT (µA) VS = ±6V OUTPUT STEP (V) 16 0 –50 –25 OUTPUT SATURATION VOLTAGE (V) TA = 25°C IB = (IB + + IB –)/2 18 COMMON MODE RANGE (V) SUPPLY CURRENT, BOTH AMPLIFIERS (mA) Input Bias Current vs Input Common Mode Voltage Input Common Mode Range vs Supply Voltage Supply Current vs Temperature 50 25 0 75 TEMPERATURE (°C) 100 125 1969 G46 –6 0 10 20 30 40 SETTLING TIME (ns) 50 60 1886 G05 5 LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS – – 13k resistor from CTRL1 to V and a 49.9k resistor from CTRL2 to V Gain Bandwidth vs Supply Voltage 80 100 70 80 60 60 VS = ±2.5V 50 40 VS = ±6V 40 20 30 0 20 VS = ±2.5V –20 10 GAIN –40 0 –10 –20 –60 TA = 25°C AV = –10 RL = 100Ω 1M PHASE (DEG) GAIN (dB) VS = ±6V 800 TA = 25°C AV = –10 RL = 1k 700 GAIN BANDWIDTH (MHz) PHASE Output Impedance vs Frequency 100 600 RL = 100Ω 500 RL = 25Ω OUTPUT IMPEDANCE (Ω) Gain and Phase vs Frequency 400 10 AV = 100 1 0.1 AV = 10 –80 10M 100M FREQUENCY (Hz) –100 1G 300 0 2 4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V) 0.01 100k 14 1M 10M FREQUENCY (Hz) 1969 G06 1969 G08 1969 G07 Frequency Response vs Supply Voltage, AV = 10 23 22 23 22 21 9 TA = 25°C AV = –10 RL = 100Ω 8 6 19 5 VS = ±6V VS = ±2.5V 16 VS = ±6V 18 17 VS = ±2.5V 16 15 15 14 14 13 1M 13 1M 10M 100M FREQUENCY (Hz) 1G 0 3 38 2 35 VS = ±2.5V 29 VS = ±6V GAIN (dB) GAIN (dB) 32 –2 –3 –4 –5 –6 TA = 25°C AV = –1 RL = 100Ω RF = RG = 1k RC = 124Ω CC = 100pF SEE FIGURE 2 –7 1M 10M 100M FREQUENCY (Hz) 26 23 Power Supply Rejection vs Frequency 100 500pF 200pF 100pF 50pF 20 14 11 1G 8 1M VS = ±6V AV = 10 90 1000pF 17 1969 G12 6 VS = ±6V TA = 25°C AV = 10 NO RL 1G 1969 G11 Frequency Response vs Capacitive Load –1 10M 100M FREQUENCY (Hz) 1969 G10 Frequency Response vs Supply Voltage, AV = –1 0 TA = 25°C AV = 2 RL = 100Ω RF = RG = 1k RC = 124Ω CC = 100pF SEE FIGURE 3 –1 1M 1G 1969 G09 1 3 1 10M 100M FREQUENCY (Hz) VS = ±6V 4 2 POWER SUPPLY REJECTION (dB) 17 GAIN (dB) 20 19 18 VS = ±2.5V 7 20 GAIN (dB) GAIN (dB) 21 Frequency Response vs Supply Voltage, AV = 2 Frequency Response vs Supply Voltage, AV = –10 TA = 25°C AV = 10 RL = 100Ω 100M 80 70 (–) SUPPLY 60 50 40 30 (+) SUPPLY 20 10 10M 100M FREQUENCY (Hz) 1G 1969 G13 0 100k 1M 10M FREQUENCY (Hz) 100M 1969 G14 LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS – – 13k resistor from CTRL1 to V and a 49.9k resistor from CTRL2 to V Common Mode Rejection Ratio vs Frequency 90 80 70 60 50 40 30 20 10 0 100k 1M 10M FREQUENCY (Hz) 100M 0 0 VS = ±6V AV = 10 RL = 100Ω INPUT = –20dBm –10 –20 –20 –30 –40 –50 B→A –60 –70 –80 A→B –90 –100 1M 10M 100M FREQUENCY (Hz) Harmonic Distortion vs Frequency, AV = 10, VS = ±2.5V RL = 25Ω –60 2nd 2nd 3rd –70 3rd –80 –90 –30 –40 –50 –60 2nd –70 –30 –40 –50 –60 10 100 LOAD RESISTANCE (Ω) 1k 1 0 TA = 25°C f = 1MHz –10 –30 –80 2nd –90 3rd –40 RL = 25Ω –60 2nd –70 3rd –80 2nd –90 RL = 100Ω –100 DISTORTION (dBc) –20 –30 DISTORTION (dBc) –20 3rd 3rd 2 4 6 8 10 OUTPUT VOLTAGE (VP-P) 12 1969 G21 –40 –50 RL = 25Ω –60 –70 2nd –80 2nd 3rd –100 0 1 2 3 4 OUTPUT VOLTAGE (VP-P) 5 1969 G22 RL = 100Ω 3rd –90 RL = 100Ω –100 0 TA = 25°C RF = RG = 1k RC = 124Ω CC = 100pF f = 1MHz SEE FIGURE 3 –10 –30 –50 1k Harmonic Distortion vs Output Swing, AV = 2, VS = ±6V –20 2nd 10 100 LOAD RESISTANCE (Ω) 1969 G20 0 TA = 25°C f = 1MHz –70 3rd 1969 G19 0 –60 2nd –70 Harmonic Distortion vs Output Swing, AV = 10, VS = ±2.5V RL = 25Ω TA = 25°C VS = ±2.5V AV = 10 2VP-P OUT f = 1MHz –100 1 Harmonic Distortion vs Output Swing, AV = 10, VS = ±6V –50 10M –90 –100 10M –40 RL = 100Ω 1M FREQUENCY (Hz) –80 3rd 1969 G18 –10 3rd –20 –90 1M FREQUENCY (Hz) 2nd –90 –10 –80 RL = 100Ω –100 100k –80 1969 G17 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) –50 –70 0 –20 –40 3rd RL = 25Ω –60 Harmonic Distortion vs Resistive Load TA = 25°C VS = ±6V AV = 10 2VP-P OUT f = 1MHz –10 –30 2nd –50 –100 100k 0 –20 –40 Harmonic Distortion vs Resistive Load TA = 25°C AV = 10 2VP-P OUT –10 DISTORTION (dBc) 1G –30 1969 G16 1969 G15 0 TA = 25°C AV = 10 2VP-P OUT –10 DISTORTION (dBc) VS = ±6V TA = 25°C OUTPUT TO INPUT CROSSTALK (dB) COMMON MODE REJECTION RATIO (dB) 100 Harmonic Distortion vs Frequency, AV = 10, VS = ±6V Amplifier Crosstalk vs Frequency 0 2 4 6 8 10 OUTPUT VOLTAGE (VP-P) 12 1969 G23 7 LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS Harmonic Distortion vs Output Swing, AV = 2, VS = ±2.5V –30 –40 –50 –60 RL = 25Ω –70 2nd 3rd 2nd –80 –90 RL = 100Ω 3rd –100 0 TA = 25°C AV = 10 f = 1MHz –40 RL = 5Ω –50 RL = 10Ω –60 RL = 25Ω –70 2 3 4 OUTPUT VOLTAGE (VP-P) 5 1400 RL = 25Ω –70 200 300 400 100 PEAK OUTPUT CURRENT (mA) 8 TA = 25°C AV = 10 RL = 100Ω 1% DISTORTION VS = ±2.5V 4 0 500 2 1M FREQUENCY (Hz) VS = ±6V AV = –10 1200 800 600 400 0 78 77 8 6 10 4 ICC, PER AMPLIFIER (mA) 2 75 12 100 VS = ±6V OUTPUT IMPEDANCE (Ω) 150 100 100 10 f = 1MHz 1 f = 600kHz 0.1 12 Output Impedance vs Frequency Low Power ** VS = ±6V AV = 10 350 FALLING 10 4 6 8 ICC, PER AMPLIFIER (mA) 2 1969 G29 Output Impedance vs Supply Current RISING 0 1959 G28 Slew Rate vs Supply Current 200 79 76 200 1969 G27 250 VS = ±6V MEASURED AT AV = –10 80 1000 10M 300 250 Phase Margin vs Supply Current 81 0 0 100k 100 150 200 50 PEAK OUTPUT CURRENT (mA) 1969 G26 PHASE MARGIN VS = ±6V GAIN BANDWIDTH PRODUCT (MHz) OUTPUT VOLTAGE SWING (VP-P) RL = 10Ω –60 Gain Bandwidth Product vs Supply Current 12 400 –50 1969 G25 Undistorted Output Swing vs Frequency 6 RL = 5Ω –80 0 1969 G24 10 TA = 25°C AV = 10 f = 1MHz –40 –80 1 OUTPUT IMPEDANCE (Ω) –20 HIGHEST HARMONIC DISTORTION (dBc) –10 DISTORTION (dBc) –30 –30 TA = 25°C RF = RG = 1k RC = 124Ω CC = 100pF f = 1MHz SEE FIGURE 3 HIGHEST HARMONIC DISTORTION (dBc) 0 SLEW RATE (V/µs) Harmonic Distortion vs Output Current, VS = ±2.5V Harmonic Distortion vs Output Current, VS = ±6V VS = ±6V 10 1 AV = 100 AV = 10 0.1 50 0.01 0 0 1 8 10 6 4 ICC, PER AMPLIFIER (mA) 2 12 1969 G30 8 0 1 2 3 4 5 6 7 8 ICC PER AMPLIFIER (mA) 9 10 1969 G31 0.01 100k 1M 10M FREQUENCY (Hz) 100M 1969 G32 LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum IOUT Sourcing vs Quiescent Current Small-Signal Transient, AV = 10, Nominal Power* 800 MAXIMUM IOUT (mA) VS = ±6V SHORT-CIRCUIT CURRENT 700 Small-Signal Transient, AV = –10, Nominal Power* 600 LINEAR OUTPUT CURRENT REGION 500 400 300 200 1969 G34 100 0 0 1 4 5 2 3 6 ICC PER AMPLIFIER (mA) 7 1969 G35 8 1969 G33 Small-Signal Transient, AV = 10, CL = 1000pF, Nominal Power* Large-Signal Transient, AV = 10, Nominal Power* 1969 G36 Large-Signal Transient, AV = –10, Nominal Power* 1969 G38 1969 G37 Large-Signal Transient, AV = 10, CL = 1000pF, Nominal Power* 1969 G39 Small-Signal Transient, AV = 10, CL = 1000pF, Low Power** 1969 G40 *13k RESISTOR FROM CTRL1 TO V – AND A 49.9k RESISTOR FROM CTRL2 TO V – ** 49.9k RESISTOR FROM CTRL2 TO V –, CTR1 FLOATING 9 LT1969 U W TYPICAL PERFOR A CE CHARACTERISTICS Large-Signal Transient, AV = 10, Low Power** Large-Signal Transient, AV = – 10, Low Power** 1969 G42 1969 G41 *13k RESISTOR FROM CTRL1 TO V – AND A 49.9k RESISTOR FROM CTRL2 TO V – ** 49.9k RESISTOR FROM CTRL2 TO V –, CTR1 FLOATING U W U U APPLICATIO S I FOR ATIO Input Considerations The inputs of the LT1969 are an NPN differential pair protected by back-to-back diodes (see the Simplified Schematic). There are no series protection resistors onboard which would degrade the input voltage noise. If the inputs can have a voltage difference of more than 0.7V, the input current should be limited to less than 10mA with external resistance (usually the feedback resistor or source resistor). Each input also has two ESD clamp diodes—one to each supply. If an input drive exceeds the supply, limit the current with an external resistor to less than 10mA. The LT1969 design is a true operational amplifier with high impedance inputs and low input bias currents. The input offset current is a factor of ten lower than the input bias current. To minimize offsets due to input bias currents, match the equivalent DC resistance seen by both inputs. The low input noise current can significantly reduce total noise compared to a current feedback amplifier, especially for higher source resistances. Layout and Passive Components With a gain bandwidth product of 700MHz the LT1969 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and 10 a combination of RF-quality supply bypass capacitors (i.e., 470pF and 0.1µF). As the primary applications have high drive current, use low ESR supply bypass capacitors (1µF to 10µF). For best distortion performance with high drive current a capacitor with the shortest possible trace lengths should be placed between Pins 1 and 5. The optimum location for this capacitor is on the back side of the PC board. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause frequency peaking. In general, use feedback resistors of 1kΩ or less. Thermal Issues The LT1969 enhanced θJA MS10 package has the V– pin fused to the lead frame. This thermal connection increases the efficiency of the PC board as a heat sink. The PCB material can be very effective at transmitting heat between the pad area attached to the V– pin and a ground or power plane layer. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by the device. Table 1 lists the thermal resistance for several different board sizes and copper areas. All measurements LT1969 U W U U APPLICATIO S I FOR ATIO As an example, calculate the junction temperature for the circuit in Figure 1 assuming an 70°C ambient temperature. were taken in still air on 3/32" FR-4 board with 2oz copper. This data can be used as a rough guideline in estimating thermal resistance. The thermal resistance for each application will be affected by thermal interactions with other components as well as board size and shape. The device dissipation can be found by measuring the supply currents, calculating the total dissipation and then subtracting the dissipation in the load. Table 1. Fused 10-Lead MSOP Package COPPER AREA TOPSIDE* BACKSIDE (mm 2) (mm 2) The dissipation for the amplifiers is: BOARD AREA (mm 2) THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 540 540 2500 110°C/W 100 100 2500 120°C/W 100 0 2500 130°C/W 30 0 2500 135°C/W 0 0 2500 140°C/W PD = (63.5mA)(12V) – (4V/√2)2/(50) = 0.6W The total package power dissipation is 0.6W. When a 2500 sq. mm PC board with 540 sq. mm of 2oz copper on top and bottom is used, the thermal resistance is 110°C/W. The junction temperature TJ is: TJ = (0.6W)(110°C/W) + 70°C = 136°C The maximum junction temperature for the LT1969 is 150°C so the heat sinking capability of the board is adequate for the application. *Device is mounted on topside. Calculating Junction Temperature The junction temperature can be calculated from the equation: If the copper area on the PC board is reduced to 0 sq. mm the thermal resistance increases to 140°C/W and the junction temperature becomes: TJ = (PD)(θJA) + TA TJ = Junction Temperature TA = Ambient Temperature PD = Device Dissipation θJA = Thermal Resistance (Junction-to-Ambient) TJ = (0.6W)(140°C/W) + 70°C = 154°C which is above the maximum junction temperature indicating that the heat sinking capability of the board is inadequate and should be increased. 6V + – 909Ω 4V 100Ω 50Ω 1K –4V f = 1MHz CTRL1 CTRL2 6 7 13k –6V 49.9k –6V 100Ω – + –6V 1969 F01 Figure 1. Thermal Calculation Example 11 LT1969 U W U U APPLICATIO S I FOR ATIO Capacitive Loading Compensation The LT1969 is stable with a 1000pF capacitive load. The photo of the small-signal response with 1000pF load in a gain of 10 shows 50% overshoot. The photo of the largesignal response with a 1000pF load shows that the output slew rate is not limited by the short-circuit current. The Typical Performance Curve of Frequency Response vs Capacitive Load shows the peaking for various capacitive loads. The LT1969 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure␣ 2 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by RC and CC should be less than 15MHz to minimize peaking. The Typical Curve of Frequency Response vs Supply Voltage, AV = –1 shows less than 1dB of peaking for a break frequency of 12.8MHz. This stability is useful in the case of directly driving a coaxial cable or twisted pair that is inadvertently unterminated. For best pulse fidelity, however, a termination resistor of value equal to the characteristic impedance of the cable or twisted pair (i.e., 50Ω/75Ω/100Ω/135Ω) should be placed in series with the output. The other end of the cable or twisted pair should be terminated with the same value resistor to ground. Figure 3 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the RF RG Vo – Vi RC CC (OPTIONAL) = Vi Vo + –RF RG (RC || RG) ≤ RF/9 1 < 15MHz 2πRCCC 1969 F02 Figure 2. Compensation for Inverting Gains Vo + Vi RC CC (OPTIONAL) =1+ Vi Vo – (RC || RG) ≤ RF/9 1 RF RF RG < 15MHz 2πRCCC RG 1969 F03 Figure 3. Compensation for Noninverting Gains 12 LT1969 U W U U APPLICATIO S I FOR ATIO network is bootstrapped. This network can also be placed between the inverting input and an AC ground. Another compensation scheme for noninverting circuits is shown in Figure 4. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of Figures 3 and 4 can be combined as shown in Figure 5. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies. Output Loading The LT1969 output stage is very wide bandwidth and able to source and sink large currents. Reactive loading, even isolated with a back-termination resistor, can cause ringing at frequencies of hundreds of MHz. For this reason, any design should be evaluated over a wide range of output conditions. To reduce the effects of reactive loading, an Vi Vo + =1+ VO – RF RG = 1 (LOW FREQUENCIES) Vi RF optional snubber network consisting of a series RC across the load can provide a resistive load at high frequency. Another option is to filter the drive to the load. If a backtermination resistor is used, a capacitor to ground at the load can eliminate ringing. Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 6. The cable/line is terminated in its characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.). A back-termination resistor also equal to to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is + Vi (HIGH FREQUENCIES) RC CC RG ≤ RF/9 1 Vo – RG Vo RF 2πRGCC =1+ RG =1+ AT MEDIUM FREQUENCIES RF AT HIGH FREQUENCIES (RC || RG) 1969 F04 Figure 4. Alternate Noninverting Compensation Vi RF RG CBIG CC = 1 AT LOW FREQUENCIES Vi < 15MHz 1969 F05 Figure 5. Combination Compensation CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL + RBT VO – RL RF RBT = RL RG Vo Vi = 1 2 (1 + RF/RG) 1969 F06 Figure 6. Standard Cable/Line Back-Termination 13 LT1969 U W U U APPLICATIO S I FOR ATIO wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. Eliminating Vp, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n) For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 =␣ 12.3. Note that the overall gain is increased: RP2 / (RP2 + RP1) Vo = Vi (1+ 1 / n) / (1+ RF / RG ) − RP1 / (RP2 + RP1) An alternate method of back-termination is shown in Figure 7. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor of n. To analyze this circuit, first ground the input. As RBT␣ = RL/n, and assuming RP2>>RL we require that: [ Va = Vo (RF/RP) RP2 FOR RBT = + Vi Va RBT VP – Vo RL n RF ( )( RP1 RG RP1 + RP2 Vo 1 + 1/n 1+ ) 1 =1– n RP2/(RP2 + RP1) RL RF = Vi ( ) 1+ RP1 – RP2 + RP1 RF RG RG 1969 F07 Figure 7. Back-Termination Using Positive Feedback + Vi Va RBT Vo – FOR RBT = RF RG 1– RL RF RF 1+ Vo Vi – –Va = RF + RG RF RP ( ) 2 1– RF RP RBT + n RP RP –Vi RL 1 n= RL RP RG –Vo 1969 F08 Figure 8. Back-Termination Using Differential Positive Feedback 14 ] A simpler method of using positive feedback to reduce the back-termination is shown in Figure 8. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of –RF/RP from –Vo to Va Va = Vo (1 – 1/n) to increase the effective value of RBT by n. Vp = Vo (1 – 1/n)/(1 + RF/RG) Vo = Vp (1 + RP2/RP1) RP1 ] [ LT1969 U W U U APPLICATIO S I FOR ATIO Table 2. ADSL Upstream Driver Designs and assuming RP >> RL, we require STANDARD Va = Vo (1 – 1/n) solving Line Impedance 100Ω 100Ω Line Power 13dBm 13dBm 5.33 5.33 Peak-to-Average Ratio RF/RP = 1 – 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: Vo/Vi = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)] The LT1969 is an ideal choice for ADSL upstream (CPE) modems. The key advantages are: ±200mA output drive with only 1.7V worst-case total supply voltage headroom, high bandwidth, which helps achieve low distortion, low quiescent supply current of 7mA per amplifier and a space-saving, thermally enhanced MS10 package. An ADSL remote terminal driver must deliver an average power of 13dBm (20mW) into a 100Ω line. This corresponds to 1.41VRMS into the line. The DMT-ADSL peak-toaverage ratio of 5.33 implies voltage peaks of 7.53V into the line. Using a differential drive configuration and transformer coupling with standard back-termination, a transformer ratio of 1:2 is well suited. This is shown on the front page of this data sheet along with the distortion performance vs line voltage at 200kHz, which is beyond ADSL requirements. Note that the distortion is better than Vi Transformer Turns Ratio Reflected Impedance Back-Termination Resistors Transformer Insertion Loss ADSL Driver Requirements + LOW POWER 2 1 25Ω 100Ω 12.5Ω 8.35Ω 1dB 0.5dB Average Amplifier Swing 0.79VRMS 0.87VRMS Average Amplifier Current 31.7mARMS 15mARMS Peak Amplifier Swing 4.21V Peak 4.65V Peak Peak Amplifier Current 169mA Peak 80mA Peak 550mW 350mW Single 12V Single 12V Total Average Power Consumption Supply Voltage –73dBc for all swings up to 16VP-P into the line. The gain of this circuit from the differential inputs to the line voltage is 10. Lower gains are easy to implement using the compensation techniques of Figure 5. Table 2 shows the drive requirements for this standard circuit. The above design is an excellent choice for desktop applications and draws typically 550mW of power. For portable applications, power savings can be achieved by reducing the back-termination resistor using positive feedback as shown in Figure 9. The overall gain of this circuit 8.45Ω – 1k 1.21k 523Ω 1:1 100Ω 1µF 523Ω 1k 1.21k – 1969 F09 AV = 10 8.45Ω –Vi + Figure 9. Power Saving ADSL Modem Driver 15 LT1969 U W U U APPLICATIO S I FOR ATIO is also 10, but the power consumption has been reduced to 350mW, a savings of 36% over the previous design. Note that the reduction of the back-termination resistor has allowed use of a 1:1 transformer ratio. Table 2 compares the two approaches. It may seem that the low power design is a clear choice, but there are further system issues to consider. In addition to driving the line, the amplifiers provide back-termination for signals that are received simultaneously from the line. In order to reject the drive signal, a receiver circuit is used such as shown in Figure 10. Taking advantage of the differential nature of the signals, the receiver can subtract out the drive signal and amplify the received signal. This method works well for standard back-termination. If the backtermination resistors are reduced by positive feedback, a portion of the received signal also appears at the amplifier outputs. The result is that the received signal is attenuated by the same amount as the reduction in the back-termination resistor. Taking into account the different transformer turns ratios, the received signal of the low power design will be one third of the standard design received signal. The reduced signal has system implications for the sensitivity of the receiver. The power reduction may, or may not, be an acceptable system tradeoff for a given design. Controlling the Quiescent Current The quiescent current of the LT1969 is controlled via two control pins, CTRL1 and CTRL2. The pins can be used to either turn off the amplifiers, reducing the quiescent current on ±2.5V supplies to less than 500µA per amplifier, or to control the quiescent current in normal operation. Figure 11 shows how the control pins are used in conjunction with external resistors to program the supply current. In normal operation, each control pin is biased to approximately 1V above V – and by varying the resistor values, the current from each control pin can be adjusted. It is this current that sets the supply current of both amplifiers. If one of the resistors is open, i.e. R2, the supply current of the amplifiers will be set by CTRL1 and R1. Figure 12 shows supply current vs resistor value. RBT Va VL 1:n RL RBT –Va –VL RF – + RD RG RL LT1813 = REFLECTED IMPEDANCE n2 + RL VRX RL + – 2n2 VBIAS LT1813 – RF 2n2 = ATTENUATION OF Va + RBT RL RD RG SET RG RD = 2n2 RL 2n2 Figure 10. Receiver Configuration 16 + RBT 1969 F10 LT1969 U W U U APPLICATIO S I FOR ATIO V+ CTRL1 6 1 + CTRL2 7 R1 R2 OFF – CTRL1 6 R1 ON 5 CTRL2 7 V– V– V– 1969 F11 VS = ±6V TA = 25°C ICC, BOTH AMPLIFIERS (mA) 25 3.3V/5V FROM V – 1969 F13 ON Figure 13 R2 Figure 11 30 OFF 20 remains low, preserving the line termination. The Typical Performance Characteristics curve Output Impedance vs Supply Current shows the details. Both logic inputs high further reduces the supply current and places the part in a “standby” mode with less than 500µA per amplifier quiescent current. Output Loading in Low Current Modes 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 RESISTANCE (kΩ) 1969 F12 Figure 12. Supply Current vs Control Resistance (R1//R2) Using CTRL1 and CTRL2 to set the supply current effectively places R1 and R2 in parallel obtaining a net resistance, and Figure 12 can still be utilized in determining supply current. The use of two pins to control the supply current allows for applications where external logic can be used to place the amplifiers in different supply current modes. Figure 13 illustrates a partial shutdown with direct logic on each control pin. If both logic inputs are low, the control pins will effectively see a resistance of 13k//49.9k = 10k to V –. This will set the amplifiers in nominal mode with a gain bandwidth of 700MHz and ±200mA minimum IOUT. The electrical characteristics are specified in nominal mode. Forcing R1’s input logic high will partially shut down the part, putting it in a low power mode. By keeping the output stage slightly biased, the output impedance The LT1969 output stage has a very wide bandwidth and is able to source and sink large amounts of current. The internal circuitry of the output stage incorporates a positive feedback boost loop giving it high drive capability. As the supply current is reduced, the sourcing drive capability also reduces. Maximum sink current is independent of supply current and is limited by the short-circuit protection at 500mA. If the amplifier is in a low power or “standby” mode, the output stage is slightly biased and is not capable of sourcing high output currents. The Typical Performance Characteristics curve Maximum IOUT Sourcing vs Quiescent Current shows the maximum output current for a given quiescent current. Considerations for Fault Protection The basic line driver design presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current, 500mA or more, to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall 17 LT1969 U W U U APPLICATIO S I FOR ATIO system performance. If left unchecked, the high DC current can heat the LT1969 to destruction. Using DC blocking capacitors to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbsTM, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also 18 create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT1969 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. TransZorb is a registered trademark of General Instruments, GSI LT1969 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS10 Package 10-Lead Plastic MSOP (LTC DWG # 05-08-1661) 0.118 ± 0.004* (3.00 ± 0.102) 10 9 8 7 6 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) 1 2 3 4 5 0.034 (0.86) REF 0.043 (1.10) MAX 0.007 (0.18) 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.007 – 0.011 (0.17 – 0.27) 0.0197 (0.50) BSC 0.005 ± 0.002 (0.13 ± 0.05) MSOP (MS10) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1969 U TYPICAL APPLICATIO Split Supply ±5V ADSL CPE Line Driver 5V 4 130Ω 5V 1 + 3 BAV99** 6.19Ω 2 1/2 LT1969 –5V – 0.47µF** 1k 100pF + 1:2* 2k 866Ω + VIN 100Ω VL – 866Ω 100pF 9 0.47µF** – 1/2 LT1969 130Ω 8 – 2k 1k + 6.19Ω 10 5V 7 BAV99** 5 6 –5V 13k 49.9k –5V –5V –5V VL =5 *COILCRAFT X8390-A OR EQUIVALENT **SEE TEXT REGARDING FAULT PROTECTION 1969 TA02 (ASSUME 0.5dB TRANSFORMER POWER LOSS) VIN REFLECTED LINE IMPEDANCE = 100Ω / 22 = 25Ω EFFECTIVE TERMINATION = 2 • 6.19 • 2kΩ = 24.8Ω 1kΩ EACH AMPLIFIER: 0.56VRMS, 29.9mARMS ±3V PEAK, ±160mA PEAK RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1207 Dual 250mA, 60MHz Current Feedback Amplifier Shutdown/Current Set Function LT1396 Dual 400MHz, 800V/µs Current Feedback Amplifier 4.6mA Supply Current Set, 80mA IOUT LT1497 Dual 125mA, 50MHz Current Feedback Amplifier 900V/µs Slew Rate LT1795 Dual 500mA, 50MHz Current Feedback Amplifier Shutdown/Current Set Function, ADSL CO Driver LT1886 Dual 700MHz, 200mA Op Amp Gain of 10 Stable, Low Distortion 20 Linear Technology Corporation 1969f LT/TP 0301 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2001