1 GSPS Direct Digital Synthesizer w/ 14-bit DAC AD9912 Preliminary Technical Data FEATURES APPLICATIONS 1 GSPS internal clock speed (up to 400 MHz out directly) Integrated 1 GSPS 14-bit DAC 48-bit frequency tuning word Differential HSTL Comparator Flexible System Clock Input accepts either crystal or external reference clock. On-chip Low-Noise PLL REFCLK Multiplier 2 Spur Reduction Channels Low Jitter clock doubler for frequencies up to 750 MHz Single-ended CMOS Comparator; frequencies < 50MHz Programmable output divider for CMOS output Serial I/O control Excellent Dynamic Performance Software controlled power-down 64-lead LFCSP package Phase Noise @ 95MHz using Vectron VCC6 87.5MHz Oscillator: 100 Hz Offset: -103 dBc/Hz 10 kHz Offset: -133 dBc/Hz 1 MHz Offset: -136 dBc/Hz Agile LO frequency synthesis Low jitter, fine tune clock generation Test and measurement equipment Wireless Base Stations, Controllers Secure Communications Fast frequency hopping GENERAL DESCRIPTION The AD9912 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC. The AD9912 features a 48–bit frequency tuning word (FTW) which can synthesize frequencies in step sizes no larger than 4 uHz. Absolute frequency accuracy can be achieved by adjusting the DAC system clock. The AD9912 also features an integrated system clock PLL, which allows reference clocks as low as 25 MHz. The AD9912 operates over an industrial temperature range, spanning -40°C to +85°C. Figure 1: Basic Block Diagram Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved AD9912 Preliminary Technical Data 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SCLK SDIO SDO CSB IO_UPDATE RESET PWRDOWN N/C N/C S4 S3 AVDD AVSS IOUTB IOUT AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9912 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DAC_RSET AVDD3 AVDD3 AVDD N/C AVSS AVDD FDBK_IN FDBK_INB AVSS OUT_CMOS AVDD3 AVDD OUT OUTB AVSS N/C N/C AVDD N/C N/C N/C AVDD AVDD AVDD AVDD SYSCLK SYSCLKB AVDD AVDD LOOP_FILTER CLKMODESEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DVDD_I/O DVSS DVDD DVSS DVDD DVSS DVDD DVSS S1 S2 AVDD N/C N/C AVDD3 N/C N/C Figure 2: 64-Lead LFCSP Pin Configuration Table 2: Pin Function Descriptions Pin No. 1 2, 4, 6, 8 3, 5, 7 9, 10, 54, 55 11, 19, 2326, 29, 30, 36, 42, 45, 53 Input/ Output I I I I/O Pin Type Power Power Power 3.3V CMOS I Power Mnemonic Description DVDD_I/O DVSS DVDD S1, S2, S3, S4 3.3V I/O Digital Supply Digital Ground: Connect to Ground 1.8V Digital Supply Configurable startup strapping pins: These pins are configured under program control (see “Default Power-up Frequency Options for 1 GHz System Clock” on Page 21. After power-up, these pins become outputs. Analog Supply: Connect to a nominal 1.8V Supply AVDD Rev. PrB | Page 2 of 3 Preliminary Technical Data 12, 13, 15-18, 20, 21, 22, 44 14, 37, 46, 47, 49 27 28 31 N/C I Power I I AD9912 No Connect No Connect: These excess, unused pins should be left floating. AVDD3 Analog Supply: Connect to a nominal 3.3V supply SYSCLK SYSCLKB LOOP_FILTER System Clock Input. Can be LVPECL or Crystal input, depending on CLKMODESEL pin. Complementary System Clock: Complementary signal to the input provided on pin 27 System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the System Clock, an external loop filter must be constructed and attached to this pin. Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an oscillator or external clock source. (See the SysClk Inputs section for details on the use of this pin). Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection. 32 I 1.8V CMOS CLKMODESEL 33, 39, 43, 52 34 I GND AVSS O OUTB 35 O 38 O 1.8V HSTL 1.8V HSTL 3.3V CMOS 40 OUT Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND MULTIPLIER section, under sub heading Primary (Differential) Driver, for details HSTL Output: See specification table and the CLOCK DRIVERS section OUT_CMOS CMOS Output: See specification table and the CLOCK DRIVERS section I FDBK_INB 41 I FDBK_IN 48 O DAC_RSET 50 O IOUT 51 O IOUTB 56, 57 58 I 59 I 60 I 3.3V CMOS IO_UPDATE 61 I 3.3V CMOS CSB 62 O SDO 63 I/O 64 O 3.3V CMOS 3.3V CMOS 3.3V CMOS Complementary Feedback input: In standard operating mode, this pin is connected to the filtered IOUTB output . This internally biased input is typically AC-coupled, and when configured as such, can accept any differential signal. Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT output DAC output current setting resistor. Connect a resistor from this pin to GND . See the “DAC Output” section. DAC output: Output signal should be filtered and sent back on chip through FDBK_INB input Complimentary DAC output: Output signal should be filtered and sent back on chip through FDBK_IN input No Connect: These should be left floating. Power Down: When this active high pin is asserted, the device goes into full power down mode. Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon power up, a 10 us reset pulse is automatically generated when the power supplies reach a threshold and stabilize. I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port registers to the control registers (see the Write subsection of the General Operation of Serial Control Port section). Chip Select: Active low. When programming a device, this pin must be held low. In systems where more than one AD9549 is present this enables individual programming of each AD9549 Serial Data Output: When the device is in three wire mode, data is read on this pin 3.3V CMOS 3.3V CMOS No Connect PWRDOWN RESET SDIO SCLK Serial Data Input/Output: When the device is in three-wire mode, data is written via this pin. In 2 wire mode, data reads and writes both occur on this pin Serial Programming Clock: data clock for serial programming. Rev. PrB| Page 3 of 3 PR06763-0-6/07(PrB)