LINER LTC1407ACMSE

LTC1407/LTC1407A
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
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FEATURES
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DESCRIPTIO
3Msps Sampling ADC with Two Simultaneous
Differential Inputs
1.5Msps Throughput per Channel
Low Power Dissipation: 14mW (Typ)
3V Single Supply Operation
2.5V Internal Bandgap Reference with External
Overdrive
3-Wire Serial Interface
Sleep (10µW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection at 100kHz
0V to 2.5V Unipolar Input Range
Tiny 10-Lead MS Package
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APPLICATIO S
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The LTC®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
with two 1.5Msps simultaneously sampled differential
inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10µW.
The combination of speed, low power and tiny package
makes the LTC1407/LTC1407A suitable for high speed,
portable applications.
The LTC1407/LTC1407A contain two separate differential
inputs that are sampled simultaneously on the rising edge
of the CONV signal. These two sampled inputs are then
converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring
signals differentially from the source.
Telecommunications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
I & Q Demodulation
Industrial Control
The devices convert 0V to 2.5V unipolar inputs differentially. The absolute voltage swing for CH0+, CH0–, CH1+
and CH1– extends from ground to the supply voltage.
The serial interface sends out the two conversion results in
32 clocks for compatibility with standard serial interfaces.
, LTC and LT are registered trademarks of Linear Technology Corporation.
W
3V
CH0+
1
+
S&H
CH0–
2
–
MUX
CH1+
4
+
S&H
CH1–
5
3
10µF
–
GND
11
VDD
LTC1407A
–44
–50
–56
THREESTATE
SERIAL
OUTPUT
PORT
SDO
8
10
CONV
9
SCK
TIMING
LOGIC
VREF
6
3Msps
14-BIT ADC
THD, 2nd and 3rd
vs Input Frequency
THD, 2nd, 3rd (dB)
7
14-BIT LATCH
10µF
14-BIT LATCH
BLOCK DIAGRA
THD
2nd
–62
–68
–74
3rd
–80
–86
–92
–98
2.5V
REFERENCE
EXPOSED PAD
–104
0.1
1
10
FREQUENCY (MHz)
100
1407 G02
1407A BD
1407f
1
LTC1407/LTC1407A
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Analog Input Voltage
(Note 3) ................................... – 0.3V to (VDD + 0.3V)
Digital Input Voltage .................... – 0.3V to (VDD + 0.3V)
Digital Output Voltage .................. – 0.3V to (VDD + 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1407C/LTC1407AC ............................ 0°C to 70°C
LTC1407I/LTC1407AI ......................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
CH0 +
CH0 –
VREF
CH1+
CH1–
1
2
3
4
5
10
9
8
7
6
11
LTC1407CMSE
LTC1407IMSE
LTC1407ACMSE
LTC1407AIMSE
CONV
SCK
SDO
VDD
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
MSE PART MARKING
TJMAX = 125°C, θJA = 150°C/ W
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
LTBDQ
LTBDR
LTAFE
LTAFF
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
LTC1407
TYP MAX
LTC1407A
MIN TYP MAX
●
12
Integral Linearity Error
(Notes 5, 17)
●
–2
±0.25
2
–4
±0.5
4
LSB
Offset Error
(Notes 4, 17)
●
–10
±1
10
–20
±2
20
LSB
–5
±0.5
5
–10
±1
10
LSB
●
–30
±5
30
–60
±10
60
LSB
–5
±1
5
–10
±2
10
LSB
Offset Match from CH0 to CH1
(Note 17)
Gain Error
(Notes 4, 17)
Gain Match from CH0 to CH1
(Note 17)
Gain Tempco
Internal Reference (Note 4)
External Reference
14
UNITS
±15
±1
Bits
±15
±1
ppm/°C
ppm/°C
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 9)
2.7V ≤ VDD ≤ 3.3V
MIN
TYP
MAX
VCM
Analog Common Mode + Differential
Input Range (Note 10)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
1
ns
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
0.3
ps
tSK
Sample-and-Hold Aperture Skew from CH0 to CH1
200
ps
CMRR
Analog Input Common Mode Rejection Ratio
–60
–15
dB
dB
V
0 to VDD
V
1
●
13
(Note 6)
fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V
UNITS
0 to 2.5
pF
39
●
µA
ns
1407f
2
LTC1407/LTC1407A
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
LTC1407A
MIN TYP MAX
PARAMETER
CONDITIONS
SINAD
Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal
750kHz Input Signal
100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V
750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V
Total Harmonic
Distortion
100kHz First 5 Harmonics
750kHz First 5 Harmonics
SFDR
Spurious Free
Dynamic Range
100kHz Input Signal
750kHz Input Signal
–87
–83
–90
–86
dB
dB
IMD
Intermodulation
Distortion
1.25V to 2.5V 1.40MHz into CH0+ , 0V to 1.25V,
1.56MHz into CH0– . Also Applicable to CH1+ and CH1–
–82
–82
dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 17)
0.25
1
Full Power Bandwidth
VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15)
50
50
MHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
5
5
MHz
THD
MIN
LTC1407
TYP MAX
SYMBOL
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I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
●
●
68
70.5
70.5
72.0
72.0
–87
–83
70
73.5
73.5
76.3
76.3
–90
–86
–77
UNITS
dB
dB
dB
dB
dB
dB
–80
LSBRMS
TA = 25°C. VDD = 3V.
MIN
VREF Output Tempco
TYP
MAX
UNITS
2.5
V
15
ppm/°C
µV/V
VREF Line Regulation
VDD = 2.7V to 3.6V, VREF = 2.5V
600
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
2
ms
VREF Settling Time
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.3V
●
MIN
VIL
Low Level Input Voltage
VDD = 2.7V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 3V, IOUT = – 200µA
●
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT = 160µA
VDD = 2.7V, IOUT = 1.6mA
●
VOUT = 0V to VDD
●
TYP
MAX
2.4
2.5
UNITS
V
0.6
V
±10
µA
5
pF
2.9
V
0.05
0.10
0.4
V
V
±10
µA
IOZ
Hi-Z Output Leakage DOUT
COZ
Hi-Z Output Capacitance DOUT
1
pF
ISOURCE
Output Short-Circuit Source Current
VOUT = 0V, VDD = 3V
20
mA
ISINK
Output Short-Circuit Sink Current
VOUT = VDD = 3V
15
mA
1407f
3
LTC1407/LTC1407A
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Supply Voltage
IDD
Supply Current
Active Mode, fSAMPLE = 1.5Msps
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
TYP
MAX
UNITS
3.6
V
7.0
1.5
15
10
mA
mA
µA
µA
2.7
4.7
1.1
2.0
2.0
●
●
12
mW
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency per Channel
(Conversion Rate)
●
tTHROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
●
tSCK
Clock Period
(Note 16)
tCONV
Conversion Time
(Note 6)
32
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
ns
t3
SCK Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t7
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+ or
CH1+ input with CH0 – or CH1– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0+ and CH0 – or CH1+ and CH1–.
Note 9: The absolute voltage at CH0+, CH0 –, CH1+ and CH1– must be
within this range.
CONDITIONS
MIN
●
TYP
MAX
1.5
UNITS
MHz
667
19.6
10000
34
ns
ns
SCLK cycles
ns
2
ms
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specified with 14-bit Resolution
(1LSB = 152µV) and the LTC1407 is measured and specified with 12-bit
Resolution (1LSB = 610µV).
1407f
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LTC1407/LTC1407A
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TYPICAL PERFOR A CE CHARACTERISTICS
THD, 2nd and 3rd
vs Input Frequency
11.5
71
11.0
68
10.5
65
62
10.0
59
9.5
9.0
56
8.5
53
8.0
0.1
104
–50
98
THD
–56
86
–68
3rd
–74
–80
56
–98
50
1
10
FREQUENCY (MHz)
0
MAGNITUDE (dB)
SNR (dB)
68
65
62
59
56
53
1
10
FREQUENCY (MHz)
100
–20
–30
–30
–40
–40
–50
–60
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
–60
–70
–80
–90
–100
700
1407 G06
100
200 300 400 500
FREQUENCY (kHz)
600
1.0
2.0
1.6
0.6
1.2
0.4
0.2
0
–0.2
–0.4
–0.6
700
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
0.8
–0.8
–110
0
1407 G05
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
MAGNITUDE (dB)
–50
600
–60
–70
Differential Linearity for CH0 with
Internal 2.5V Reference
–40
200 300 400 500
FREQUENCY (kHz)
–50
1407 G04
1.5Msps
100
0
1.5Msps
–10
–20
1403kHz Input Summed with
1563kHz Input IMD 4096 Point
FFT Plot
–30
100
748kHz Sine Wave 4096 Point
FFT Plot
1.5Msps
1407 G03
–20
1
10
FREQUENCY (MHz)
1407 G19
MAGNITUDE (dB)
71
0
44
0.1
100
98kHz Sine Wave 4096 Point
FFT Plot
–10
–120
68
1407 G02
74
0
74
–92
SNR vs Input Frequency
–10
80
62
–86
1407 G01
50
0.1
92
2nd
–62
–104
0.1
50
100
1
10
FREQUENCY (MHz)
SFDR vs Input Frequency
–44
SFDR (dB)
74
THD, 2nd, 3rd (dB)
12.0
SINAD (dB)
ENOBs (BITS)
ENOBs and SINAD
vs Input Sinewave Frequency
VDD = 3V, TA = 25°C (LTC1407A)
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–1.0
–2.0
0
4096
12288
8192
OUTPUT CODE
16384
1407 G15
0
4096
12288
8192
OUTPUT CODE
16384
1407 G16
1407f
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LTC1407/LTC1407A
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TYPICAL PERFOR A CE CHARACTERISTICS
VDD = 3V, TA = 25°C (LTC1407A)
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
1.0
2.0
0.8
1.6
0.6
1.2
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
Differential Linearity for CH1 with
Internal 2.5V Reference
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–1.0
–2.0
0
4096
12288
8192
OUTPUT CODE
0
16384
4096
12288
8192
OUTPUT CODE
16384
1407 G17
1407 G18
VDD = 3V, TA = 25°C (LTC1407/LTC1407A)
Full-Scale Signal Frequency
Response
CMRR vs Frequency
Crosstalk vs Frequency
0
12
6
–20
–30
–20
–40
–12
–18
CROSSTALK (dB)
–40
–6
CMRR (dB)
AMPLITUDE (dB)
0
–60
CH0
CH1
–80
–60
CH1 TO CH0
–70
–24
CH0 TO CH1
–100
–30
–36
1M
–50
10M
100M
FREQUENCY (Hz)
1G
–80
–120
100
1k
10k 100k
1M
FREQUENCY (Hz)
10M
–90
100
1k
10k
100k
FREQUENCY (Hz)
1407 G08
1407 G07
Simultaneous Input Steps at CH0
and CH1 from 25Ω
–25
2.6
–30
2.2
–35
1.8
–40
CH0
CH1
1.4
1M
10M
1407 G09
PSSR vs Frequency
3.0
PSRR (dB)
ANALOG INPUTS (V)
100M
1.0
–45
–50
0.6
–55
0.2
–60
–0.2
–65
–70
–0.6
0
5
10
15
20
TIME (ns)
25
30
1407 G10
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
1407 G11
1407f
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LTC1407/LTC1407A
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TYPICAL PERFOR A CE CHARACTERISTICS
VDD = 3V, TA = 25°C (LTC1407/LTC1407A)
Reference Voltage
vs Load Current
Reference Voltage vs VDD
2.4902
2.4900
2.4900
2.4898
2.4898
VREF (V)
VREF (V)
2.4902
2.4896
2.4896
2.4894
2.4894
2.4892
2.4892
2.4890
2.4890
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
1407 G12
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
1407 G13
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PI FU CTIO S
CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates fully
differentially with respect to CH0– with a 0V to 2.5V
differential swing and a 0 to VDD absolute input range.
CH0– (Pin 2): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+ with a –2.5V to 0V
differential swing and a 0 to VDD absolute input range.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Can be
overdriven by an external reference voltage ≥ 2.55V and
≤VDD.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND pin and solid
analog ground plane with a 10µF ceramic capacitor (or
10µF tantalum) in parallel with 0.1µF ceramic. Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-state Serial Data Output. Each pair of
output data words represent the two analog input channels at the start of the previous conversion.
CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates fully
differentially with respect to CH1– with a 0V to 2.5V
differential swing and a 0 to VDD absolute input range.
SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CH1– (Pin 5): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+ with a –2.5V to 0V
differential swing and a 0 to VDD absolute input range.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts Nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts Sleep mode.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these connections.
1407f
7
LTC1407/LTC1407A
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BLOCK DIAGRA
3V
CH0+
1
+
CH0–
2
–
S&H
MUX
CH1+
4
+
CH1–
5
–
S&H
3
10µF
6
11
LTC1407A
THREESTATE
SERIAL
OUTPUT
PORT
8
SDO
10
CONV
9
SCK
TIMING
LOGIC
VREF
GND
3Msps
14-BIT ADC
VDD
14-BIT LATCH
7
14-BIT LATCH
10µF
2.5V
REFERENCE
EXPOSED PAD
1407A BD
1407f
8
SDO
INTERNAL
S/H STATUS
CONV
SCK
SDO
INTERNAL
S/H STATUS
CONV
SCK
t6
t4
34
t6
t4
34
SAMPLE
33
SAMPLE
33
Hi-Z
2
t8
t2
3
D11
4
6
HOLD
7
1
2
t8
t2
Hi-Z
t3
3
D13
4
8
t1
9
t10
10
11
12
13
14
15
D10
D9
D8
6
HOLD
7
8
t1
D6
D4
9
t10
10
11
12-BIT DATA WORD
D5
D3
12
D2
13
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
X*
t9
16
X*
17
19
14
15
D3
D2
D1
t9
16
D0
17
19
21
22
HOLD
23
24
25
26
27
28
29
30
t8
20
21
D10
D9
22
23
HOLD
D8
D7
24
D6
D4
25
26
27
12-BIT DATA WORD
D5
D3
28
D2
29
D1
30
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
D3
D2
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D13
tTHROUGHPUT
tCONV
Hi-Z
18
t8
20
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D11
tTHROUGHPUT
tCONV
Hi-Z
18
LTC1407A Timing Diagram
D1
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
D7
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
*BITS MARKED “X” AFTER D0 SHOULD BE IGNORED
1
t3
LTC1407 Timing Diagram
t5
31
32
32
t8
t8
X*
D1
t5
31
D0
X*
34
34
Hi-Z
t9
SAMPLE
tACQ
t7
33
Hi-Z
t9
SAMPLE
tACQ
t7
33
HOLD
HOLD
1407A TD01
1
1407A TD01
1
LTC1407/LTC1407A
TI I G DIAGRA S
1407f
9
UW
W
LTC1407/LTC1407A
W
UW
TI I G DIAGRA S
Nap Mode and Sleep Mode Waveforms
SCK
t1
t1
CONV
NAP
SLEEP
t12
VREF
1407 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
VIH
t8
t10
SDO
t9
VOH
90%
SDO
10%
VOL
1407 TD03
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DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1407/LTC1407A
are easy to drive. The inputs may be driven differentially or
as a single-ended input (i.e., the CH0– input is grounded).
All four analog inputs of both differential analog input
pairs, CH0+ with CH0– and CH1+ with CH1–, are sampled
at the same instant. Any unwanted signal that is common
to both inputs of each input pair will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low, then the LTC1407/LTC1407A inputs
can be driven directly. As source impedance increases, so
will acquisition time. For minimum acquisition time with
high source impedance, a buffer amplifier must be used.
The main requirement is that the amplifier driving the
analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
39ns for full throughput rate). Also keep in mind, while
choosing an input amplifier, the amount of noise and
harmonic distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC1407/LTC1407A depends
on the application. Generally, applications fall into two
categories: AC applications where dynamic specifications
are most critical and time domain applications where DC
accuracy and settling time are most critical. The following
list is a summary of the op amps that are suitable for
driving the LTC1407/LTC1407A. (More detailed information is available in the Linear Technology Databooks and
on the LinearViewTM CD-ROM.)
LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter.
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 500µV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for AC
applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
– 93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for AC
applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/amplifier, 8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
5MHz, unity gain stable, rail-to-rail in and out,
10mA/amplifier, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
unity gain stable, rail-to-rail in and out, 15mA/amplifier,
16nV/√Hz.
LinearView is a trademark of Linear Technology Corporation.
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LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual
Voltage Mode Operational Amplifier.
LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,
unity gain stable, rail-to-rail in and out, 15mA/amplifier,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,
unity gain stable, rail-to-rail in and out, 3mA/amplifier,
1.9nV/√Hz.
LT6600: Amplifier/Filter Differential In/Out with 10MHz
Cutoff.
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1407/LTC1407A noise and distortion. The smallsignal bandwidth of the sample-and-hold circuit is 50MHz.
Any noise or distortion products that are present at the
analog inputs will be summed over this entire bandwidth.
Noisy input circuitry should be filtered prior to the analog
ANALOG
INPUT
51Ω*
inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows
a 47pF capacitor from CHO+ to ground and a 51Ω source
resistor to limit the net input bandwidth to 30MHz. The
47pF capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silvermica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can generate distortion from self heating and from damage that may occur during soldering. Metal film surface
mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in
frequency to the desired signal frequency a multiple pole
filter is required.
High external source resistance, combined with 13pF of
input capacitance, will reduce the rated 50MHz input bandwidth and increase acquisition time beyond 39ns.
1
47pF*
2
3
10µF
11
ANALOG
INPUT
51Ω*
4
47pF*
5
CH0+
CH0–
LTC1407/
LTC1407A
VREF
GND
CH1+
CH1–
1407 F01
*TIGHT TOLERANCE REQUIRED TO AVOID
APERTURE SKEW DEGRADATION
Figure 1. RC Input Filter
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INPUT RANGE
The analog inputs of the LTC1407/LTC1407A may be
driven fully differentially with a single supply. Either input
may swing up to 3V, provided the differential swing is no
greater than 2.5V. In the valid input range, the noninverting input of each channel should always be more positive
than the inverting input of each channel. The 0V to 2.5V
range is also ideally suited for single-ended input use with
single supply applications. The common mode range of
the inputs extend from ground to the supply voltage VDD.
If the difference between the CH0+ and CH0– inputs or the
CH1+ and CH1– inputs exceeds 2.5V, the output code will
stay fixed at all ones, and if this difference goes below 0V,
the ouput code will stay fixed at all zeros.
INTERNAL REFERENCE
The LTC1407/LTC1407A have an on-chip, temperature
compensated, bandgap reference that is factory trimmed
near 2.5V to obtain a precise 2.5V input span. The reference amplifier output VREF, (Pin 3) must be bypassed with
a capacitor to ground. The reference amplifier is stable with
capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or a 10µF tantalum in parallel with
a 0.1µF ceramic is recommended. The V REF pin can be
overdriven with an external reference as shown in Figure␣ 2.
The voltage of the external reference must be higher than
the 2.5V of the open-drain P-channel output of the internal
reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will
see a DC quiescent load of 0.75mA and as much as 3mA
during conversion.
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a unipolar voltage span
that equals the difference between the voltage at the
reference buffer output VREF (Pin 3) and the voltage at the
Exposed Pad ground. The differential input range of ADC
is 0V to 2.5V when using the internal reference. The
internal ADC is referenced to these two nodes. This
relationship also holds true with an external reference.
DIFFERENTIAL INPUTS
The ADC will always convert the unipolar difference of
CH0+ minus CH0– or the unipolar difference of CH1+
minus CH1–, independent of the common mode voltage at
either set of inputs. The common mode rejection holds up
at high frequencies (see Figure 3.) The only requirement is
that both inputs not go below ground or exceed VDD.
0
–20
3
VREF
LTC1407/
10µF
LTC1407A
11
GND
1407 F02
Figure 2
–40
CMRR (dB)
3V REF
–60
CH0
CH1
–80
–100
–120
100
1k
10k 100k
1M
FREQUENCY (Hz)
10M
100M
1407 G08
Figure 3. CMRR vs Frequency
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Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common
mode voltage. However, the offset error will vary. CMRR
is typically better than 60dB.
Figure 4 shows the ideal input/output characteristics for
the LTC1407/LTC1407A. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural
binary with 1LSB = 2.5V/16384 = 153µV for the LTC1407A
and 1LSB = 2.5V/4096 = 610µV for the LTC1407. The
LTC1407A has 1LSB RMS of Gaussian white noise.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best
performance from the LTC1407/LTC1407A, a printed circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the four input
wires of the two input channels should be kept matched.
But each pair of input wires to the two input channels
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.
High quality tantalum and ceramic bypass capacitors should
be used at the VDD and VREF pins as shown in the Block
Diagram on the first page of this data sheet. For optimum
performance, a 10µF surface mount tantalum capacitor
with a 0.1µF ceramic is recommended for the VDD and VREF
pins. Alternatively, 10µF ceramic chip capacitors such as
X5R or X7R may be used. The capacitors must be located
as close to the pins as possible. The traces connecting the
pins and the bypass capacitors must be kept short and
should be made as wide as possible. The VDD bypass capacitor returns to GND (Pin 6) and the VREF bypass capacitor returns to the Exposed Pad ground (Pin 11). Care should
be taken to place the 0.1µF VDD bypass capacitor as close
to Pins 6 and 7 as possible.
Figure 5 shows the recommended system ground connections. All analog circuitry grounds should be terminated at
the LTC1407/LTC1407A Exposed Pad. The ground return
from the LTC1407/LTC1407A Pin 6 to the power supply
should be low impedance for noise-free operation. The
Exposed Pad of the 10-lead MSE package is also tied to
Pin␣ 6 and the LTC1407/LTC1407A GND. The Exposed Pad
should be soldered on the PC board to reduce ground
connection inductance. Digital circuitry grounds must be
connected to the digital supply common.
111...111
UNIPOLAR OUTPUT CODE
111...110
111...101
000...010
000...001
000...000
0
FS – 1LSB
INPUT VOLTAGE (V)
1407 F04
Figure 4. LTC1407/LTC1407A Transfer Characteristic
1407f
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1407 F05
Figure 5. Recommended Layout
POWER-DOWN MODES
Upon power-up, the LTC1407/LTC1407A are initialized to
the active state and is ready for conversion. The Nap and
Sleep mode waveforms show the power down modes for
the LTC1407/LTC1407A. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two
rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407/LTC1407A in Nap mode
and the power drain drops from 14mW to 6mW. The
internal reference remains powered in Nap mode. One or
more rising edges at SCK wake up the LTC1407/LTC1407A
for service very quickly and CONV can start an accurate
conversion within a clock cycle. Four rising edges at
CONV, without any intervening rising edges at SCK, put
the LTC1407/LTC1407A in Sleep mode and the power
drain drops from 14mW to 10µW. One or more rising
edges at SCK wake up the LTC1407/LTC1407A for operation. The internal reference (VREF ) takes 2ms to slew and
settle with a 10µF load. Using sleep mode more frequently
compromises the settled accuracy of the internal reference. Note that for slower conversion rates, the Nap and
Sleep modes can be used for substantial reductions in
power consumption.
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DIGITAL INTERFACE
The LTC1407/LTC1407A have a 3-wire SPI (Serial Protocol Interface) interface. The SCK and CONV inputs and
SDO output implement this interface. The SCK and CONV
inputs accept swings from 3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed
description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1407/
LTC1407A until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a
pulse that is one SCK wide to drive the LTC1407/LTC1407A
and then buffer this signal to drive the frame sync input of
the processor serial port. It is good practice to drive the
LTC1407/LTC1407A CONV input first to avoid digital noise
interference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good
practice to keep the width of the low portion of the CONV
signal greater than 15ns to avoid introducing glitches in
the front end of the ADC just before the sample-and-hold
goes into Hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a
CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in the interface circuit examples, the SCK and CONV inputs
should be driven first, with digital buffers used to drive the
serial port interface. Also note that the master clock in the
DSP may already be corrupted with jitter, even if it comes
directly from the DSP crystal. Another problem with high
speed processor clocks is that they often use a low cost,
low speed crystal (i.e., 10MHz) to generate a fast, but
jittery, phase-locked-loop system clock (i.e., 40MHz). The
jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out two
sets of 12/14 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1407/
LTC1407A first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of
the processor serial port. Use the falling edge of the clock
to latch data from the Serial Data Output (SDO) into your
processor serial port. The 14-bit Serial Data will be received right justified, in two 16-bit words with 32 or more
clocks per frame sync. It is good practice to drive the
LTC1407/LTC1407A SCK input first to avoid digital noise
interference during the internal bit comparison decision
by the internal high speed comparator. Unlike the CONV
input, the SCK input is not sensitive to jitter because the
input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out two sets of 12/14 bits in the output data stream after
the third rising edge of SCK after the start of conversion
with the rising edge of CONV. The two 12-/14-bit words are
separated by two clock cycles in high impedance mode.
Please note the delay specification from SCK to a valid
SDO. SDO is always guaranteed to be valid by the next
rising edge of SCK. The 32-bit output data stream is
compatible with the 16-bit or 32-bit serial port of most
processors.
1407f
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HARDWARE INTERFACE TO TMS320C54x
The LTC1407/LTC1407A are serial output ADCs whose
interface has been designed for high speed buffered serial
ports in fast digital signal processors (DSPs). Figure 6
shows an example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 3Msps conversion rate of the LTC1407/
LTC1407A. The DSP assembly code sets frame sync mode
at the BFSR pin to accept an external positive going pulse
and the serial clock at the BCLKR pin to accept an external
positive edge clock. Buffers near the LTC1407/LTC1407A
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC1407/LTC1407A. This configuration is adequate to traverse a typical system board,
but source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If you
need to terminate the SDO transmission line, buffer it first
with one or two 74ACxx gates. The TTL threshold inputs of
the DSP port respond properly to the 3V swing used with
the LTC1407/LTC1407A.
3V
VDD
5V
7
VCC
10
CONV
LTC1407/
LTC1407A
9
SCK
SDO
GND
BFSR
TMS320C54x
BCLKR
B13
8
B12
BDR
6
CONV
CLK
3-WIRE SERIAL
INTERFACELINK
1407 F06
0V TO 3V LOGIC SWING
Figure 6. DSP Serial Interface to TMS320C54x
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;
;
;
;
;
;
;
;
;
;
;
;
;
08-21-03 ******************************************************************
Files: 1407ASIAB.ASM -> 1407A Sine wave collection with Serial Port interface
both channels collected in sequence in the same 2k record
bvectors.asm
buffered mode.
s2k14ini.asm
2k buffer size.
unipolar mode
Works 16 or 64 clock frames.
negative edge BCLKR
negative BFSR pulse
-0 data shifted
1' cable from counter to CONV at DUT
2' cable from counter to CLK at DUT
***************************************************************************
.width
160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”,
0x500,0
;Set address
.setsect “vectors”, 0x180,0
;Set address
.setsect “buffer”, 0x800,0
;Set address
.setsect “result”, 0x1800,0
;Set address
.text
;.text marks
of executable
of incoming 1407A data
of BSP buffer for clearing
of result for clearing
start of code
start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
pmst = #01a0h
sp = #0700h
dp = #0
ar2 = #1800h
ar3 = #0800h
ar4 = #0h
call sineinit
sinepeek:
call sineinit
wait
;
goto
; stop timer
; stop TDM serial port to AC01
; set up iptr. Processor Mode STatus register
; init stack pointer.
; data page
; pointer to computed receive buffer.
; pointer to Buffered Serial Port receive buffer
; reset record counter
; Double clutch the initialization to insure a proper
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait
————————Buffered Receive Interrupt Routine -————————-
breceive:
ifr = #10h
; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull
; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
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;
———————mask and shift input data ——————————————
bufull:
b = *ar3+ << -0
b = #07FFFh & b
*ar2+ = data(#0bh)
TC = (@ar2 == #02000h)
if (TC) goto start
goto bufull
;
bsend
;
;
;
;
;
;
;
load acc b with BSP buffer and shift right -0
mask out the TRISTATE bits with #03FFFh
store B to out buffer and advance AR2 pointer
output buffer is 2k starting at 1800h
restart if out buffer is at 1fffh
—————————dummy bsend return————————————
return_enable
;this is also a dummy return to define bsend
;in vector table file BVECTORS.ASM
——————————— end ISR ——————————————
.copy “c:\dskplus\1407A\s2k14ini.asm”
;initialize buffered serial port
.space 16*32
;clear a chunk at the end to mark the end
;======================================================================
;
; VECTORS
;
;======================================================================
.sect “vectors”
;The vectors start here
.copy “c:\dskplus\1407A\bvectors.asm”
;get BSP vectors
.sect “buffer”
.space 16*0x800
.sect “result”
.space 16*0x800
;Set address of BSP buffer for clearing
;Set address of result for clearing
.end
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
***************************************************************************
File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus
10.Jul.96
BSP vectors and Debugger vectors
TDM vectors just return
***************************************************************************
The vectors in this table can be configured for processing external and
internal software interrupts. The DSKplus debugger uses four interrupt
vectors. These are RESET, TRAP2, INT2, and HPIINT.
* DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
All other vector locations are free to use. When programming always be sure
the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
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.title “Vector Table”
.mmregs
reset
nmi
trap2
int0
int1
int2
tint
brint
bxint
trint
txint
int3
hpiint
goto #80h
nop
nop
return_enable
nop
nop
nop
goto #88h
nop
nop
.space 52*16
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
goto breceive
nop
nop
nop
goto bsend
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
return_enable
nop
nop
nop
dgoto #0e4h
nop
nop
;00; RESET
* DO NOT MODIFY IF USING DEBUGGER *
;04; non-maskable external interrupt
;08; trap2
* DO NOT MODIFY IF USING DEBUGGER *
;0C-3F: vectors for software interrupts 18-30
;40; external interrupt int0
;44; external interrupt int1
;48; external interrupt int2
;4C; internal timer interrupt
;50; BSP receive interrupt
;54; BSP transmit interrupt
;58; TDM receive interrupt
;5C; TDM transmit interrupt
;60; external interrupt int3
;64; HPIint
* DO NOT MODIFY IF USING DEBUGGER *
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.space
24*16
;68-7F; reserved area
**********************************************************************
*
(C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996
*
**********************************************************************
*
*
* File: BSPI1407A.ASM BSP initialization code for the ‘C54x DSKplus *
*
for use with 1407A in standard mode
*
*
BSPC and SPC seem interchangeable in the ‘C542
*
*
BSPCE and SPCE seem interchangeable in the ‘C542
*
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON
.set 1
OFF
.set !ON
YES
.set 1
NO
.set !YES
BIT_8
.set 2
BIT_10
.set 1
BIT_12
.set 3
BIT_16
.set 0
GO
.set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled. Set the variables listed below to configure the BSP for
* your application.
*
*****************************************************************************************************
*LTC1407A timing with 40MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1407A board.
*
*Horizontal scale is 6.25ns/chr or 25ns period at BCLKR
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/
~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
~\_/~\_/~*
*BDR
Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13B12*
*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/
~~~~~~~\_______/~~~~~*
*C542 read
0 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0
0
B13 B12*
*
*
* negative edge BCLKR
* negative BFSR pulse
* no data shifted
* 1' cable from counter to CONV at DUT
1407f
21
LTC1407/LTC1407A
U
W
U U
APPLICATIO S I FOR ATIO
* 2' cable from counter to CLK at DUT
*No right shift is needed to right justify the input data in the main program
*
*the two msbs should also be masked
*
****************************************************************************************************
*
Loopback
.set
NO
;(digital looback mode?)
DLB bit
Format
.set
BIT_16
;(Data format? 16,12,10,8)
FO bit
IntSync
.set
NO
;(internal Frame syncs generated?) TXM bit
IntCLK
.set
NO
;(internal clks generated?)
MCM bit
BurstMode
.set
YES
;(if BurstMode=NO, then Continuous) FSM bit
CLKDIV
.set
3
;(3=default value, 1/4 CLOCKOUT)
PCM_Mode
.set
NO
;(Turn on PCM mode?)
FS_polarity
.set
YES
;(change polarity)YES=~~~\_/~~~, NO=___/~\___
CLK_polarity
.set
NO
;(change polarity)for BCLKR YES=_/~, NO=~\_
Frame_ignore
.set
!YES
;(inverted !YES -ignores frame)
XMTautobuf
.set
NO
;(transmit autobuffering)
RCVautobuf
.set
NO
;(receive autobuffering)
XMThalt
.set
NO
;(transmit buff halt if XMT buff is full)
RCVhalt
.set
NO
;(receive buff halt if RCV buff is full)
XMTbufAddr
.set
0x600
;(address of transmit buffer)
RCVbufAddr
.set
0x800
;(address of receive buffer)
XMTbufSize
.set
0x200
;(length of transmit buffer)
RCVbufSize
.set
0x040
;(length of receive buffer)
*
* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up
* valid buffer start and length values.
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync
<<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &
1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)),
SPCEval
bspi1407A:
bspc = #SPCval
bspce = #SPCEval
axr = #XMTbufAddr
bkx = #XMTbufSize
arr = #RCVbufAddr
bkr = #RCVbufSize
bspc = #(SPCval | GO)
return
;
;
;
;
;
;
;
;
places buffered serial port in reset
programs BSPCE and ABU
initializes transmit buffer start address
initializes transmit buffer size
initializes receive buffer start address
initializes receive buffer size
bring buffered serial port out of reset
for transmit and receive because GO=0xC0
1407f
22
LTC1407/LTC1407A
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
0.254
(.010)
DETAIL “A”
0° – 6° TYP
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
10
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.127 ± 0.076
(.005 ± .003)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.497 ± 0.076
(.0196 ± .003)
REF
MSOP (MSE) 0603
1 2 3 4 5
1407f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1407/LTC1407A
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SoftSpan is a trademark of Linear Technology Corporation.
1407f
24 Linear Technology Corporation
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