Freescale Semiconductor, Inc. MOTOROLA Order this document by MPC9608 SEMICONDUCTOR TECHNICAL DATA MPC9608 1:10 LVCMOS Zero Delay Clock Buffer Freescale Semiconductor, Inc... The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. Features • 1:10 outputs LVCMOS zero-delay buffer • Single 3.3 V supply • Supports a clock I/O frequency range of 12.5 to 200 MHz • Selectable divide-by-two for one output bank • Synchronous output enable control (CLK_STOP) • Output tristate control (output high impedance) • PLL bypass mode for low frequency system test purpose • Supports networking, telecommunications and computer applications • Supports a variety of microprocessors and controllers • Compatible to PowerQuicc I and II • Ambient Temperature Range -40°C to +85°C • 32-lead Pb-free package available LOW VOLTAGE 3.3 V LVCMOS 1:10 ZERO-DELAY CLOCK BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A AC SUFFIX 32 LEAD LQFP PACKAGE-Pb-free CASE 873A Functional Description The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized to the input reference for both bank B configurations. Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification do not apply. CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL losing lock. The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. REV 2 © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9608 Bank A CCLK Ref CCLK PLL 00: 100-200 MHz 25k QA0 01: 50-100 MHz QA1 STOP VCO QA2 10: 25- 50 MHz QA3 FB 11:12.5- 25 MHz FB_IN 25k QA4 Bank B F_RANGE[0:1] 25k QB0 2 QB1 Freescale Semiconductor, Inc... PLL_EN ÷2 25k QB2 QB3 CLK_STOP 25k QB4 BSEL PLL feedback 25k OE QFB 25k GND CLK_STOP BSEL VCC F_RANGE0 F_RANGE1 OE GND Figure 1. MPC9608 Logic Diagram 24 23 22 21 20 19 18 17 VCC 25 16 VCC QA4 26 15 QB4 QA3 27 14 QB3 QA2 28 13 QB2 GND 29 12 GND QA1 30 11 QB1 QA0 31 10 QB0 VCC 32 9 VCC 1 2 3 4 5 6 7 8 GND CCLK PLL_EN VCCA VCC FB_IN QFB GND MPC9608 Figure 2. MPC9608 32-Lead Package Pinout (Top View) 2 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9608 TABLE 1. PIN CONFIGURATION Freescale Semiconductor, Inc... Pin I/O Type Function CCLK Input LVCMOS PLL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to a QFB output F_RANGE[0:1] Input LVCMOS PLL frequency range select BSEL Input LVCMOS Frequency divider select for bank B outputs PLL_EN Input LVCMOS PLL enable/disable OE Input LVCMOS Output enable/disable (high-impedance tristate) CLK_STOP Input LVCMOS Synchronous clock enable/stop QA0-4, QB0-4 Output LVCMOS Clock outputs QFB Output LVCMOS PLL feedback signal output. Connect to FB_IN GND Supply Ground Negative power supply VCCA Supply VCC PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for the analog power supply pin VCCA. Refer to the Applications Information section for details. VCC Supply VCC Positive power supply for I/O and core TABLE 2. FUNCTION TABLE Control Default 0 1 F_RANGE[0:1] 00 PLL frequency range. Refer to Table 3 “Clock frequency configuration for QFB connected to FB_IN” BSEL 0 fQB0-4 = fQA0-4 fQB0-4 = fQA0-4 ÷ 2 CLK_STOP 0 Outputs enabled Outputs synchronously stopped in logic low state OE 0 Outputs enabled (active) Outputs disabled (high-impedance state), independent on CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device. The PLL feedback output QFB is not affected by OE. PLL_EN 0 Normal operation mode with PLL enabled. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC9608 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Applying OE = 1 and PLL_EN = 1 resets the device. TABLE 3. Clock Frequency Configuration for QFB connected to FB_IN F_RANGE[0] F_RANGE[1] BSEL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TIMING SOLUTIONS fREF (CCLK) range [MHz] Ratio fQA0-4 [MHz] 100.0 – 200.0 fREF 100.0 – 200.0 50.0 – 100.0 QA0-QA4 fREF 50.0 – 100.0 25.0 – 50.0 fREF 25.0 – 50.0 12.5 – 25.0 fREF 12.5 – 25 For More Information On This Product, Go to: www.freescale.com QB0-B4 Ratio fQB0-4 [MHz] QFB fREF 100.0 – 200.0 fREF fREF ÷ 2 50.0 – 25.0 fREF fREF 50.0 – 100.0 fREF fREF ÷ 2 25.0 – 50.0 fREF fREF 25.0 – 50.0 fREF fREF ÷ 2 12.5 – 25.0 fREF fREF 12.5 – 25.0 fREF fREF ÷ 2 6.25 – 12.5 fREF 3 Freescale Semiconductor, Inc. MPC9608 TABLE 4. GENERAL SPECIFICATIONS Symbol Characteristics Min Max Unit VCC ÷ 2 VTT Output termination voltage MM ESD protection (Machine model) 200 HBM Typ Condition V V ESD protection (Human body model) 2000 V LU Latch-up immunity 200 mA CPD Power dissipation capacitance 10 pF Per output CIN Input capacitance 4.0 pF Inputs TABLE 5. ABSOLUTE MAXIMUM RATINGSa Freescale Semiconductor, Inc... Symbol Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS a. Characteristics DC Input Current DC Output Current Storage temperature -65 Condition Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. TABLE 6. DC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C) Symbol Characteristics VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN Currentb Input Min Typ 2.0 Max Unit VCC + 0.3 V LVCMOS 0.8 V LVCMOS V IOH = -24 mAa V V IOL = 24 mA IOL = 12 mA 2.4 0.55 0.30 Condition Ω 14 – 17 ±200 µA VIN = VCC or GND ICCA Maximum PLL Supply Current 4.0 8.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 4.0 mA All VCC Pins a. The MPC9608 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. b. Inputs have pull-down resistors affecting the input current. 4 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9608 TABLE 7. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C)a Symbol Min Input reference frequency in PLL modeb F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Input reference frequency in PLL bypass modec fmax Output Frequencyd tPW, MIN Freescale Semiconductor, Inc... Characteristics fref F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Reference Input Pulse Widthe Max Unit 100 50 25 12.5 0 200 100 50 25 200 MHz MHz MHz MHz MHz 100 50 25 12.5 200 100 50 25 MHz MHz MHz MHz 2.0 tr, tf CCLK Input Rise/Fall Time t(∅) Propagation Delay (SPO) CCLK to FB_IN fref = 100 MHz and above -175 fref = 12.5 MHz to 100 MHz -1.75% of tPER tSK(o) 45 0.1 Output Rise/Fall Time Output Disable Time tPZL, LZ tJIT(CC) tJIT(PER) Period Jitter BW tLOCK 1.0 ns 0.8 V to 2.0 V +175 +1.75% of tPER ps ps PLL Locked 80 100 150 Output Duty Cycle tr, tf BSEL = 0 BSEL = 0 BSEL = 0 BSEL = 0 ps Within a bank Bank-to-bank All outputs, inluding QFB tPLZ, HZ Condition ns Output-to-Output Skew DC tJIT(∅) Typ 50 55 % 1.0 ns 10 ns Output Enable Time 10 ns Cycle-to-cycle jitter 150 ps BSEL = 0 150 ps BSEL = 0 125 ps BSEL = 0 RMS (1 σ) I/O Phase Jitter PLL closed loop bandwidth f F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Maximum PLL Lock Time a. AC characteristics apply for parallel output termination of 50 Ω to VTT. b. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation. 7 – 15 2–7 1–3 0.5 – 1.3 MHz MHz MHz MHz 10 ms 0.55 V to 2.4 V c. In bypass mode, the MPC9608 divides the input reference clock. d. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two. e. Calculation of reference duty cycle limits: DCREF, MIN = tPW, MIN * fREF *100% and DCREF, MAX = 100% – DCREF, MIN. For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%. f. -3 dB point of PLL transfer characteristics. TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. MPC9608 APPLICATIONS INFORMATION Freescale Semiconductor, Inc... Power Supply Filtering The MPC9608 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9608 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9608. Figure 3 illustrates a typical power supply filter scheme. The MPC9608 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 4 mA (8 mA maximum), assuming that a minimum of 3.125 V must be maintained on the VCCA pin. The resistor RF shown in Figure 3 “VCCA Power Supply Filter” must have a resistance of 9 – 10 Ω (VCC = 3.3 V) to meet the voltage drop criteria. RF = 9-10 Ω for VCC = 3.3 V VCC CF = 1 µF for VCC = 3.3 V (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9608 in Zero-delay Applications Nested clock trees are typical applications for the MPC9608. Designs using the MPC9608, as LVCMOS PLL fanout buffer with zero insertion delay, will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9608 clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting in a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9608 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9608 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) . CF RF VCCA CF 10 nF MPC9608 VCC This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: CCLKCommon Figure 3. VCCA Power Supply Filter QFBDevice 1 The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3 “VCCA Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. Any QDevice 1 As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9608 has several design features to minimize the susceptibility to power supply noise Any QDevice 2 6 tPD,LINE(FB) -t(∅) 33...100 nF tJIT(∅) +tSK(O) +t(∅) QFBDevice2 tJIT(∅) +tSK(O) Max. skew tSK(PP) Figure 4. MPC9608 maximum device-to-device skew For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9608 Due to the statistical nature of I/O jitter, an RMS value (1 σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Freescale Semiconductor, Inc... TABLE 8. Confidence Facter CF IN CF Probability of clock edge within the distribution ± 1σ 0.68268948 ± 2σ 0.95449988 ± 3σ 0.99730007 ± 4σ 0.99993663 ± 5σ 0.99999943 ± 6σ 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst case timing uncertainty from input to any output of -295 ps to 295 ps1 relative to CCLK: tSK(PP) = tSK(PP) = MPC9608 OUTPUT BUFFER [-100 ps...100 ps] + [-150 ps...150 ps] + [(15 ps . -3)...(15 ps . 3)] + tPD, LINE(FB) [-295 ps...295 ps] + tPD, LINE(FB) Driving Transmission Lines The MPC9608 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC ÷ 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9608 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5 “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9608 clock driver is effectively doubled due to its capability to drive multiple lines. RS = 36 Ω 14 Ω OutA MPC9608 OUTPUT BUFFER IN ZO = 50 Ω RS = 36 Ω ZO = 50 Ω OutB0 14 Ω RS = 36 Ω ZO = 50 Ω OutB1 Figure 5. Single versus Dual Transmission Lines The waveform plots in Figure 6 “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9608 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. From the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9608. The output waveform in Figure 6 “Single versus Dual Line Termination Waveforms” shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS ( Z0 ÷ (RS + R0 + Z0)) 50 Ω || 50 Ω 36 Ω || 36 Ω 14 Ω 3.0 ( 25 ÷ (18 + 17 + 25)) 1.31 V At the load end the voltage will double to 2.6 V due to the near unity reflection coefficient. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Skew data are designed targets and pending device specifcations. TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. MPC9608 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 MPC9608 OUTPUT BUFFER OutB tD = 3.9386 ZO = 50 Ω RS = 22 Ω ZO = 50 Ω 14 Ω 2.0 In 1.5 14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω 1.0 Figure 7. Optimized Dual Line Termination 0.5 Freescale Semiconductor, Inc... RS = 22 Ω 0 2 4 6 8 10 TIME (nS) 12 14 Figure 6. Single versus Dual Waveforms Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 7 “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9608 DUT Pulse Generator Z = 50 Ω ZO = 50 Ω RT = 50 Ω ZO = 50 Ω RT = 50 Ω VTT VTT Figure 8. CCLK MPC9608 AC test reference for VCC = 3.3 V 8 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9608 VCC VCC ÷ 2 VCC VCC ÷ 2 CCLK GND VCC VCC ÷ 2 GND VCC VCC ÷ 2 FB_IN GND GND tSK(O) t(∅) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. Freescale Semiconductor, Inc... Figure 9. Output-to-output Skew tSK(O) VCC VCC ÷ 2 Figure 10. Propagation delay (tPD, static phase offset) test reference CCLK GND FB_IN tP T0 TJIT(∅) = |T0 - T1 mean| DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles. Figure 11. Output Duty Cycle (DC) Figure 12. I/O Jitter TN TJIT(CC) = |TN -TN + 1| TN + 1 TJIT(PER) = |TN - 1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles. Figure 13. Cycle-to-cycle Jitter Figure 14. Period Jitter VCC VCC = 3.3 V 2.4 VCC ÷ 2 CCLK GND 0.55 tF VCC VCC ÷ 2 CLK_STOP tR GND ts Figure 15. Output Transition Time Test Reference TIMING SOLUTIONS tH Figure 16. Setup and Hold Time (ts, tH) Test Reference For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. MPC9608 OUTLINE DIMENSIONS 4X 0.20 H 6 A-B D D1 PIN 1 INDEX 3 e/2 D1/2 32 A, B, D 25 1 E1/2 A F B 6 E1 E 4 F DETAIL G Freescale Semiconductor, Inc... 8 17 9 7 D/2 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 4 D A-B D H SEATING PLANE DETAIL G D 4X 0.20 C E/2 28X e 32X C 0.1 C DETAIL AD PLATING BASE METAL b1 c c1 b 8X (θ1˚) 0.20 R R2 A2 C A-B D SECTION F-F R R1 A M 5 0.25 GAUGE PLANE A1 (S) L (L1) θ˚ DETAIL AD 8 DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0˚ 7˚ 12 REF 0.08 0.20 0.08 --0.20 REF FA SUFFIX LQFP PACKAGE AC SUFFIX LQFP PACKAGE-Pb-free CASE 873A-02 ISSUE A 10 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9608 Freescale Semiconductor, Inc... NOTES 11 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 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Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MPC9608