PHILIPS PSMN008-75P

PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
Rev. 01 — 18 September 2000
Product specification
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PSMN008-75P in SOT78
PSMN008-75B in SOT404 (D2-PAK).
2. Features
■ Fast switching
■ Low on-state resistance
■ Avalanche ruggedness rated.
3. Applications
c
■ DC to DC converters
■ Uninterruptable power supplies.
c
4. Pinning information
Table 1:
Pinning - SOT78 and SOT404, simplified outline and symbol
Pin
Description
1
gate (g)
2
drain (d)
3
source (s)
mb
connected to
drain (d)
Simplified outline
Symbol
mb
mb
[1]
d
g
2
MBK106
1 2 3
SOT78
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
1.
TrenchMOS is a trademark of Royal Philips Electronics.
1
3
MBK116
SOT404 (D2-PAK)
MBB076
s
Philips Semiconductors
PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
5. Quick reference data
Table 2:
Quick reference data
Symbol
Parameter
Conditions
Typ
Max
Unit
VDS
drain-source voltage (DC)
Tj = 25 to 175 °C
−
75
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 10 V
−
75
A
Ptot
total power dissipation
Tmb = 25 °C
−
230
W
Tj
junction temperature
−
175
°C
RDSon
drain-source on-state resistance
7.9
8.5
mΩ
Min
Max
Unit
VGS = 10 V; ID = 25 A
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS
drain-source voltage (DC)
Tj = 25 to 175 °C
−
75
V
VDGR
drain-gate voltage (DC)
Tj = 25 to 175 °C; RGS = 20 kΩ
−
75
V
VGS
gate-source voltage (DC)
−
±20
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 10 V;
Figure 2 and 3
−
75
A
Tmb = 100 °C; VGS = 10 V;
Figure 2 and 3
−
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 2 and 3
−
240
A
Tmb = 25 °C; Figure 1
Ptot
total power dissipation
−
230
W
Tstg
storage temperature
−55
+175
°C
Tj
operating junction temperature
−55
+75
°C
Source-drain diode
IS
source (diode forward) current
(DC)
Tmb = 25 °C
−
75
A
ISM
peak source (diode forward)
current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
−
240
A
Avalanche ruggedness
EAS
non-repetitive avalanche energy
unclamped inductive load; ID = 75 A;
tp = 0.1 ms; VDD ≤ 15 V;
RGS = 50 Ω; VGS = 10 V; starting
Tj = 25 °C; Figure 4
−
360
mJ
IAS
non-repetitive avalanche current
unclamped inductive load;
VDD ≤ 15 V; RGS = 50 Ω;
VGS = 10 V; Figure 4
−
75
A
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
2 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03ad10
03aa11
120
120
Ider
Pder 100
100
(%)
(%)
80
80
60
60
40
40
20
20
0
0
0
25
50
75
100
0
125
150
175
Tamb (oC)
25
50
75
100
125
150
175
200
Tmb (oC)
VGS ≥ 10 V
P tot
P der = ---------------------- × 100%
P
°
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
103
ID
(A)
03ac65
RDSon = VDS/ ID
tp = 100 µs
03ac93
103
I
AS
(A)
1 ms
102
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
102
10 ms
25 oC
D.C.
10
δ=
P
tp
100 ms
T
10
Tj prior to avalance = 150 oC
1
t
tp
T
10-1
1
10
102
VDS (V)
103
Tmb = 25 °C; IDM is single pulse
1
10-2
1
tp (ms)
10
Unclamped inductive load; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C and 150 °C.
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage.
Fig 4. Non-repetitive avalanche ruggedness current
as a function of pulse duration.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
10-1
Rev. 01 — 18 September 2000
3 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
7. Thermal characteristics
Table 4:
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting Figure 5
base
Rth(j-amb)
thermal resistance from junction to ambient
Value
Unit
0.65
K/W
SOT78 package; vertical in still air
60
K/W
SOT404 package; mounted on
printed circuit board; minimum
footprint.
50
K/W
7.1 Transient thermal impedance
03ac94
1
δ = 0.5
Zth(j-mb)
(K/W)
0.2
10-1
0.1
0.05
0.02
P
d=
10-2
tp
T
single pulse
t
tp
T
10-3
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of
pulse duration.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
4 of 14
Philips Semiconductors
PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V
75
90
−
V
Tj = 25 °C
2
3
4
V
Tj = 175 °C
1
−
−
V
Tj = 25 °C
−
0.05
10
µA
Tj = 175 °C
−
−
500
µA
−
4
100
nA
Tj = 25 oC
−
7.9
8.5
mΩ
Tj = 175 °C
−
−
20
mΩ
−
115
−
nC
−
21
−
nC
−
50
−
nC
−
4.7
−
nF
−
760
−
pF
−
400
−
pF
Static characteristics
V(BR)DSS
drain-source breakdown
voltage
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 10
IDSS
drain-source leakage current
VGS = 0 V; VDS = 75 V
IGSS
gate-source leakage current
VDS = 0 V; VGS = ±20 V
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A;
Figure 8 and 9
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-source charge
Qgd
gate-drain (Miller) charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
turn-off rise time
td(off)
tf
ID = 75 A; VDS = 60 V;
VGS = 10 V; Figure 15
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 13
−
18
−
ns
−
80
−
ns
turn-off delay time
−
170
−
ns
turn-off fall time
−
100
−
ns
VDD = 37.5 V; RD = 1.5 Ω;
VGS = 10 V; RG = 10 Ω
Source-drain diode
VSD
source-drain (diode forward)
voltage
IS = 25 A; VGS = 0 V;
Figure 14
−
0.8
1.2
V
trr
reverse recovery time
−
80
−
ns
Qr
recovered charge
IS = 5 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
−
227
−
nC
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
5 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03ac64
100
ID
(A) 90
03ac67
100
Tj = 25 oC
ID
(A) 90
VGS = 6.0 V
80
VDS > ID X RDSon
80
5.0 V
70
70
60
60
50
50
Tj = 150 oC
4.5 V
40
40
4.3 V
30
30
4.1 V
20
Tj = 25 oC
20
3.9 V
10
10
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
0.5
1
1.5
2
2.5
3
VDS (V)
3.5
4
4.5
5
5.5
6
VGS (V)
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID × RDSon
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values.
03ac66
0.1
3.9 V
R DSon 0.09
(Ω)
0.08
Tj = 25 oC
4.1 V
4.3 V
0.07
0.06
4.5 V
0.05
0.04
0.03
VGS = 10 V
0.02
5.0 V
0.01
0
0
10
20
30
40
50
60
70
80
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03aa29
3
a 2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60
90 100
I D (A)
Tj = 25 °C
-20
20
60
100
140
180
Tj (oC)
R DSon
a = --------------------------R
°
DSon ( 25 C )
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
6 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03aa32
5
VGS(th)
4.5
4
(V)
03aa35
10-1
ID
(A)
max.
10-2
3.5
3
10-3
typ.
2.5
min
2
typ
max
10-4
min
1.5
1
10-5
0.5
0
10-6
-60
-20
20
60
100
140
Tj (oC)
180
Fig 10. Gate-source threshold voltage as a function of
junction temperature.
2
3
4
VGS (V)
5
Fig 11. Sub-threshold drain current as a function of
gate-source voltage.
03ac71
100
(S)
1
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
gfs
0
03ac68
104
VDS > ID X RDSon
90
Ciss, Coss,
Tj = 25 oC
80
Ciss
Crss (pF)
70
60
175 oC
50
103
Coss
40
30
20
Crss
10
0
0
10
20
30
40
50
60
70
80 90 100
ID (A)
Tj = 25 °C and 175 °C; VDS > ID × RDSon
102
1
10 2
10
VDS (V)
VGS = 0 V; f = 1 MHz
Fig 12. Forward transconductance as a function of
drain current; typical values.
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
10-1
Rev. 01 — 18 September 2000
7 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03ac70
50
VGS = 0 V
IS 45
(A)
40
03ac69
15
VGS 14
( V ) 13
ID = 75 A
o
Tj = 25 C
12
175 oC
11
35
10
9
30
V
8
25
DS
= 15 V
7
20
6
VDS = 60 V
5
15
4
10
3
2
Tj = 25 oC
5
1
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VSD (V)
Tj = 25 °C and 175 °C; VGS = 0 V
0
20
30
40
50
60
70
80 90 100
QG (nC)
ID = 75 A; VDS = 15 V and 60 V
Fig 14. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 15. Gate-source voltage as a function of gate
charge; typical values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
10
Rev. 01 — 18 September 2000
8 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
9. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
E
SOT78
A
A1
P
q
mounting
base
D1
D
L1
L2(1)
Q
b1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
e
L
L1
L2
max.
P
q
Q
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
EIAJ
3-lead TO-220AB
SC-46
EUROPEAN
PROJECTION
ISSUE DATE
99-09-13
00-09-07
Fig 16. SOT78
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
9 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.40
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig 17. SOT404 (D2-PAK).
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
10 of 14
Philips Semiconductors
PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
10. Revision history
Table 6:
Revision history
Rev Date
01
20000918
CPCN
Description
-
Product specification.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
11 of 14
PSMN008-75P; PSMN008-75B
Philips Semiconductors
N-channel enhancement mode field-effect transistor
11. Data sheet status
Datasheet status
Product status
Definition [1]
Objective specification
Development
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
12. Definitions
13. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
© Philips Electronics N.V. 2000 All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
12 of 14
Philips Semiconductors
PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
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Internet: http://www.semiconductors.philips.com
(SCA70)
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07495
Product specification
Rev. 01 — 18 September 2000
13 of 14
Philips Semiconductors
PSMN008-75P; PSMN008-75B
N-channel enhancement mode field-effect transistor
Contents
1
2
3
4
5
6
7
7.1
8
9
10
11
12
13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
© Philips Electronics N.V. 2000.
Printed in The Netherlands
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Date of release: 18 September 2000
Document order number: 9397 750 07495