Final Electrical Specifications
LTC3900
Synchronous Rectifier
Driver for Forward Converters
November 2003
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DESCRIPTIO
FEATURES
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The LTC®3900 is a secondary-side synchronous rectifier
driver designed to be used in isolated forward converter
power supplies. The chip drives N-channel rectifier
MOSFETs and accepts pulse sychronization from the
primary-side controller via a pulse transformer.
N-Channel Synchronous Rectifier MOSFET Driver
Programmable Timeout
Reverse Inductor Current Sense
Pulse Transformer Synchronization
Wide VCC supply range: 4.5V to 11V
15ns Rise/Fall Times at VCC = 5V, CL = 4700pF
Undervoltage Lockout
Small SO-8 Package
The LTC3900 incorporates a full range of protection for the
external MOSFETs. A programmable timeout function is
included that disables both drivers when the synchronization signal is missing or incorrect. Additionally, the chip
senses the output inductor current through the drainsource resistance of the catch MOSFET, shutting off the
MOSFET if the inductor current reverses. The LTC3900
also shuts off the drivers if the supply voltage is low.
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APPLICATIO S
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48V Input Isolated DC/DC Converters
Isolated Telecom Power Supplies
Distributed Power Step-Down Converters
Industrial Control System Power Supplies
Automotive and Heavy Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
ISOLATION
BARRIER
L0
VIN
36V TO 72V
D3
COUT
BG
+
VOUT
3.3V
T1
CZ
RCS2
Q1
RCS1
Q3
LTC1693-2
QREG
RB
DZ
CS+
CG
Q4
VCC
CS–
RCS3
RTMR
LTC3900
FG
CSG
CVCC
TIMER
CTMR
SYNC GND
LTC1693-2
GATE
LT1950
FORWARD CONTROLLER
RZ
SG
T2
RSYNC
RF
R1
CF
270Ω
GND COMP
R2
–
LT1797
+
OC1
VR
3900 F01
Figure 1. Simplified Isolated Forward Converter
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3900
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage
VCC ......................................................................................... 12V
Input Voltage
CS –, TIMER .............................. – 0.3V to (VCC +0.3V)
SYNC ...................................................... –12V to 12V
Input Current
CS+ .................................................................................... 15mA
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
CS + 1
8
SYNC
CS –
2
7
TIMER
CG 3
6
GND
VCC 4
5
FG
LTC3900ES8
S8 PART
MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
3900
TJMAX = 150°C, θJA = 130°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range. VCC = 5V, TA = 25°C unless otherwise specified. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCC
Supply Voltage Range
4.5
5
11
V
VUVLO
VCC Undervoltage Lockout Threshold
VCC Undervoltage Lockout Hysteresis
Rising Edge
Rising Edge to Falling Edge
●
4.1
0.5
4.5
V
V
IVCC
VCC Supply Current
VSYNC = 0V
●
fSYNC = 100kHz, CFG = CCG = 4700pF (Note 4) ●
0.5
7
1
15
mA
mA
VCC/5
10%
V
●
UNITS
Timer
VTMR
Timer Threshold Voltage
ITMR
Timer Input Current
VTMR = 0V
●
–6
–10
µA
tTMRDIS
Timer Discharge Time
CTMR = 1000pF, RTMR = 4.7k
●
40
120
ns
VTMRMAX
Timer Pin Clamp Voltage
CTMR = 1000pF, RTMR = 4.7k
ICS+
CS+ Input Current
VCS+ = 0V
●
±1
µA
ICS–
CS–
Input Current
VCS – = 0V
●
±1
µA
VCSMAX
CS+
Pin Clamp Voltage
IIN = 5mA, VSYNC = –5V
VCS
Current Sense Threshold Voltage
10.5
13.5
18
mV
mV
±1
±10
µA
●
–10%
2.5
V
Current Sense
11
VCS – = 0V
(Note 6)
●
●
7.5
3
V
SYNC Input
ISYNC
SYNC Input Current
VSYNC = ±10V
VSYNCP
SYNC Input Positive Threshold
SYNC Positive Input Hysteresis
(Note 5)
SYNC Input Negative Threshold
SYNC Negative Input Hysteresis
(Note 5)
VSYNCN
●
1.0
1.4
0.2
1.8
V
V
●
–1.8
–1.4
0.2
–1.0
V
V
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LTC3900
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range. VCC = 5V, TA = 25°C unless otherwise specified. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
Driver Pull-Up Resistance
IOUT = –100mA
MIN
TYP
MAX
UNITS
0.9
1.2
1.6
Ω
Ω
0.9
1.2
1.6
Ω
Ω
Driver Output
RONH
●
RONL
Driver Pull-Down Resistance
IOUT = 100mA
●
IPK
Driver Peak Output Current
(Note 5)
2
A
Switching Characteristics (Note 7)
CFG = CCG = 4700pF, VSYNC = ±5V
●
Minimum SYNC Pulse Width
VSYNC = ±5V
●
Driver Rise/Fall Time
CFG = CCG = 4700pF, VSYNC = ±5V
td
SYNC Input to Driver Output Delay
tSYNC
t r, t f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3900E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design; characterization and correlation
with statistical process controls.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
60
75
120
ns
ns
15
ns
will vary with supply voltage, switching frequency and the external
MOSFETs used.
Note 5: Guaranteed by design, not subject to test.
Note 6: The current sense comparator threshold has a 0.33%/°C
temperature coefficient (TC) to match the TC of the external MOSFET
RDS(ON).
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured from ±1.4V at SYNC input to 20%/80% levels at the
driver output.
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TYPICAL PERFOR A CE CHARACTERISTICS
Timeout vs VCC
5.25
5.25
TA = 25°C
RTMR = 51k
CTMR = 470pF
5.20
5.15
5.20
5.15
10
VCC = 5V
RTMR = 51k
CTMR = 470pF
TA = 25°C
9 VCC = 5V
CTMR = 470pF
8
5.10
5.05
5.00
4.95
7
TIMEOUT (µs)
TIMEOUT (µs)
5.10
TIMEOUT (µs)
Timeout vs RTMR
Timeout vs Temperature
5.05
5.00
4.95
6
5
4
4.90
4.90
3
4.85
4.85
2
4.80
4.80
1
4.75
4.75
–50 –25
4
5
6
8
7
VCC (V)
9
10
11
3900 G01
50
25
0
75
TEMPERATURE (°C)
100
125
3900 G02
0
0
10 20 30 40 50 60 70 80 90 100
RTMR (kΩ)
3900 G03
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LTC3900
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TYPICAL PERFOR A CE CHARACTERISTICS
VCS(MAX) Clamp Voltage vs CS+
Input Current
18
17 VCC = 5V, 11V
16
15
14
13
12
11
10
9
8
7
6
5
4
3
0
25
50
75
–50 –25
TEMPERATURE (°C)
18
1.8
TA = 25°C
SYNC POSITIVE THRESHOLD (V)
16
15
14
13
12
11
100
10
125
0
10
5
CS
15
25
20
–1.4
–1.5
–1.6
–1.7
110
100
90
80
70
60
SYNC TO FG
125
4
5
6
7
8
9
Propagation Delay vs CLOAD
10
SYNC TO FG
TA = 25°C
CLOAD = 4.7nF
45
30
25
20
15
50
5
40
0
6
7
CLOAD (nF)
8
9
10
RISE TIME
0
25
50
75
100
125
VCC = 5V
CLOAD = 4.7nF
35
30
25
20
15
RISE TIME
10
FALL TIME
FALL TIME
5
4
5
6
7
8
9
10
11
VCC (V)
3900 G10
SYNC TO CG
40
35
10
SYNC TO CG
5
SYNC TO FG
Rise/Fall Time vs Temperature
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
70
4
60
50
45
80
3
70
3900 G09
40
2
80
Rise/Fall Time vs VCC
TA = 25°C
VCC = 5V
1
90
40
–50 –25
11
50
60
100
3900 G08
120
125
100
TEMPERATURE (°C)
3900 G07
90
75
VCC = 5V
CLOAD = 4.7nF
VCC (V)
100
50
50
SYNC TO CG
TEMPERATURE (°C)
110
25
Propagation Delay vs
Temperature
40
100
0
120
50
75
1.2
3900 G06
PROPAGATION DELAY (µs)
–1.3
50
VCC = 5V
1.3
TEMPERATURE (°C)
TA = 25°C
CLOAD = 4.7nF
110
PROPAGATION DELAY (µs)
SYNC NEGATIVE THRESHOLD (V)
–1.1
–1.2
VCC = 11V
1.4
1.0
–50 –25
30
+ INPUT CURRENT (mA)
120
VCC = 5V, 11V
25
1.5
Propagation Delay vs VCC
–1.0
0
1.6
3900 G05
SYNC Negative Threshold vs
Temperature
–1.8
–50 –25
1.7
1.1
3900 G04
PROPAGATION DELAY (µs)
SYNC Positive Threshold vs
Temperature
17
VCS(MAX) CLAMP VOLTAGE (V)
CURRENT SENSE THRESHOLD (mV)
Current Sense Threshold vs
Temperature
3900 G11
0
–50 –25
0
25
50
75
TEMPERATURE (°C)
100
125
3900 G12
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LTC3900
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TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout Threshold
Voltage vs Temperature
Rise/Fall Time vs Load
Capacitance
45
UNDERVOLTAGE LOCKOUT THRESHOLD
VOLTAGE (V)
TA = 25°C
VCC = 5V
35
30
25
20
RISE TIME
15
FALL TIME
10
5
0
0
1
2
3
4
5 6
CLOAD (nF)
7
8
9
10
20
CLOAD = 4.7nF
18
16
VCC = 11V
14
12
10
8
VCC = 5V
6
100
125
4
–50 –25
0
25
50
75
100
125
TEMPERATURE (°C)
3900 G13
3900 G14
3900 G15
VCC Supply Current vs Load
Capacitance
30
TA = 25°C
25
SUPPLY CURRENT (mA)
RISE/FALL TIME (ns)
40
4.5
4.4
4.3
4.2
RISING EDGE
4.1
4.0
3.9
3.8
3.7
3.6
3.5
FALLING EDGE
3.4
3.3
3.2
3.1
3.0
0
25
50
75
–50 –25
TEMPERATURE (°C)
VCC SUPPLY CURRENT (mA)
50
VCC Supply Current vs
Temperature
VCC = 11V
20
15
10
VCC = 5V
5
0
0
1
2
3
4
5 6
CLOAD (nF)
7
8
9
10
3900 G16
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LTC3900
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PI FU CTIO S
CS+, CS– (Pin 1, 2): Current Sense Differential Input.
Connect CS+ through a series resistor to the drain of the
external catch MOSFET, Q4. Connect CS– to the source.
The LTC3900 monitors the CS inputs 250ns after CG goes
high. If the inductor current reverses and flows into the
MOSFET causing CS+ to rise above CS– by more than
10.5mV, the LTC3900 pulls CG low. See the Current Sense
section for more details on choosing the resistance value
for RCS1 to RCS3.
CG (Pin 3): Catch MOSFET Gate Driver. This pin drives the
gate of the external N-channel catch MOSFET, Q4.
VCC (Pin 4): Main Supply Input. This pin powers the
drivers and the rest of the internal circuitry. Bypass this
pin to GND using a 4.7µF capacitor in close proximity to
the LTC3900.
FG (Pin 5): Forward MOSFET Gate Driver. This pin drives
the gate of the external N-channel forward MOSFET, Q3.
GND (Pin 6): The VCC bypass capacitor should be connected directly to this GND pin.
TIMER (Pin 7): Timer Input. Connect this pin to an external
R-C network to program the timeout period. The LTC3900
resets the timer at every negative transition of the SYNC
input. If the SYNC signal is missing or incorrect, the
LTC3900 pulls both CG and FG low once the TIMER pin
goes above the timeout threshold. See the Timer section
for more details on programming the timeout period.
SYNC (Pin 8): Driver Synchronization Input. This input is
signal edge sensitive. A negative voltage slew at SYNC
forces FG to pull high and CG to pull low. A positive voltage
slew at SYNC forces FG to pull low and CG to pull high. The
SYNC input can accept both pulse or square wave signals.
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BLOCK DIAGRA
S+
SYNC+
+1.4V
–1.4V
SYNC 8
CS + 1
CS – 2
–+
10.5mV
S–
SYNC
AND
DRIVER
LOGIC
DISABLE
DRIVER
ZCS
11V
5
FG
TIMER
RESET
3
CG
6
GND
UVLO
TMR
R1
180k
ZTMR
0.5 • VCC
MTMR
VCC
SYNC –
IS
TIMER 7
4
R2
45k
3900 BD
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LTC3900
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APPLICATIO S I FOR ATIO
Overview
In a typical forward converter topology, a power transformer is used to provide the functions of input/output
isolation and voltage step-down to achieve the required
low output voltage. Schottky diodes are often used on
the secondary-side to provide rectification. Schottky diodes, though easy to use, result in a loss of efficiency due
to relatively high voltage drops. To improve efficiency,
synchronous output rectifiers utilizing N-channel MOSFETs
can be used instead of Schottky diodes. The LTC3900
provides all of the necessary functions required to drive
the synchronous rectifier MOSFETs.
Figure 1 shows a simplified forward converter application.
T1 is the power transformer; Q1 is the primary-side power
transistor driven by the primary controller, LT1950 GATE
output. The pulse transformer T2 provides synchronization and is driven by either the inverted GATE output or a
synchronization signal, SG from the primary controller.
Q3 and Q4 are secondary-side synchronous switches
driven by the LTC3900’s FG and CG output. Inductor LO
and capacitor COUT form the output filter to provide a
steady DC output voltage for the load. Also shown in
Figure␣ 1 is the feedback path from VOUT through the
optocoupler driver LT1797 and an optocoupler, back to
the primary controller to regulate VOUT.
Each full cycle of the forward converter operation consists
of two periods. In the first period, Q1 turns on and the
primary-side delivers power to the load through T1. SG
goes low and T2 generates a negative pulse at the LTC3900
SYNC input. The LTC3900 forces FG to turn on and CG to
turn off, Q3 conducts. Current flows to the load through
Q3, T1 and LO. In the next period, Q1 turns off, SG goes
high and T2 generates a positive pulse at the LTC3900
SYNC input. The LTC3900 forces FG to turn off and CG to
turn on, Q4 conducts. Current continues to flow to the load
through Q4 and LO. Figure 2 shows the LTC3900 synchronization waveforms.
External MOSFET Protection
A programmable timer and a differential input current
sense comparator are included in the LTC3900 for protection of the external MOSFET during power down and Burst
Mode® operation. The chip also shuts off the MOSFETs if
VCC < 4.1V.
GATE
SG
SYNC
FG
CG
3900 F02
Figure 2. Synchronization Waveforms
When the primary controller is powering down, the primary controller shuts down first and the LTC3900 continues to operate for a while by drawing power from the VCC
bypass cap, CVCC. The SG signal stops switching and there
is no SYNC pulse to the LTC3900. The LTC3900 keeps one
of the drivers turned on depending on the polarity of the
last SYNC pulse. If the last SYNC pulse is positive, CG will
remain high and the catch MOSFET, Q4 will stay on. The
inductor current will start falling down to zero and continue going in the negative direction due to the voltage that
is still present across the output capacitor (the current
now flows from COUT back to LO). If Q4 is turned off while
the inductor current is negative, the inductor current will
produce high voltage across Q4, resulting in a MOSFET
avalanche. Depending on the amount of energy stored in
the inductor, this avalanche energy may damage Q4.
The timer circuit and current sense comparator in LTC3900
are used to prevent reverse current buildup in the output
inductor.
Timer
Figure 3 shows the LTC3900 timer internal and external
circuits. The timer operates by using an external R-C
charging network to program the time-out period. On
every negative transition at the SYNC input, the chip
generates a 200ns pulse to reset the timer cap. If the SYNC
signal is missing or incorrect, allowing the timer cap
voltage to go high, it shuts off both drivers once the
voltage reaches the time-out threshold. Figure 4 shows
the timer waveforms.
Burst Mode is a registered trademark of Linear Technology Corporation.
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LTC3900
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APPLICATIO S I FOR ATIO
R2
VCC
R1
MISSING/LOW
POSITIVE
SYNC PULSE
4
TIMER RESET AFTER
RECEIVING POSITIVE
SYNC PULSE
RTMR
TMR
SYNC
TIMEOUT
TIMER
RESET
TIMER DO NOT RESET
AT SECOND NEGATIVE
SYNC PULSE
7
ZTMR
FG
CTMR
CG
3900 F03
TIMER RESET
(INTERNAL)
Figure 3. Timer Circuit
TIMEOUT
TIMEOUT
THRESHOLD
SG
TIMER
SYNC
3900 F05
LAST
PULSE
FG
CG
Figure 5. Timer Waveforms with Incorrect SYNC Pulses
threshold of the comparators. This can cause only one of
the SYNC comparators to trip. This also appears as
incorrect SYNC pulse and the timer will not reset.
TIMER RESET
(INTERNAL)
TIMEOUT
THRESHOLD
TIMER
3900 F04
Figure 4. Timer Waveforms
A typical forward converter cycle always turns on Q3 and
Q4 alternately and the SYNC input should alternate between positive and negative pulses. The LTC3900 timer
also includes sequential logic to monitor the SYNC input
sequence. If after one negative pulse, the SYNC comparator receives another negative pulse, the LTC3900 will not
reset the timer cap. If no positive SYNC pulse appears,
both drivers are shut off once the timer times out. Once
positive pulses reappear the timer resets and the drivers
start switching again. This is to protect the external
components in situations where only negative SYNC pulse
is present and FG output remains high. Figure 5 shows the
timer waveforms with incorrect SYNC pulses.
The LTC3900 has two separate SYNC comparators (S+
and S– in the Block Diagram) to detect the positive and
negative pulses. The threshold voltages of both comparators are designed to be of the same magnitude (1.4V
typical) but opposite in polarity. In some situations, for
example during power up or power down, the SYNC pulse
magnitude may be low, slightly higher or lower than the
The timeout period is determined by the external RTMR and
CTMR values and is independent of the VCC voltage. This is
achieved by making the timeout threshold a ratio of VCC.
The ratio is 0.2x, set internally by R1 and R2 (see Figure 3).
The timeout period should be programmed to be around
1 period of the primary switching frequency using the
following formula:
TIMEOUT = 0.2 • RTMR • CTMR + 0.27E-6
To reduce error in the timeout setting due to the discharge
time, select CTMR between 100pF and 1000pF. Start with
a CTMR around 470pF and then calculate the required
RTMR. CTMR should be placed as close as possible to the
LTC3900 with minimum PCB trace between CTMR, the
TIMER pin and GND. This is to reduce any ringing caused
by the PCB trace inductance when CTMR discharges. This
ringing may introduce error to the timeout setting.
The timer input also includes a current sinking clamp
circuit (ZTMR in Figure 3) that clamps this pin to about
0.5 • VCC if there is missing SYNC/timer reset pulse. This
clamp circuit prevents the timer cap from getting fully
charged up to the rail, which results in a longer discharge
time. The current sinking capability of the circuit is around
1mA. The timeout function can be disabled by connecting
the timer pin to GND.
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LTC3900
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Current Sense
The differential input current sense comparator is used for
sensing the voltage across the drain-to-source terminals
of Q4 through the CS+ and CS– pins. If the inductor current
reverses into the Q4 causing CS+ to rise above CS– by
more than 10.5mV, the LTC3900 pulls CG low. This
comparator is used to prevent inductor reverse current
buildup during power down or Burst Mode operation,
which may cause damage to the MOSFET. The 10.5mV
input threshold has a positive temperature coefficient,
which closely matches the TC of the external MOSFET
RDS(ON). The current sense comparator is only active
250ns after CG goes high; this is to avoid any ringing
immediately after Q4 is switched on.
Under light load conditions, if the inductor average current
is less than half of its peak-to-peak ripple current, the
inductor current will reverse into Q4 during a portion of the
switching cycle, forcing CS+ to rise above CS–. The current
sense comparator input threshold is set at 10.5mV to
prevent tripping under light load conditions. If the product
of the inductor negative peak current and MOSFET RDS(ON)
is higher than 10.5mV, the LTC3900 will operate in discontinuous current mode. Figure 6 shows the LTC3900 operating in discontinuous current mode; the CG output goes
low before the next negative SYNC pulse, as soon as the
inductor current becomes negative. Discontinuous current mode is sometimes undesirable. To disable discontinuous current mode operation, add a resistor divider,
RCS1 and RCS2 at the CS+ pin to increase the 10.5mV
threshold so that the LTC3900 operates in continuous
mode at no load.
The LTC3900 CS+ pin has an internal current sinking
clamp circuit (ZCS in the Block Diagram) that clamps the
pin to 11V. The clamp circuit is to be used together with the
external series resistor, RCS1 to protect the CS+ pin from
high Q4 drain voltage in the power transfer cycle. During
the power transfer cycle, Q4 is off, the drain voltage of Q4
is determined by the primary input voltage and the transformer turns ratio. This voltage can be high and may
damage the LTC3900 if CS+ is connected directly to the
drain of Q4. The current sinking capability of the clamp
circuit is 5mA minimum.
The value of the resistors, RCS1, RCS2 and RCS3 should be
calculated using the following formulas to meet both the
threshold and clamp voltage requirements:
k = {48 • IRIPPLE • RDS(ON)} –1
RCS2 = {200 • VIN(MAX) • NS/NP –2200 • (1 + k)} /k
RCS1 = k • RCS2
RCS3 = {RCS1 • RCS2} / {RCS1 + RCS2}
If k = 0 or less than zero, RCS2 is not needed and RCS1
= RCS3 = {VIN(MAX) • (NS/NP) – 11V} / 5mA
where:
IRIPPLE = Inductor peak-to-peak ripple current
RDS(ON) = On-resistance of Q4 at IRIPPLE/2
VIN(MAX) = Primary side main supply maximum input
voltage
NS/NP = Power transformer T1, turn ratio
SG
SYNC
SYNC
FG
FG
CG
CG
INDUCTOR
CURRENT
INDUCTOR
CURRENT
0A
CURRENT SENSE
COMPARATOR TRIP
3900 F06a
Figure 6a. Discontinuous Current Mode Operation at No Load
0A
ADJUSTED CURRENT
SENSE THRESHOLD
3900 F06b
Figure 6b. Continuous Current Mode Operation
with Adjusted Current Sense Threshold
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APPLICATIO S I FOR ATIO
If the LTC3900 still operates in discontinuous mode with
the calculated resistance value, increase the value of RCS1
to raise the threshold. The resistors RCS1 and RCS2 and the
CS+ pins input capacitance plus the PCB trace capacitance
forms an R-C delay; this slows down the response time of
the comparator. The resistors and CS+ input leakage
currents also create an input offset error.
To minimize this delay and error, do not use resistance
value higher than required and make the PCB trace from
the resistors to the LTC3900 CS+/CS– pins as short as
possible. Add a series resistor, RCS3 with value equal to
parallel sum of RCS1 and RCS2 to the CS– pin and connect
the other end of RCS3 directly to the source of Q4.
SYNC Input
Figure 7 shows the external circuit for the LTC3900 SYNC
input. With a selected type of pulse transformers, the
values of the CSG and RSYNC should be adjusted to obtain
a optimum SYNC pulse amplitude and width. A bigger
capacitor, CSG, generates a higher and wider SYNC pulse.
The peak of this pulse should be much higher than the
typical LTC3900 SYNC threshold of ±1.4V. Amplitudes
greater than ±5V will help to speed up the SYNC comparator and reduce the SYNC to drivers propagation delay. The
pulse width should be wider than 75ns. Overshoot during
the pulse transformer reset interval must be minimized
and kept below the minimum SYNC threshold of ±1V. The
amount of overshoot can be reduced by having a smaller
RSYNC.
PRIMARY
CONTROLLER
SG
CSG
220pF
T2
LTC3900
SYNC
RSYNC
470Ω
T2: COILCRAFT Q4470B
OR PULSE P0926
3900 F06
Figure 7. SYNC Input Circuit
An alternative method of generating the SYNC pulse is
shown in Figure 8. This circuit produces square SYNC
pulses with amplitude dependent on the logic supply
voltage. The SYNC pulse width can be adjusted with R1
and C1 without affecting the pulse amplitude.
For nonisolated applications, the SYNC input can be driven
directly by a bipolar square pulse. To reduce the propaga-
tion delay, make the positive and negative magnitude of
the square wave much greater than the ±1.4V SYNC
threshold.
74HC14
PRIMARY
CONTROLLER
SG
74HC132
R1
470Ω
T2
LTC3900
SYNC
RSYNC
470Ω
74HC14
C1
220pF
SYNC
SG
3900 F07
Figure 8. Symmetrical SYNC Drive
VCC Regulator
The VCC supply for the LTC3900 can be generated by peak
rectifying the transformer secondary winding as shown in
Figure 9. The Zener diode DZ sets the output voltage to
(VZ – 0.7V). A resistor, RB (on the order of a few hundred
ohms), in series with the base of QREG may be required to
surpress high frequency oscillations depending on QREG’s
selection.
The LTC3900 has an UVLO detector that pulls the drivers
output low if VCC < 4.1V. The UVLO detector has 0.5V of
hysteresis to prevent chattering.
In a typical forward converter, the secondary-side circuits
have no power until the primary-side controller starts
operating. Since the power for biasing the LTC3900 is
derived from the power transformer T1, the LTC3900 will
initially remain off. During that period (VCC < 4.1V), the
output rectifier MOSFETs Q3 and Q4 will remain off and the
MOSFETs body diodes will conduct. The MOSFETs may
experience very high power dissipation due to a high
voltage drop in the body diodes. To prevent MOSFET
damage, VCC voltage greater than 4.1V should be provided
T1
SECONDARY
WINDING
D3
MBR0540
0.1µF
RZ
2k
RB
10Ω
DZ
7.5V
QREG
BCX55
VCC
CVCC
4.7µF
3900 F08
Figure 9. VCC Regulator
3900i
10
LTC3900
U
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W
U
APPLICATIO S I FOR ATIO
quickly. The VCC supply circuit shown in Figure 9 will
provide power for the LTC3900 within the first few switching pulses of the primary controller, preventing overheating of the MOSFETs.
MOSFET Selection
The required MOSFET RDS(ON) should be determined
based on allowable power dissipation and maximum required output current.
The body diodes conduct during the power-up phase,
when the LTC3900 VCC supply is ramping up. The CG and
FG signals stay low and the inductor current flows through
the body diodes. The body diodes must be able to handle
the load current during start-up until VCC reaches 4.1V.
The LTC3900 drivers dissipate power when switching
MOSFETs. The power dissipation increases with switching frequency, VCC and size of the MOSFETs. To calculate
the driver dissipation, the total gate charge QG is used.
This parameter is found on the MOSFET manufacturers
data sheet.
The power dissipated in each LTC3900 MOSFET driver is:
PDRIVER = QG • VCC • fSW
where fSW is the switching frequency of the converter.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3900 for your layout:
1. Connect the 4.7µF bypass capacitor as close as possible
to the VCC and GND pins.
2. Connect the two MOSFET drain terminals directly to the
transformer. The two MOSFET sources should be as close
together as possible.
3. Keep the timer, SYNC and VCC regulator circuit away
from the high current path of Q3, Q4 and T1.
4. Place the timer capacitor, CTMR as close as possible to
the LTC3900.
5. Keep the PCB trace from the resistors RCS1, RCS2 and
RCS3 to the LTC3900 CS+/CS– pins as short as possible.
Connect the other ends of the resistors directly to the drain
and source of the MOSFET, Q4.
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 ±.005
.189 – .197
(4.801 – 5.004)
NOTE 3
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.010 – .020
× 45°
(0.254 – 0.508)
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS
SHALL NOT EXCEED .006" (0.15mm)
.008 – .010
(0.203 – 0.254)
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.014 – .019
(0.355 – 0.483)
TYP
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
3900i
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LTC3900
U
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APPLICATIO S I FOR ATIO
36V TO 72V
INPUT
2
210k
3
4
5
0.1µF
6
7
R4, 18k
8
COMP
FB
VSEC
VIN
ROSC
BOOST
SYNC
PGND
SLOPE
VREF
VIN2
SHDN
GND
GATE
ISENSE
BLANK
10VBIAS
R7
120Ω
R6
18k
15
14
8 U2A
LTC1693-1
1
7
D1
BAS516
UV
11
CS
RS
0.015Ω
10k
10k
1
2
U2B
6
LTC1693-1
3
5
9
4
CG
T2
220pF
SYNC
7VBIAS
3
4
LTC3900
CS+
SYNC
CS–
TIMER
GND
CG
FG
VCC
8
SYNC
15k
7
7VBIAS
6
5
1nF
FG
560Ω
8.06k
+VO
CS
24.9k
3.3nF
4.7k
HCPL-M453
10VBIAS
6
1
5
2
4.7µF
BAT760
0.1µF
4
3
143k
270Ω
4.7k
100k
BC847BF
UV
PH5330E
BAT760
10VBIAS
10
27k
100k
C01
100µF
X5R
2×
47Ω
10nF
R9
470k
PH5330E CG
PHM12NQ20 FG
C4
1000pF
12
+VIN
2.2µF
100V
X5R
VO
3.3V
20A
2
1µF
13
C.PI-1365-1R2
7VBIAS
7VBIAS
5
1
4
10k
LT1797
2
COMP
+
1
LT1950
R5
470k
16
–VIN
–
4.7k
10VBIAS
+VIN
COMP
T1
PAYTON
50460
+VIN
3
4.7µF
LT1009
3900 F09
Figure 10. 36V t0 72V Input to 3.3V at 20A Synchronous Forward Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1693
High Speed Single/Dual N-Channel MOSFET Drivers
CMOS Compatible Input, VCC Range: 4.5V to 12V
LTC1698
Secondary Synchronous Rectifier Controller
Use with the LT1681, Optocoupler Driver, Pulse Transformer Synchronization
LT1950
Single Switch Controller
Used for 20W to 500W Forward Converters
LT3710
Secondary-Side Synchronous Post Regulator
For Regulated Auxiliary Output in Isolated DC/DC Converters
LT3781
“Bootstrap” Start Dual Transistor Synchronous
Forward Controller
72V Operation, Synchronous Switch Output
LT3804
Secondary Side Dual Output Controller
with Opto Driver
Regulates Two Secondary Outputs, Optocoupler Feedback Driver
and Second Output Synchronous Driver Controller
LTC3901
Secondary-Side Synchronous Driver for
Push-Pull and Full-Bridge Converter
Similar Function to LTC3900, Used in Full-Bridge and Push-Pull Converter
3900i
12
Linear Technology Corporation
LT/TP1103 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003