54AC11240, 74AC11240
OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS169 – MAY 1987 – REVISED APRIL 1993
•
•
•
•
•
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic SmallOutline Packages, Plastic Shrink
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11240 . . . JT PACKAGE
74AC11240 . . . DB, DW OR NT PACKAGE
(TOP VIEW)
t
1Y1
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
2Y2
2Y3
2Y4
description
The 54AC11240 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74AC11240 is characterized for
operation from – 40°C to 85°C.
1A1
1A2
1A3
1A4
2G
2A1
2A2
2A3
2A4
1
1
22
2
21
3
20
4
13
17
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
(TOP VIEW)
1A2
1A1
1G
NC
1Y1
1Y2
1Y3
EN
23
3
1G
1A1
1A2
1A3
1A4
VCC
VCC
2A1
2A2
2A3
2A4
2G
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
2A3
2A4
2G
NC
2Y4
2Y3
2Y2
1Y4
GND
GND
NC
GND
GND
2Y1
24
23
54AC11240 . . . FK PACKAGE
logic symbol†
1G
24
2
1A3
1A4
VCC
NC
VCC
2A1
2A2
These octal buffers/line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters. These devices provide inverting outputs and
symmetrical G (active-low output control) inputs.
These devices feature high fan-out and improved
fan-in.
1
NC – No internal connection
1Y1
1Y2
1Y3
FUNCTION TABLE
(each buffer)
1Y4
INPUTS
EN
1
16
9
10
15
11
14
12
2Y1
2Y2
G
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
2Y3
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
54AC11240, 74AC11240
OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS169 – MAY 1987 – REVISED APRIL 1993
logic diagram (positive logic)
1G
1A1
1A2
1A3
1A4
13
24
2G
23
1
22
2
21
3
20
4
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
17
9
16
10
15
11
14
12
2Y1
2Y2
2Y3
2Y4
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
54AC11240
VCC
VIH
Supply voltage
High-level input voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
Low-level input voltage
MAX
3
5
5.5
TA
Operating free-air temperature
MAX
3
5
5.5
3.15
3.15
3.85
VCC = 4.5 V
VCC = 5.5 V
0
Input
In
ut transition rise or fall rate
NOM
2.1
0
Low-level output current
MIN
2.1
Output voltage
Dt /Dv
2–2
NOM
Input voltage
High-level output current
74AC11240
MIN
VCC = 3 V
VCC = 4.5 V
3.85
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
0
VCC
VCC
–4
–4
– 24
– 24
– 24
– 24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
G
0
5
0
5
Data
0
10
0
10
– 55
125
– 40
85
• DALLAS, TEXAS 75265
V
V
VCC = 5.5 V
VCC = 3 V
POST OFFICE BOX 655303
UNIT
V
V
V
mA
mA
ns/ V
°C
54AC11240, 74AC11240
OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS169 – MAY 1987 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = – 50 mA
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 50 mA{
IOH = – 75 mA{
IOL = 24 mA
IOL = 50 mA{
IOL = 75 mA{
VO = VCC or GND
VI = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
MIN
MAX
74AC11240
MIN
3V
2.9
2.9
2.9
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
UNIT
V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
V
1.65
5.5 V
IO = 0
MAX
3.85
5.5 V
IOL = 12 mA
IOZ
II
54AC11240
4.5 V
5.5 V
IOL = 50 mA
VOL
TA = 25°C
MIN
TYP
MAX
1.65
5.5 V
± 0.5
± 10
±5
mA
5.5 V
± 0.1
±1
±1
mA
8
160
80
mA
5.5 V
5V
4
pF
CO
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
G
Y
tPHZ
tPLZ
G
Y
POST OFFICE BOX 655303
MIN
TA = 25°C
TYP
MAX
54AC11240
74AC11240
MIN
MAX
MIN
MAX
1.5
7.6
10.5
1.5
12.8
1.5
11.7
1.5
6.3
8.6
1.5
10.2
1.5
9.5
1.5
8.2
11.6
1.5
13.4
1.5
12.7
1.5
7.6
10.8
1.5
13
1.5
12
1.5
5.5
7.5
1.5
8.1
1.5
7.8
1.5
6.7
9.4
1.5
10
1.5
9.8
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
2–3
54AC11240, 74AC11240
OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS169 – MAY 1987 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
G
Y
tPHZ
tPLZ
G
Y
MIN
TA = 25°C
TYP
MAX
54AC11240
74AC11240
MIN
MAX
MIN
MAX
1.5
5.4
7.5
1.5
9
1.5
8.4
1.5
4.6
6.6
1.5
7.8
1.5
7.2
1.5
5.7
8.2
1.5
9.9
1.5
9.2
1.5
5.3
7.7
1.5
9.4
1.5
8.7
1.5
4.7
6.3
1.5
6.9
1.5
6.6
1.5
5.2
7.3
1.5
8
1.5
7.7
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per buffer
Outputs disabled
CL = 50 pF,
pF
TYP
39
f = 1 MHz
12
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
GND
LOAD CIRCUIT
Output
Control
(low-level
enabling)
VCC
50%
50%
0V
tPHL
tPLH
VOH
Output
S1
Open
2 × VCC
GND
500 Ω
CL = 50 pF
(see Note A)
Input
(see Note B)
Open
TEST
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
50% VCC
50% VCC
VOL
VCC
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
50%
50%
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated