AND8079/D A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator http://onsemi.com APPLICATION NOTE Prepared by: Jim Lepkowski Senior Application Engineer Vdd INTRODUCTION This application note describes a low cost power supply circuit for a DDR (Double Data Rate) memory system. The design is based on the NCP1570/NCP1571 low voltage synchronous buck converter. The reference design created to evaluate the system uses a 3.80″ by 2.15″ two layer printed circuit board, optimized for a small solution size at an economical cost. DDR memories bring new challenges to the power supply by requiring an efficient main power of 2.5 V (Vdd) and a second voltage (Vtt) that accurately tracks one half of Vdd (i.e. 1.25 V) that is capable of both sourcing and sinking current. In addition, a third voltage is required (VREF) that also tracks Vdd/2. A low voltage synchronous buck converter is used to create an 8.0 A output at 2.5 V, while the Vtt and VREF voltages are created using a unique operational amplifier linear regulator circuit. The demonstration circuit is designed for low power DDR systems such as desktop PCs, but the circuit’s output power capability can be increased with the selection of the external inductor and capacitors for high power systems such as PC workstations. Vtt = Vdd/2 RS Transmitter 22 VREF October, 2002 - Rev. 1 Receiver Figure 1. DDR Memory Simplified Schematic Vtt is equal to Vdd/2 instead of Vdd in order to save power. The power dissipated in the resistors is equal to voltage squared divided by the bus resistance, thus a termination voltage of Vdd/2 provides a factor of four power savings. The third voltage is used as a reference voltage to the differential amplifier input section of the receiver ICs. A summary of the specifications for the DDR memory system is listed below. The transient requirements are not defined in the industry JEDEC standards. DDR Memory Power Supply Requirements Figure 1 shows a simplified schematic of the DDR memory system. Voltage Vdd powers the memory ICs, in addition to the buffer interface circuits. The termination voltage Vtt is used for the pull-up resistors and must be able to either sink or source current. For example, if all of the driver circuits are at a logic high state (i.e. VOH = Vdd = 2.5 V), the Vtt supply will have to sink current in order to maintain its 1.25 V. In contrast, if all of the driver circuits are at a logic low state (i.e. VOL = Vss = 0 V), the Vtt supply will have to source current because the termination resistors will be effectively connected to ground. Semiconductor Components Industries, LLC, 2002 RT 25 1 DDR Voltage Output Voltage Tolerance Output Current Vdd 2.5 V 200 mV 8.0 A Vtt Vdd/2 (1.25 V) Vdd/2 3% (1.250 V 37.5 mV) 2.0 A (Sink and Source) VREF Vdd/2 Vtt 40 mV 5.0 mA Publication Order Number: AND8079/D AND8079/D The sink and source ability of the Vtt supply is provided by MOSFETs Q4 and Q5 which are used to extend the current capability of the operational amplifier circuit. When the Vtt supply is in the current sinking mode of operation, Q4 is “OFF” and Q5 is “ON”. The output of U2A will be at a negative voltage (i.e. –5.0 V) to control the Vgs of the P-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. In a similar manner, when the Vtt supply is in the current sourcing mode of operation, Q4 is “ON” and Q5 is “OFF”. The output of U2A will reach a positive voltage (i.e. + 4.5 V) to control the Vgs of the N-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. Resistor R7 is used to isolate the output of U2B from Vtt and the bulk capacitor C20. The slew rate of the operational amplifier and the ability of the bulk capacitors to hold the voltage at 1.25 V under the load conditions control the transient response of the Vtt control loop. Note that the bulk capacitors maintain the Vtt voltage at approximately 1.25 V; therefore, the operational amplifier is only required to slew its output a relatively small amount; therefore, the relatively slow slew rate of the LM358 operational amplifiers is not a limiting factor in the design. Many industry experts have predicted that DDR memory will soon become the standard for desktop computers, with notebooks shortly behind. Next generation DDR-II generation systems are likely to have a lower Vdd voltage of 1.8 V with a Vtt and VREF voltage equal to 900 mV. This lower voltage will be required to satisfy the consumer’s requirement for more memory without a large increase in required power. Supply Voltage (Vdd) The Vdd 2.5 V power supply is created with the NCP1571 low voltage synchronous buck controller. The NCP1571 controller contains the required circuitry for a synchronous N-channel MOSFET buck regulator. The V2 control method is used to achieve a fast 200 ns transient response and an output regulation of ±1.0%. The IC operates at a fixed internal frequency of 200 kHz. In addition, the NCP1571 provides the following features: undervoltage lockout protection, programmable soft start, power good signal with delay and overvoltage protection. Note the NCP1570 and NCP1571 are functionally and pin for pin equivalent. The NCP1571’s under voltage lockout operation (UVLO) feature has been modified for applications that require a parallel standby power supply in addition to the main power supplied by the buck converter. Standby Power Operation The demonstration PCB has the provision of providing a low power standby mode of operation to the DDR memory system. This mode could be used to provide a 2.5 V low current standby voltage to the memory ICs when the main 5.0 V input power is not available. A MC33375 (U3) 300 mA low dropout voltage regulator (LDO) was chosen for the design to provide the 2.5 V standby power. The MC33375 has an ON/OFF enable pin and is available in a SOT-223 package. The performance of the standby regulator was not verified. Q1, a N-Channel MOSFET, serves as a diode to prevent current flow back to the main 5.0 volt input power supply during the standby mode. The MOSFET was chosen instead of a Schottky diode in order to minimize the voltage drop and power consumption of the diode. Termination Supply Voltage (Vtt) and Reference Voltage (VREF) The Vtt supply voltage is equal to one half of the Vdd voltage, or approximately 1.25 V. Operational amplifiers U2A and U2B function as voltage followers to create the Vtt voltage. The input to U2B is created by the resistive voltage divider formed by R5 and R6 and divides the 2.5 V Vdd supply by two to form the VREF reference voltage. Also, U2B provides filtering to remove any of the high frequency switching noise that is results from the synchronous buck converter. The Vtt output of the circuit formed by U2A and transistors Q4 and Q5 tracks the voltage at the non-inverting terminal by virtue of the voltage follower circuit configuration. Thus, the output of voltage of the Vtt supply is referenced to 50% of the 2.5 V Vdd supply, rather than an absolute 1.25 V reference. http://onsemi.com 2 Q1 MTB1306 D2 PAK L1 1H TP5 C1 1800F 10V TP6 C2 1800F 10V C3 1800F 10V C5 1800F 10V Prov. C4 0.1F L2 2.2H D1 MBRM110LT PowerMite Prov. GND_Input TP7 12 V_Input 4 Q2 MTB1306 D2 PAK 5 V_Input To = 1.0% Q3 R1 10 U1 1 TP8 NCP1571 SO-8 VCC GND 2 V_Logic C13 0.01F 3 4 Vfb PWRGD PGDELAY GATE(L) COMP GATE(H) MTB1306 D2PAK 5 C6 100pF Q4 NTD4302 D2 PAK C16 VTT (+1.25V, 2A) C24 1F ON OFF 2 VOUT 3 GND TP2 4 3 V- 0.1F 1 OUT − + V_5P0_STBV 2 VDDQ (+2.5V, 8A) 6 C14 0.1F 1 VIN C11 C10 1800F 1800F 6.3V 6.3V C8 C9 1800F 0.1F 6.3V 7 MC33375ST-2.5T3 SOT-223 U3 Prov. TP9 C7 1800F 6.3V Prov. R4 13k V+ 8 C17 U2A LM358 Micro8 4 1.25V_Vtt R7 1k Q5 MTD20P03HDL DPAK 0.1F C18 C20 1800F 6.3V Prov. C21 C22 1800F 0.1F 6.3V Prov. C23 1800F 6.3V TP3 GND_Output VREF (+1.25V, 2mA) TP4 TP10 -12 V_Input Tol. = 1.0% R5 10K U2B LM358 6 0.15F − R8 200 7 + OUT 1.25V_Ref 5 Tol. = 1.0% R6 10K C15 1F R9 100 Note: The provisional components were not used in the verification of the reference design. Figure 2. DDR Memory Reference Design C19 2F AND8079/D 3 http://onsemi.com C12 0.1F R2 47k Tol = 1.0% 8 TP1 2.5V R3 20k AND8079/D Component Selection Output Capacitors The output capacitors are selected to meet the desired output ripple requirements. The key specifications for the capacitors are their ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). In order to obtain a good transient response, a combination of low value/high frequency ceramic capacitors and bulk electrolytic capacitors are placed as close to the load as possible. The voltage change during the load current transient is: Input Inductor The input inductor (LIN) is used to isolate the input power supply from the switching portion of the buck regulator. LIN also limits the inrush current into the bulk input capacitors and limits the input current slew rate that results from the transient load. The inductor blocks the ripple current and transfers the transient current requirement to the bulk input capacitor bank. The design equations for LIN are listed below and for connivance an inductance of 1.0 H is chosen. The cut-off frequency of the second order LC filter provides adequate attenuation for the 200 kHz switching frequency of the NCP1571. VOUT IOUT ESL ESR tr t COUT IOUT ESR Empirical data indicates that most of the output voltage change that results from the load current transients is determined by the capacitor ESR; therefore, the maximum allowable ESR can be approximated from the following equation. V LIN 5 V 2.5 V 5 s 1.25 H 10 A (dIdt)Max 1 1 2 1 H 5400 F 2 LIN CIN 216 Hz f 3db ESR max VOUT 75 mV 7.5 m 10 A IOUT where: LIN = input inductor CIN = bulk input capacitor(s) dI/dt = 10 A in 5.0 s The number of capacitors is calculated by using the equation listed below. Input Capacitors The input filter capacitors provide a charge reservoir that minimizes the supply voltage variations due to the pulsating current through the MOSFETs. The input capacitors are chosen primarily to meet the ripple current rating of the capacitors. The design equation is listed below. The ESR of the Rubycon 6.3 V 1800 F capacitors is specified at 19 m; therefore, 3 capacitors are used in the design. Number of capacitors ESRCAP 19 m 2.5 7.5 m ESR max MOSFET Selection The output switch MOSFETs are chosen based on the gate charge/gate-source threshold voltage, gate capacitance, on resistance, current rating and the thermal capacity of the package. In this DDR design, the MOSFETs were chosen for economical reasons and have a current and power rating that is much better than needed for this design. In addition, the MOSFETs selected were verified by measuring the thermal characteristics of the devices on the PCB. The power dissipation design equation for selecting the MOSFETs is given below. ICin(RMS) D (1 D) Iout2 .5 (1 .5) 102 5 A where: D = duty cycle = VOUT/VIN = 2.5 V/5.0 V = 0.5 IOUT = maximum output current The Rubycon 10 V 1800 f capacitors have a ripple current rating of 2.55 A. Thus only 2 of the capacitors are needed to meet the ripple requirements; however, 3 capacitors were chosen to be conservative. I VDS Tr FS P IMAX2 RDS(ON) D MAX 2 IMAX VDS Tf FS 2 Output Inductance The main criterion in selecting the output filter inductance (LOUT) is to provide a satisfactory response to the load transients. The inductance affects the output voltage ripple by limiting the rate at which the current can either increase or decrease. The design equation used for selecting LOUT is listed below. A 2.2 H inductor was chosen for the design. where: Tr = rise time or turn-on time of MOSFET Tf = fall time or turn-off time of MOSFET FS = switching frequency (VIN VOUT) tr (5 V 2.5 V) 10 s I 10 A 2.5 H LOUT where: tr = output transient load time http://onsemi.com 4 AND8079/D Experimental Results The experimental results of the demonstration PCB are shown in Figures 4 through 20. Figure 3 shows the test setup used to create the current load transients for the Vtt supply voltage. The transient current load tests for the Vdd and Vtt supply voltages were created using a Kikusui Electronic Load Controller. Unless noted, the standard test conditions are as listed below: 1. Ambient Temperature = 23C 2. Vdd Current Load (IVdd) = 8.0 A 3. Vtt Current Load (IVtt) = 1.25 A source load 4. VREF Current Load (IREF) = 2.5 mA 5. 5.0 V Input Voltage = 5.00 V 6. 12 V Input Voltage = 12.00 V 7. -12 V Input Voltage = -12.00 V Schottky Diode for Synchronous MOSFET The efficiency of the buck converter can be improved slightly by placing a Schottky diode (D1) in parallel with the bottom MOSFET (Q3). The body diode of Q3 is used to conduct current during the non-overlap time when both the top (Q2) and bottom (Q3) MOSFETs are turned OFF. But because the non-overlap time is only approximately 50 ns for the NCP1571’s 200 kHz switching speed, the efficiency savings will be only approximately 1.0%. The demonstration board included a provision for D 1; however, the performance of the circuit was not testing with this diode. 2.5 V Vdd Vtt DDR Circuit - Q4 2.0 A DC Current Source + VREF Vtt R7 OUT + + U2A + + C22 C23 Pulsating Current Source - Q5 Pulse Width = 100 ms Period = 200 ms l1 = 0 A l2 = 4.0 A Rise Time = 50 s Fall Time = 50 s DC Current Source DC Current Source 2 .0 A 2 .0 A 2.0 A 2.0 A Vtt Circuit Vtt Vtt Circuit 0A Vtt 4A Pulsating Current Source Pulsating Current Source 2.0 A Current Sink Test 2.0 A Current Source Test Figure 3. Vtt Transient Load Test Setup for a 2.0 A Sink to 2.0 A Source Test http://onsemi.com 5 AND8079/D 2.475 2.6 OUTPUT VOLTAGE (V) 2.4 2.470 Vdd Vdd VOLTAGE (V) 2.2 2.0 1.8 1.6 1.4 Vtt 2.465 2.460 2.455 2.450 2.445 1.2 Vref 1.0 0 Vdd 1.0 2.440 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 Vdd LOAD (A) Vdd LOAD (A) Figure 4. Output Voltage vs. Vdd Load Figure 5. Vdd Voltage vs. Vdd Load 8.0 2.6 1.234 1.232 VOLTAGE OUTPUT (V) 2.4 1.230 VOLTAGE (V) Vtt & Vref Vref 1.228 Vtt 1.226 1.224 1.222 1.220 1.218 Vdd 2.2 2.0 1.8 1.6 1.4 1.216 1.2 1.214 0 1.0 3.5 Vtt Vref 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 4.0 4.5 5.0 Vdd LOAD (A) 5.5 6.0 6.5 7.0 7.5 8.0 INPUT VOLTAGE (V) Figure 6. Vtt and Vref vs. Vdd Load Figure 7. Output Voltage vs. Input Voltage 0.90 0.82 0.85 0.81 EFFICIENCY EFFICIENCY (%) EFFICIENCY (%) 0.80 EFFICIENCY 0.80 0.75 0.70 0.79 0.78 0.77 0.76 0.65 0.75 0.60 0 1 2 3 4 5 6 Vdd LOAD CURRENT (A) 7 0.74 8 3 Figure 8. Efficiency vs. Vdd Load 4 5 6 7 8 INPUT VOLTAGE (V) 9 Figure 9. Efficiency vs. Input Voltage http://onsemi.com 6 10 AND8079/D Channel 1: L2 Inductor Voltage Channel 2: Bottom (Q3) Buck MOSFET Gate Drive Channel 3: Top (Q2) Buck MOSFET Gate Drive Figure 10. L2 Inductor Voltage, Top (Q2) and Bottom (Q3) Buck MOSFET Gate Drive Channel 1: Vdd ripple voltage Channel 2: Vtt ripple voltage Figure 11. Steady-State Vdd and Vtt with IVdd = 0.1 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com 7 AND8079/D Channel 1: VREF ripple voltage Figure 12. Steady-State VREF with IVdd = 0.1 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA Channel 1: Vdd ripple voltage Channel 2: Vtt ripple voltage Figure 13. Steady-State Vdd and Vtt with IVdd = 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com 8 AND8079/D Channel 1: VREF ripple voltage Figure 14. Steady-State VREF with IVdd = 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA Channel 1: Vdd ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A Figure 15. Vdd with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com 9 AND8079/D Channel 1: Vtt ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A Figure 16. Vtt with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA Channel 1: VREF ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A Figure 17. VREF with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com 10 AND8079/D Channel 1: Vdd ripple voltage Channel 2: Transient current load IVtt = 0 to 4.0 A sourcing (i.e. –2.0 A sinking to +2.0 A sourcing transient current load) Figure 18. Vdd with a Transient Load IVtt = -2.0 to +2.0 A, IVdd = 8.0 A and VREF = 2.45 mA Channel 1: Vtt ripple voltage Channel 2: Transient current load IVtt = 0 to 4.0 A sourcing (i.e. –2.0 A sinking to +2.0 A sourcing transient current load) Figure 19. Vtt with a Transient Load IVtt = -2.0 to +2.0 A, IVdd = 8.0 A and VREF = 2.45 mA http://onsemi.com 11 AND8079/D Channel 1: 5.0 V Input Voltage Channel 2: Transient current load of IVdd = 0 to 8.0 A Figure 20. Switching Noise Reflected to the 5.0 V Input Power Supply with a Transient Load IVdd = 0 to 8.0 A, IVtt = 0 to 4.0 A Sourcing (i.e. –2.0 A Sinking to +2.0 A Sourcing Transient Current Load) and VREF = 2.45 mA Table 1: Component temperature measured in still air at an ambient temperature of 23C. The load conditions were: 1. Vdd Transient current load IVdd = 0 to 8.0 A 2. Vtt Transient current load IVtt = 0 to 4.0 A sourcing (i.e. –2.0 A sinking to +2.0 A sourcing transient current load) 3. Steady state VREF current load IREF = 2.5 mA Table 1. Circuit Component Temperature (C) Vdd FET Diode (Q1) 41.6 Vdd Top FET (Q2) 54.2 Vdd Bottom FET (Q3) 56.4 Vdd Input Inductor (L1) 42.1 Vdd Output Inductor (L2) 57.9 Vdd Input Capacitor (C2) 33.0 Vdd Output Capacitor (C10) 31.2 Vdd NCP1571 (U1) 55.0 Vtt LM358 (U2) 46.2 Vtt Top FET (Q4) 42.1 Vtt Bottom FET (Q5) 49.3 http://onsemi.com 12 AND8079/D DEMONSTRATION DESIGN PCB Figure 21. Component Layout Figure 22. TopSide of PCB (layer 1) http://onsemi.com 13 AND8079/D Figure 23. Bottom Side of PCB (layer 2) http://onsemi.com 14 AND8079/D 3.80 2.15 0 0.125 0 0.125 Figure 24. Drill Plot Size Qty. 62 5 38 22 62 2 18 41 125 5 http://onsemi.com 15 Symbol AND8079/D Table 2. Demonstration Board Bill of Materials Item Quantity Part Part No. Package Mfg. Comments 1 4 C1, C2, C3, C5 1800 F, 10 V MBZ Series see data sheet Rubycon C5 is provisional 2 7 C7, C8, C10, C11, C20, C21, C23 1800 F, 6.3 V MBZ Series see data sheet Rubycon C7, C20 and C21 are provisional 3 7 C4, C9, C12, C14, C16, C17, C22 0.1 F - SMT 1206 - - 4 1 C6 100 pF - SMT O805 - - 5 1 C18 0.15 F - SMT 1206 - - 6 1 C13 0.01 F - SMT O805 - - 7 1 C15 1.0 F - SMT O805 - - 8 1 C19 2.0 F - SMT O805 - - 9 1 L1 1.0 H DO3316P-102HC see data sheet Coilcraft - 10 1 L2 2.2 H DO5022P-222HC see data sheet Coilcraft - 11 3 Q1, Q2, Q3 N-Channel Mosfet MTB1306 D2PAK ON Semiconductor - 12 1 Q4 N-Channel Mosfet NTD4302 DPAK Bent Lead ON Semiconductor - 13 1 Q5 P-Channel Mosfet MTD20P03HDL DPAK Bent Lead ON Semiconductor - 14 1 R1 10 ohm - SMT O805 - - 15 1 R2 47 Kohm - SMT O805 - - 16 1 R3 20 Kohm - SMT O805 - - 17 1 R4 13 Kohm - SMT O805 - - 18 2 R5, R6 10 Kohm - SMT O805 - - 19 1 R7 1.0 Kohm - SMT O805 - - 20 1 R8 200 ohm - SMT O805 - - 21 1 R9 100 ohm - SMT O805 - - 22 1 U1 Sync. Buck Controller NCP1571 SO-8 ON Semiconductor - 23 1 U2 Op-Amp LM358DMR2 Micro-8 ON Semiconductor - 24 1 U3 LDO Regulator MC33375ST-2.5T3 SOT-223 ON Semiconductor U3 is provisional 25 1 D1 Schottky Diode MBRM110LT PowerMite ON Semiconductor D1 is provisional NOTE: Reference The provisional components were not used in the verification of the reference design. Acknowledgement The author would like to acknowledge Tod Schiff’s assistance in designing the linear Vdd circuit. http://onsemi.com 16 AND8079/D Notes http://onsemi.com 17 AND8079/D Notes http://onsemi.com 18 AND8079/D Notes http://onsemi.com 19 AND8079/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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