a Synchronous Buck Controller with Dual Linear Regulator Controllers ADP3171 FEATURES Fixed 1.2 V N-Channel Synchronous Buck Driver Two On-Board Linear Regulator Controllers Total Accuracy ±1% over Temperature High Efficiency Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Switching Output with No Additional External Components FUNCTIONAL BLOCK DIAGRAM VCC CT 8 UVLO AND BIAS OSCILLATOR SET RESET CROWBAR REFERENCE DRVH PWM LOGIC DRVL REF GND 1 DAC +20% APPLICATIONS Auxiliary System Supplies for Desktop Computer Systems General-Purpose Low Voltage Supplies 1.5V PWRGD LRFB1 3 LRDRV1 4 DAC –20% 1.8V CS– LRFB2 CMP 7 CS+ LRDRV2 5 FB gm COMP 1.2V ADP3171 GENERAL DESCRIPTION The ADP3171 is a highly efficient output synchronous buck switching regulator controller optimized for converting a 5 V main supply into the auxiliary supply voltages required by processors and chipsets. The ADP3171 provides a fixed output voltage of 1.2 V at up to 15 A, depending on the power ratings of the external MOSFETs and inductor. The ADP3171 uses a current-mode, constant off time architecture to drive two N-channel MOSFETs at a programmable switching frequency that can be optimized for regulator size and efficiency. The ADP3171 contains two fixed output voltage linear regulator controllers that are designed to drive external N-channel MOSFETs. These linear regulators are used to generate the auxiliary voltages required in most motherboard designs and have been designed to provide a high bandwidth load-transient response. The ADP3171 is specified over the commercial temperature range of 0°C to 70°C and is available in a 14-lead SOIC package. The ADP3171 provides accurate and reliable short circuit protection and adjustable current limiting. It also includes an integrated overvoltage crowbar function to protect the load in case the output voltage exceeds the nominal programmed voltage by more than 20%. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3171–SPECIFICATIONS1(V Parameter = 12 V, TA = 0C to 70C, unless otherwise noted.) Symbol Conditions Min VFB ∆VOUT VCROWBAR Figure 1 VCC = 10 V to 14 V % of Nominal FB Voltage % of Nominal FB Voltage Overvoltage to DRVL Going High 1.188 1.2 0.06 115 120 40 50 400 TA = 25°C, CT = 200 pF TA = 25°C, VOUT in Regulation TA = 25°C, VOUT = 0 V 3.5 130 25 FEEDBACK INPUT Output Accuracy Line Regulation Crowbar Trip Point Crowbar Reset Point Crowbar Response Time tCROWBAR OSCILLATOR Off Time CT Charge Current ICT ERROR AMPLIFIER Output Resistance Transconductance Output Current Maximum Output Voltage Output Disable Threshold –3 dB Bandwidth RO(ERR) gm(ERR) IO(ERR) VCOMP(MAX) VCOMP(OFF) BWERR CURRENT SENSE Threshold Voltage VCS(TH) Input Bias Current Response Time CC ICS+, ICS– tCS 2.05 FB Forced to VOUT – 3% FB Forced to VOUT – 3% 600 COMP = Open FB Forced to VOUT – 3% FB ≤ 0.45 V 0.8 V ≤ COMP ≤ 1 V CS+ = CS– = VOUT CS+ – (CS–) > 87 mV to DRVH Going Low 69 35 OUTPUT DRIVERS Output Resistance Output Transition Time RO(DRV(X)) t R , tF IL = 50 mA CL = 3000 pF LINEAR REGULATORS Feedback Current LR1 Feedback Voltage LR2 Feedback Voltage Driver Output Voltage ILRFB(X) VLRFB(1) VLRFB(2) VLRDRV(X) Figure 2, VCC = 4.5 V to 12.6 V Figure 2, VCC = 4.5 V to 12.6 V VCC = 4.5 V, VLRFB(X) = 0 V 1.45 1.75 4.2 % of Nominal FB Voltage % of Nominal FB Voltage % of Nominal FB Voltage % of Nominal FB Voltage IPWRGD(SINK) = 1 mA 75 POWER GOOD COMPARATOR Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold Overvoltage Reset Point Output Voltage Low Response Time SUPPLY DC Supply Current2 UVLO Threshold Voltage UVLO Hysteresis VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) ICC VUVLO Typ 4 150 35 130 2.2 625 3.0 750 500 78 45 1 0.5 50 Max Unit 1.212 V % % % ns 125 60 4.5 170 45 2.35 900 87 54 5 5 6.75 0.8 kΩ mmho µA V mV kHz mV mV mV µA ns Ω ns 6 80 115 40 µs µA µA 0.3 1.5 1.8 1 1.55 1.85 µA V V V 80 5 120 50 250 250 85 % % % % mV ns 7 7 1 125 60 500 9 7.25 1.2 mA V V NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs. Specifications subject to change without notice. –2– REV. 0 ADP3171 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 GND Ground Reference. GND should have a low impedance path to the source of the synchronous MOSFET. 2 PWRGD Power Good Indicator. Open-drain output that signals when the output voltage is in the proper operating range. 3, 11 LRFB1, LRFB2 Feedback connections for the fixed output voltage linear regulator controllers. 4, 10 LRDRV1, LRDRV2 Gate drives for the respective linear regulator N-channel MOSFETs. 5 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. 6 CS– Current Sense Negative Node. Negative input for the current comparator. 7 CS+ Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS–. 8 CT Timing Capacitor. An external capacitor connected from CT to ground sets the off time of the device. 9 COMP Error Amplifier Output and Compensation Point. The voltage at this output programs the output current control level between CS+ and CS–. 12 VCC Supply Voltage for the ADP3171. 13 DRVL Low-Side MOSFET Drive. Gate drive for the synchronous rectifier N-channel MOSFET. The voltage at DRVL swings from GND to VCC. 14 DRVH High-Side MOSFET Drive. Gate drive for the buck switch N-channel MOSFET. The voltage at DRVH swings from GND to VCC. ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V DRVH, DRVL, LRDRV1, LRDRV2 . . . . . . –0.3 V to VCC + 0.3 V All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V Operating Ambient Temperature Range . . . . . . . 0°C to 70°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C GND 1 14 DRVH PWRGD 2 13 DRVL LRFB1 3 12 VCC LRDRV1 4 ADP3171 LRFB2 TOP VIEW FB 5 (Not to Scale) 10 LRDRV2 11 CS– 6 9 COMP 7 8 CT CS+ *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND. ORDERING GUIDE Model Temperature Range Package Option ADP3171JR 0ºC to 70ºC SO-14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3171 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADP3171–Typical Performance Characteristics 60 SUPPLY CURRENT – mA 50 40 30 20 10 2 0 CH1 = 2.0V 0 200 400 600 OSCILLATOR FREQUENCY – kHz CH2 = 2.0V M = 100ns A: CH1 = 5.88V 800 TPC 1. Supply Current vs. Operating Frequency Using MOSFETs of Figure 3 TPC 3. Driver Transition Waveforms Using MOSFETs of Figure 3 1 1 2 2 CH1 = 5.0V CH2 = 5.0V M = 1.0s A: CH1 = 5.9V CH1 = 5.0V TPC 2. Gate Switching Waveforms Using MOSFETs of Figure 3 CH2 = 500mV M = 10.0ms A: CH1 = 5.9V TPC 4. Power-On Start-Up Waveform –4– REV. 0 ADP3171 Test Circuits ADP3171 1 GND DRVH 14 2 PWRGD DRVL 13 3 LRFB1 4 LRDRV1 VCS– 5 FB 6 CS– VCC 12 LRFB2 11 ADP3171 12V + 1F 100nF VLR1 LRDRV2 10 DRVH 14 2 PWRGD DRVL 13 3 LRFB1 4 LRDRV1 COMP 9 100 7 CS+ 1 GND 10nF CT 8 100nF AD820 5 FB VCC + VCC 12 LRFB2 11 1F 100nF VLR2 LRDRV2 10 6 CS– COMP 9 7 CS+ CT 8 10nF 1.2V Figure 2. Linear Regulator Output Voltage Accuracy Test Circuit Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high. THEORY OF OPERATION The ADP3171 uses a current-mode, constant off time control technique to switch a pair of external N-channel MOSFETs in a synchronous buck topology. Constant off time operation offers several performance advantages, including the fact that no slope compensation is required for stable operation. A unique feature of the constant off time control technique is that since the off time is fixed, the converter’s switching frequency is a function of the ratio of input voltage to output voltage. The fixed off time is programmed by the value of an external capacitor connected to the CT pin. The on time varies in such a way that a regulated output voltage is maintained as described below in the cycle-bycycle operation. Under fixed operating conditions, the on time does not vary, and it varies only slightly as a function of load. This means that switching frequency is fairly constant in most applications. Output Crowbar An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 20% greater than the targeted value, the ADP3171 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus protect the load from overvoltage destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output exceeds 1.44 V, the crowbar will turn on the lower MOSFET. If the output is then pulled down to less than 0.6 V, the crowbar will release, allowing the output voltage to recover to 1.2 V if the fault condition has been removed. Cycle-by-Cycle Operation On-Board Linear Regulator Controllers During normal operation (when the output voltage is regulated), the voltage error amplifier and the current comparator are the main control elements. During the on time of the high side MOSFET, the current comparator monitors the voltage between the CS+ and CS– pins. When the voltage level between the two pins reaches the threshold level, the DRVH output is switched to ground, which turns off the high side MOSFET. The timing capacitor CT is then charged at a rate determined by the off time controller. While the timing capacitor is charging, the DRVL output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has charged to the upper threshold voltage level, a comparator resets a latch. The output of the latch forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage error amplifier, which, in turn, leads to an increase in the current comparator threshold, thus tracking the load current. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver The ADP3171 includes two linear regulator controllers to provide a low cost solution for generating additional supply rails. These regulators are internally set to 1.5 V (LR1) and 1.8 V (LR2). The output voltage is sensed by the high input impedance LRFB(x) pin and compared to an internal fixed reference. The LRDRV(x) pin controls the gate of an external N-channel MOSFET, resulting in a negative feedback loop. The only additional components required are a capacitor and a resistor for stability. Higher output voltages can be generated by placing a resistor divider between the linear regulator output and its respective LRFB pin. The maximum output load current is determined by the size and thermal impedance of the external power MOSFET that is placed in series with the supply and controlled by the ADP3171. The linear regulator controllers have been designed so that they remain active even when the switching controller is in UVLO mode to ensure that the output voltages of the linear regulators will track the 3.3 V supply as required by Intel® design specifications. By diode OR-ing the VCC input of the IC to the 5 VSB and 12 V supplies as shown in Figure 3, the switching output will Intel is a registered trademark of Intel Corporation. REV. 0 –5– ADP3171 5V + C5 1000F D1 MBR052LT1 C8 22F 5VSB + C7 100nF C6 4.7F L1 1.7H R6 7.5m 820F 4 7.5m ESR (EACH) 1.5V, 5A 12V D2 MBR052LT1 1 GND DRVH 14 2 PWRGD DRVL 13 3 LRFB1 4 LRDRV1 5VSB C1 1F 5 FB Q1 2N7000 Q2 FDS6982 C14 C15 C16 C17 VCC 12 LRFB2 11 R8 10k LRDRV2 10 6 CS– COMP 9 7 CS+ CT 8 C10 100pF C9 150pF C2 10F R9 8.25k 5VSB Q3 IRFU014 C12 1F + 3.3VSB, 1.5A C13 220F R1 220 C3 1nF R2 220 C3 100pF R3 R4 1k 249 1.5VSB, 35mA Figure 3. Pentium® III Auxiliary Supply Generating 1.5 V, 1.5 V Standby, and 3.3 V Standby be disabled in standby mode, but the linear regulators will begin conducting once VCC rises above about 1 V. During startup, the linear outputs will track the 3.3 V supply up until they reach their respective regulation points, regardless of the state of the 12 V supply. Once the 12 V supply has exceeded the 5 VSB supply, the controller IC will track the 12 V supply. Once the 12 V supply has risen above the UVLO value, the switching regulator will begin its start-up sequence. V 1 tOFF = 1 – OUT × VIN f NOM (1) 1.5 V 1 tOFF = 1 – × = 3.5 µs 5 V 200 kHz The timing capacitor can be calculated from the equation: APPLICATION INFORMATION Specifications for a Design Example The design parameters for a typical auxiliary supply for a Pentium III application (shown in Figure 3) are as follows: CT = tOFF × I CT 3.5 µs × 150 µA = = 175 pF VT(TH) 3V f MIN = VIN – IO ( MAX ) × (RDS ( ON )HSF + RSENSE + RL ) – VOUT 1 × tOFF VIN – IO ( MAX ) × (RDS ( ON )HSF + RSENSE + RL – RDS ( ON )LSF ) f MIN = 1 5V – 5 A × (15 mΩ + 7.5 mΩ + 3 mΩ) – 1.5V = 192 kHz × 3.5 µs 5V – 5 A × (15 mΩ + 7.5 mΩ + 3 mΩ – 28 mΩ) Input Voltage: (VIN) = 5 V Auxiliary Input: (VCC) = 12 V Main Output: (VOUT) = 1.5 V @ 5 A (2) (3) The nearest standard value is 150 pF. The converter operates at the nominal operating frequency only at the above specified VOUT and at light load. At higher values of VOUT, or under heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VOUT = 1.5 V is calculated to be 192 kHz (see Equation 3), where: LDO 1 Output: (1.5 VSB) = 1.5 V @ 35 mA LDO 2 Output: (3.3 VSB) = 3.3 V @ 1.5 A CT Selection for Operating Frequency The ADP3171 uses a constant off time architecture, with tOFF determined by an external timing capacitor CT. Each time the high side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 0 V. During the off time, CT is charged by a constant current of 150 µA. Once CT reaches 3.0 V, a new on time cycle is initiated. The value of the off time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency (fNOM) of 200 kHz at an output voltage of 1.5 V, the corresponding off time is: RDS(ON)HSF is the resistance of the high side MOSFET (estimated value: 15 mΩ) RDS(ON)LSF is the resistance of the low side MOSFET (estimated value: 28 mΩ) RSENSE is the resistance of the sense resistor (estimated value: 7.5 mΩ) RL is the resistance of the inductor (estimated value: 3 mΩ) Pentium is a registered trademark of Intel Corporation. –6– REV. 0 ADP3171 Inductance Selection Selecting a Standard Inductor The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs but allows using smaller size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor, and input and output voltages: The companies listed in Table II can provide design consultation and deliver power inductors optimized for high power applications upon request. L= VOUT × tOFF I L ( RIPPLE ) Table II. Power Inductor Manufacturers Coilcraft (847) 639-6400 www.coilcraft.com Coiltronics (561) 752-5000 www.coiltronics.com Sumida Electric Company (510) 668-0660 www.sumida.com (4) For 2.5 A peak-to-peak ripple current, which corresponds to approximately 50% of the 5 A full-load dc current in an inductor, Equation 4 yields an inductance of: Vishay-Dale (203) 452-5664 www.vishay.com RSENSE 1.5V × 3.5 µs = 2.1 µH L= 2.5 A The value of RSENSE is based on the required maximum output current. The current comparator of the ADP3171 has a minimum threshold of 69 mV. Note that this minimum value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and transients. A 1.7 µH inductor can be used, which gives a calculated ripple current of 3 A at no load. The inductor should not saturate at the peak current of 8 A and should be able to handle the sum of the power dissipation caused by the average current of 5 A in the winding and the core loss. The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO(MAX), which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE allowing a 20% margin for overhead and using the minimum current sense threshold of 69 mV yields: Designing an Inductor Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool Mu® from Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low-frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. RSENSE = VCS (TH )( MIN ) 69 mV = = 10.6 mΩ IRIPPLE 3A 5 A+ IO ( MAX ) + 2 2 In this case, 7.5 m⍀ was chosen to provide ample headroom. Once RSENSE has been chosen, the maximum output current at the point where current limit is reached, IOUT(CL), can be calculated using the maximum current sense threshold of 87 mV: Two main core types can be used in this application. Open magnetic loop types such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor. Closed-loop types such as pot cores, PQ, U, and E cores, or toroids, cost more but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape. IOUT ( CL ) = IOUT ( CL ) VCS (TH )( MAX ) RSENSE – IL ( RIPPLE ) 2 87 mV 3A = – = 10.1 A 7.5 mΩ 2 (6) At output voltages below 450 mV, the current sense threshold is reduced to 54 mV, and the ripple current is negligible. Therefore, the worst-case dead short output current is reduced to: There are many useful references for quickly designing a power inductor. Table I gives some examples. IOUT ( SC ) = VCS ( SC ) RSENSE Table I. Magnetics Design References = 54 mV = 7.2 A 7.5 mΩ (7) To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least: Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for High-Frequency DCDC Converters; by William T. McLyman, Kg Magnetics ISBN 1-883107-00-08 REV. 0 (5) 2 PRSENSE = IO × RSENSE = 5 A2 × 7.5 mΩ = 188 mW –7– (8) ADP3171 Setting the Switcher Output Voltage Feedback Loop Compensation Design For this example, the resistor divider R3 and R4 set the output voltage at 1.5 V by comparing the divided-down output to the internal 1.2 V reference using: Once the output capacitor COUT and ESR values have been chosen, the output circuit’s pole (fP) and zero (fZ) frequencies can be calculated using: R4 VOUT = VREF × 1 + R3 fP = (9) COUT Selection fZ = The selection of COUT is driven by the required effective series resistance (ESR) and the desired output ripple. A good rule of thumb is to limit the ripple voltage to 1% of the nominal output voltage. It is assumed that the total ripple has two main contributors: 25% from the COUT bulk capacitance value and 75% from the COUT ESR value. The correct value for COUT can be determined by: COUT ∆I ×t = OUT OFF 0.25 × ∆VPP (10) 0.75 × ∆VPP ∆IOUT (11) VOUT × tOFF LOUT (15) VOUT IOUT (16) For this example: 1.5V = 0.3 Ω 5A 1 fP = = 160 Hz 2 π × 3280 µF × (0.3 Ω + 3 mΩ) 1 fP = = 16.2 kHz 2 π × 3280 µF × 3 mΩ ROUT = (12) The compensation circuit is simply a capacitor (CC) connected to the COMP pin. This makes the converter have a fast dynamic response to load changes. (13) The switching frequency of the converter is 200 kHz. The crossover frequency (fC) should be chosen at one-third the switching frequency, or 70 kHz. The total gain of the compensation circuit (K) is: and: ∆VPP = 0.01 × VOUT 2 π × COUT × ESR ROUT = where: ∆IOUT = 1 (14) where: and: ESR = 1 2 π × COUT × (ROUT + ESR ) Solving for this example: K = ∆VPP = 0.01 × 1.5V = 15 mV 1.5V × 3.5 µs =3A 1.7 µH 0.75 × 15 mV ESR = = 3.75 mΩ 3A 3 A × 3.5 µs COUT = = 2800 µF 0.25 × 15 mV ∆IOUT = gm 2 π × ni × C × RS × fC (17) where error amplifier transconductance (gm) is 2.2 mmho, the error amplifier gain (ni) is 25, and the sense resistor (RS) is 7.5 mΩ. The value of K is determined using the gain of the power output circuit at fC. The relationship between gain (GO) at fC, ESR, and K is: GO = ESR K × GO = 1 Four OSCON 820 µF/4 V capacitors would meet these requirements, giving a total capacitance of 3280 µF and an ESR of 3 mΩ. Manufacturers such as Vishay, AVX, Elna, WIMA, and Sanyo provide good high-performance capacitors. Sanyo’s OSCON capacitors have lower ESR for a given size at a somewhat higher price. Choosing sufficient capacitors to meet the ESR requirement for COUT will normally exceed the amount needed to meet the ripple current requirement. K = 1 1 = GO ESR (18) As K is now known, the value of CC can be determined by rearranging Equation 17 as follows: g m × ESR 2 π × ni × RS × fC 2.2 mmho × 3 mΩ CC = = 80 pF 2 π × 25 × 7.5 mΩ × 70 kHz CC = (19) The closest standard value is 100 pF. –8– REV. 0 ADP3171 With this choice, the high-side MOSFET dissipation is: Power MOSFETs Two external N-channel power MOSFETs must be selected for use with the ADP3171, one for the main switch and one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)), the ON resistance (RDS(ON)), and the gate charge (QG). Logic level MOSFETs are highly recommended. Only logic level MOSFETs with VGS ratings higher than the absolute maximum value of VCC should be used. 2 PHSF = RDS ( ON )HSF × IHSF ( MAX ) + 5 + 6.25 A × 12 nC × 192 kHz 2×1A +5V × 19 nC × 192 kHz = 349 mW where the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate turn-off current. From the data sheet, the value of QG for the FDS6982 is 12 nC and the peak gate drive current provided by the ADP3171 is about 1 A. In the third term, QRR is the charge stored in the body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDS6982 shows a value of 19 nC for this parameter. The maximum duty ratio of the low-side (synchronous rectifier) MOSFET is: DLSF ( MAX ) = 1 – DHSF ( MAX ) = 67% The low-side MOSFET dissipation is: (21) PLSF = RDS ( ON )LSF × ILSF ( MAX ) The maximum rms current of the high-side MOSFET is: IHSF ( MAX ) = 0.33 × IL ( VALLEY ) + ( IL ( VALLEY ) × IL ( PEAK ) ) + IL ( PEAK ) Note that there are no switching losses in the low-side MOSFET. (22) CIN Selection and Input Current di/dt Reduction (23) In continuous inductor-current mode, the source current of the high-side MOSFET is a square wave with a duty ratio of VOUT/VlN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: The maximum rms current of the low-side MOSFET is: 2 ILSF ( MAX ) = 0.67 × 2 IL ( VALLEY ) + ( IL ( VALLEY ) × IL ( PEAK ) ) + IL ( PEAK ) ) 3 ( 3.75 A2 + ( 3.75 A × 6.25 A ) + 6.25 A2 3 ) = 4.1 A IC ( RMS ) = IO × DHSF – DHSF PD ( FETs ) = 0.1 × 1.5V × 6.5 A = 975 mW RDS ( ON )LSF = PD ( FETs ) 3 × IHSF ( MAX ) PD ( FETs ) 2 × ILSF ( MAX ) 2 2 = = 975 mW = 38 mΩ 3 × 2.9 A2 975 mW = 29 mΩ 2 × 4.1 A2 (24) The ripple voltage across the input capacitor is: ESRC DHSF ( MAX ) VC ( RIPPLE ) = IO × + n n C C × CIN × f MIN (25) VC ( RIPPLE ) 24 mΩ 0.33 = IO × + = 26 mV 1 × 1 mF × 192 kHz 1 (30) Linear Regulators The linear regulators provide a low-cost, convenient, and versatile solution for generating moderate current supply rails. The maximum output load current is determined by the size and thermal impedance of the external N-channel power MOSFET that is placed in series with the supply and controlled by the ADP3171. The output voltage is sensed at the LRFB × pin and compared to an internal reference voltage in a negative feedback loop that keeps the output voltage in regulation. If the load is reduced or (26) Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow higher efficiency, but increase the system cost. A Fairchild FDB6982 dual MOSFET (high-side RDS(ON) = 28 mΩ nominal, 35 mΩ worst-case; and low-side RDS(ON) = 16 mΩ nominal, 22 mΩ worst-case) is a good choice in this application. REV. 0 (29) For a ZA-type capacitor with 1000 µF capacitance and 6.3 V voltage rating, the ESR is 24 mΩ and the maximum allowable ripple current at 100 kHz is 2 A. At 105°C, at least two such capacitors should be connected in parallel to handle the calculated ripple current. At 50°C ambient, however, a higher ripple current can be tolerated, so one capacitor is adequate. Allocating half of the total dissipation for the high-side MOSFET and half for the low-side MOSFET, and assuming that the resistive loss of the high-side MOSFET is one-third and the switching loss is two-thirds of its total, the required maximum MOSFET resistances will be: RDS ( ON )HSF = 2 IC ( RMS ) = 5 A × 0.33 – 0.332 = 2.4 A The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation will be: PD ( FETs ) = 0.1 × VOUT × IOUT ( MAX ) (28) 2 3 3.75 A2 + ( 3.75 A × 6.25 A ) + 6.25 A2 = 2.9 A 3 ILSF ( MAX ) = DLSF ( MAX ) × 2 PLSF = 22 mΩ × 4.1 A2 = 370 mW 2 IHSF ( MAX ) = DHSF ( MAX ) × (27) PHSF = 35 mΩ × 2.9 A2 + (20) DHSF ( MAX ) = 1 – (192 kHz × 3.5 µs ) = 33% 2 × IG +VIN × QRR × f MIN The maximum output current IO(MAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3171 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT = 1.5 V, the maximum duty ratio of the high-side FET is: DHSF ( MAX ) = 1 – ( f MIN + tOFF ) VIN × IL ( PEAK ) × QG × f MIN –9– ADP3171 increased, the MOSFET drive will also be reduced or increased by the ADP3171 to provide a well regulated output voltage. Output voltages higher than the fixed internal reference voltage can be programmed by adding an external resistor divider. The correct resistor values for setting the output voltage of the linear regulators in the ADP3171 can be determined using: into the signals at the expense of making signal ground a bit noisier. 4. The GND pin of the ADP3171 should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the analog ground plane. The analog ground plane should be located below the ADP3171 and the surrounding small signal components such as the timing capacitor and compensation network. The analog ground plane should connect to power ground plane at a single point; the best location being the negative terminal of the last output capacitor. 5. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors also should be distributed, and generally in proportion to where the load tends to be more dynamic. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). Efficiency of the Linear Regulators 6. The efficiency and corresponding power dissipation of each of the linear regulators are not determined by the ADP3171. Rather, these are a function of input and output voltage and load current. Efficiency is approximated by the formula: Absolutely avoid crossing any signal lines over the switching power path loop, described below. Power Circuitry VOUT ( LR ) = VLRFB ( X ) × RU + RL RL (31) Assuming that RL = 10 kΩ, VOUT(LR) = 3.3 V and rearranging Equation 31 to solve for RU yields: RU = RU = ( 10 kΩ × VOUT(LR) − VLRFB 2 VLRFB 2 ) 10 kΩ × (3.3 V − 1.8 V ) = 8.33 kΩ 1.8 V (32) The closest 1% resistor value is 8.25 kΩ. η = 100% × VOUT VIN 7. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs, and the power Schottky diode, if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 8. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower MOSFET’s source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper MOSFET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body-drain diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET’s body-drain diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 9. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: (33) The corresponding power dissipation in the MOSFET, together with any resistance added in series from input to output, is given by: PLDO = (VIN – VOUT ) × IOUT (34) Minimum power dissipation and maximum efficiency are accomplished by choosing the lowest available input voltage that exceeds the desired output voltage. However, if the chosen input source is itself generated by a linear regulator, its power dissipation will be increased in proportion to the additional current it must now provide. LAYOUT AND COMPONENT PLACEMENT GUIDELINES The following guidelines are recommended for optimal performance of a switching regulator in a PC system: General Recommendations 1. For best results, a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. 2. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. If critical signal lines (including the voltage and current sense lines of the ADP3171) must cross through power circuitry, it is best if a ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection –10– REV. 0 ADP3171 improved current rating through the vias (if it is a current path), and improved thermal performance—especially if the vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 10. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors. 11. For best EMI containment, the ground plane should extend fully under all the power components. These are the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor, any snubbing elements that might be added to dampen ringing, and the output capacitors. REV. 0 Signal Circuitry 12. The output voltage is sensed and regulated between the GND pin (which connects to the signal ground plane) and the FB– pin. The output current is sensed (as a voltage) and regulated between the CS– pin and the CS+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the FB– trace should be routed atop the signal ground plane, and the CS+ and CS– traces should be routed as a closely coupled pair (CS+ should be over the signal ground plane as well). 13. The CS+ and CS– traces should be Kelvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desirable to have the ADP3171 close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the GND pin is minimized, and voltage regulation is not compromised. –11– ADP3171 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) C02711–0–5/02(0) 14-Lead Narrow SOIC (R-14) 0.3444 (8.75) 0.3367 (8.55) PIN 1 14 8 1 7 0.050 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.2440 (6.20) 0.2284 (5.80) 0.0196 (0.50) 45 0.0099 (0.25) 8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 0.0500 (1.27) 0.0138 (0.35) PLANE 0.0160 (0.41) 0.0075 (0.19) PRINTED IN U.S.A. 0.1574 (4.00) 0.1497 (3.80) –12–