Data Sheet No. PD60184-D IR2167(S) PFC BALLAST CONTROL IC Features • • • • • • • • • • • PFC, Ballast Control and Half Bridge Driver in • • • • • • • One IC Critical Conduction Mode Boost Type PFC No PFC Current Sense Resistor Required Programmable Preheat Time & Frequency Programmable Ignition Ramp Programmable Over-Current Internal Fault Counter End-of-Life Protection Description Lamp Filament Sensing & Protection Capacitive Mode Protection Brown-Out Protection Dynamic Restart Automatic Restart for Lamp Exchange Thermal Overload Protection Programmable Deadtime Internal 15.6V Zener Clamp Diode on VCC Micropower Startup (150µA) Latch Immunity and ESD Protection The IR2167 is a fully integrated, fully protected 600V ballast control IC designed to drive all types of fluorescent lamps. PFC circuitry provides for high PF, low THD and DC Bus regulation. Externally programmable features such as preheat time & frequency, ignition ramp characteristics, and running mode operating frequency provide a high degree of flexibility for the ballast design engineer. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, low AC line conditions, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of the ballast control section is a variable frequency oscillator with externally programmmable deadtime. Precise control of a 50% duty cycle is accomplished using a T-flip-flop. The IR2167 is available in both 20-pin DIP and 20-pin wide body SOIC packages. Packages 20-Lead SOIC (wide body) 20-Lead PDIP Typical Application Diagram D1 L1 + Rectified AC Line R5 RSUPPLY R4 C1 VDC CPH CPH HO 1 CBUS 3 4 RRUN R2 RUN 5 CT CT 6 COC RDT DT 7 ROC OC 8 CCOMP VB CBS VCC DBS COM CVCC 18 IR2167 RT L2 C5 19 RPH RPH M2 VS 2 CRAMP RT R7 20 17 CSNUBBER 16 LO R8 CS R9 15 C7 M3 R12 D3 14 R11 SD D2 R10 D4 13 COMP PFC 9 12 10 11 C3 R6 ZX VBUS D5 D6 C6 C4 R3 C2 RCS R13 R1 M1 - Rectified AC Line Please note that this datasheet contains advance information that could change before the product is released to production. www.irf.com 1 IR2167(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Min. Max. -0.3 625 High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VLO Low side output voltage -0.3 VCC + 0.3 VPFC PFC gate driver output voltage -0.3 VCC + 0.3 IOMAX Max. allowable output current (HO,LO,PFC) due to external power transistor miller effect -500 500 -5 5 High side floating supply voltage VS IRT RT pin current Units V mA VCT CT pin voltage -0.3 6.5 VDC VDC pin voltage -0.3 VCC + 0.3 ICPH CPH pin current -5 5 IRPH RPH pin current -5 5 IRUN RUN pin current -5 5 IDT Deadtime pin current -5 5 VCS Current sense pin voltage -0.3 6.5 5 ICS Current sense pin current -5 IOC Over-current threshold pin current -5 5 ISD Shutdown pin current -5 5 VBUS IZX ICOMP ICC DC bus sensing input voltage -0.3 VCC PFC inductor current, zero crossing detection input -5 5 PFC error amplifier compensation current -5 5 Supply current (note 1) -20 20 dV/dt Allowable offset supply voltage slew ratet -50 50 PD Package power dissipation @ TA ≤ +25°C (20 lead PDIP) — 1.50 (20 lead SOIC) — 1.25 (20 lead PDIP) — 85 (20 lead SOIC) — 90 RthJA 2 Definition VB Thermal resistance, junction to ambient TJ Junction temperature -55 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 V mA V mA V mA V/ns W °C/W °C www.irf.com IR2167(S) Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead Symbol Definition VBS High side floating supply voltage VS Steady state high side floating supply offset voltage Min. Max. VCC - 0.7 VCLAMP -3.0 600 VCLAMP Units V VCC Supply voltage VCCUV+ Note 2 10 mA 0 VCC V ICC Supply current VDC VDC lead voltage ISD Shutdown lead current -1 1 ICS Current sense lead current -1 1 mA CT CT lead capacitance 220 — pF RDT Deadtime resistance 1.0 — kΩ IRT RT lead current (Note 3) -500 -50 IRPH RPH lead current (Note 3) 0 450 IRUN RUN lead current (Note 3) 0 450 IZX Zero crossing detection lead current -1 1 TJ Junction temperature -40 125 uA mA o C Electrical Characteristics VCC = VBS = V BIAS = 14V +/- 0.25V, RT = 16.9kΩ, CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT = 6.1kΩ, R OC = 20.0kΩ, VCS = 0.5V, VSD = 2.0V, CL = 1000pF, TA = 25 oC unless otherwise specified. Supply Characteristics Symbol Definition Min. Typ. Max. VCCUV+ 10.4 11.4 12.5 VUVHYS IQCCUV IQCCFLT VCC supply undervoltage positive going threshold VCC supply undervoltage lockout hysteresis UVLO mode quiescent current Fault-mode quiescent current — — 2.1 250 100 2.1 400 350 IQCC Quiescent VCC supply current 1.9 3.3 4.5 ICC50K VCC supply current, f = 48kHz 4.0 5.0 6.0 VCLAMP VCC zener clamp voltage 14.0 15.6 16.5 Note 2: Note 3: www.irf.com Units Test Conditions VCC rising from 0V V 2.0 mA VCC < VCCUVSD = 5V, CS = 2V or Tj > TSD RT no connection, CT connected to COM V ICC = 10mA µA Sufficient current should be supplied to the VCC pin to keep the internal 15.6V zener clamp diode on this pin regulating its voltage. Due to the fact that the RT pin is a voltage-controlled current source, the total RT pin current is the sum of all of the parallel current sources connected to that pin. During the preheat mode, the total current flowing out of the RT pin consists of the RPH pin current plus the current due to the RT resistor. During the run mode, the total RT pin current consists of the RUN pin current plus the current due to the RT resistor. 3 IR2167(S) Electrical Characteristics (cont.) VCC = VBS = V BIAS = 14V +/- 0.25V, RT = 16.9kΩ, CT = 470 pF, RPH and RUN leads no connection, V CPH = 0.0V, RDT = 6.1kΩ, R OC = 20.0kΩ, V CS = 0.5V, VSD = 2.0V, CL = 1000pF, T A = 25o C unless otherwise specified. Floating Supply Characteristics Symbol Definition IQBS0 ILK Quiescent VBS supply current Offset supply leakage current Min. Typ. — — 0 0 Max. 10.0 50 Units Test Conditions µA VHO = VS VB = VS = 600V PFC Error Amplifier Characteristics Symbol Definition Min. Typ. VBUS IVBUS gm ISOURCE ISINK VOH(EA) V0L(EA) 3.7 — 40 15 5 12.5 — 4.0 — 90 30 30 13.5 0.25 Min. Typ. VBUS sense input threshold VBUS sense input bias current Error amplifier transconductance Error amplifier output current sourcing Error amplifier output current sinking Error amplifier output voltage swing (Hi state) Error amplifier output voltage swing (Lo state) Max. 4.3 0.1 130 50 50 14.5 0.4 Units Test Conditions µmho µA V V µA RUN mode operation VBUS = 3V VBUS = 5V VBUS = 3V VBUS = 5V PFC Over Voltage Comparator Symbol Definition V0V Over voltage comparator threshold Max. Units 4.0 4.3 4.5 V 1.7 400 6.0 2.0 300 7.5 2.3 300 9.0 V mV V Max. Units Test Conditions PFC Zero Current Detector VZX ZX lead comparator threshold voltage VZXhys ZX lead comparator hysterisis VZXclamp+ ZX lead clamp voltage (high state) IZX = 1mA Oscillator, Ballast Control, I/O Characteristics Symbol Definition Min. Typ. fosc Oscillator frequency 41 44 47 VCT+ VCTVRT tDLO tDHO Upper CT ramp voltage threshold Lower CT ramp voltage threshold RT lead voltage LO output deadtime HO output deadtime 3.6 1.8 1.8 2.0 2.0 4.0 2.0 2.0 2.4 2.4 4.4 2.2 2.2 2.6 2.6 Symbol Definition Min. Typ. Max. Units ICPH+ CPH lead charging current ICPHCPH lead discharge current VCPHIGN CPH lead lgnition mode threshold voltage VCPHRUN CPH lead run mode threshold voltage VCPHCLMP CPH lead clamp voltage 2.5 50 3.6 4.7 6 2.8 175 4.1 kHz Test Conditions RT = 16.9kΩ, RDT = 6.1kΩ, CT=470pF V µsec Preheat Characteristics 4 5.1 10 3.2 350 4.4 5.5 11.5 µA nA Test Conditions VCPH = 0V VCPH = 0V V ICPH = 1µA www.irf.com IR2167(S) Electrical Characteristics (cont.) VCC = VBS = V BIAS = 14V +/- 0.25V, RT = 16.9kΩ, CT = 470 pF, RPH and RUN leads no connection, V CPH = 0.0V, RDT = 6.1kΩ, R OC = 20.0kΩ, VCS = 0.5V, VSD = 2.0V, CL = 1000pF, T A = 25oC unless otherwise specified. RPH Characteristics Symbol Definition IRPHLK Open circuit RPH lead leakage current Min. Typ. Max. Units Test Conditions — 0.1 — µA VRPH =5V,VRPH =6V Min. Typ. Max. Units Test Conditions — 0.1 — µA Max. Units V mV RUN Characteristics Symbol Definition IRUNLK Open circuit RUN lead leakage current VRUN = 5V Protection Circuitry Characteristics Symbol Definition Min. Typ. VSDTH+ Rising shutdown lead threshold voltage VSDHYS Shutdown lead threshold hysteresis VSDEOL+ Rising shutdown lead end-of-life threshold voltage VSDEOL- Falling shutdown lead end-of-life threshold voltage VCSTH+ Over-current sense threshold voltage VCSTHUnder-current sense threshold voltage TCS Over-current sense propogation delay VVDC+ Low VBUS/rectified line input upper threshold VVDCLow VBUS/rectified line input lower threshold Thermal shutdown junction temperature TSD 4.8 300 2.6 5.25 150 3.0 5.4 100 3.4 0.7 1.0 1.3 1.05 0.14 50 4.8 2.7 — 1.2 0.23 350 5.2 3.1 160 1.35 0.28 550 5.7 3.5 — Min. Typ. Max. — — 50 25 0 0 85 45 Test Conditions V nsec Delay from CS to LO V oC Note 4 Gate Driver Output Characteristics Symbol Definition VOL VOH tr tf Note 4: Low level output voltage (PFC, LO or HO) High level output voltage (PFC, LO or HO) Turn-on rise time (PFC, LO or HO) Turn-off fall time (PFC, LO or HO) 100 100 200 100 Units Test Conditions mV Io = 0 VBIAS - VO, Io = 0 nsec When the IC senses an overtemperature condition (Tj > 160ºC), the IC is latched off. In order to reset this Fault Latch, the SD lead must be cycled high and then low, or the VCC supply to the IC must be cycled below the falling undervoltage lockout threshold (VCCUV-). www.irf.com 5 IR2167(S) Lead Assignments Pin # Symbol Pin Assignments 1 20 HO CPH 2 19 VS RPH 3 18 VB RT 4 RUN 5 CT 6 DT 7 OC 8 COMP 9 ZX 6 10 IR2167 VDC 17 VCC 16 COM 15 LO 14 CS 13 SD 12 PFC 11 VBUS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDC CPH RPH RT RUN CT DT OC COMP ZX VBUS PFC SD CS LO COM VCC VB VS HO Description DC Bus Sensing Input Preheat Timing Capacitor Preheat Frequency Resistor & Ignition Capacitor Oscillator Timing Resistor Run Frequency Resistor Oscillator Timing Capacitor Deadtime Programming Over-current (CS+) Threshold Programming Error Amplifier Compensation Zero-Crossing, PFC Inductor Bus Voltage Sense Input PFC Gate Driver Output Shutdown Input Current Sensing Input Low-Side Gate Driver Output IC Power & Signal Ground Logic & Low-Side Gate Driver Supply High-Side Gate Driver Floating Supply High Voltage Floating Return High-Side Gate Driver Output www.irf.com IR2167(S) State Diagram Power Turned On UVLO Mode 1/2-Bridge Off PFC Off COMP=0V IQCC ≅ 150µA CPH = 0V SD > 5.1V (Lamp Removal) or VCC < 9.5V (Power Turned Off) FAULT Mode Fault Latch Set 1/ -Bridge Off 2 PFC Off COMP=0V IQCC ≅ 150µA CPH = 0V VCC = 15.6V TJ > 160C (Over-Temperature) CS > OC Threshold (Failure to Strike Lamp or Hard Switching) or TJ > 160C (Over-Temperature) CS > OC Threshold (Over-Current or Hard Switching) or CS < 0.2V (No-Load or Below Resonance) or TJ > 160C (Over-Temperature) or SD < 1V or SD > 3V (End-of-Life) www.irf.com VCC > 11.4V (UV+) and VDC > 5.1V (Bus OK) and SD < 4.9V (Lamp OK) and TJ < 160C (Tjmax) VCC < 9.5V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Power Down) or SD > 5.1V (Lamp Fault or Lamp Removal) PREHEAT Mode 1/ -Bridge @ fPH 2 PFC Enabled CPH Charging @ IPH = 3µA RPH = 0V RUN = Open Circuit CS Disabled CPH > 4.0V (End of PREHEAT Mode) IGNITION RAMP Mode fPH ramps to fMIN CPH Charging @ IPH = 1µA RPH = Open Circuit RUN = Open Circuit CS OC Threshold Enabled CPH > 5.1V (End of IGNITION RAMP) RUN Mode fMIN Ramps to fRUN CPH Charges to 10V Clamp RPH = Open Circuit RUN = 0V CS 0.2V Threshold Enabled SD 1.0V and 3.0V Thresholds Enabled 7 IR2167(S) Functional Block Diagram 3.0V 18 VB VDC 1 S Q R Q PULSE FILTER & LATCH LEVEL SHIFT 5.1V 20 HO 1.0uA 19 VS CPH 2 9.5V 5.1V S Q T Q R Q 17 VCC 4.0V R1 4.0V RPH 3 R2 Q 2.0V 15 LO IRT 15.6V RT 4 16 COM 2.0V RUN 5 Q ICT = IRT D 0.2V 14 CS CLK CT 6 Q S Q R Q R DT 7 7.6V 50uA OVERTEMP DETECT UNDERVOLTAGE DETECT OC 8 13 SD 7.6V 2.0V 7.6V VBUS 11 4.0V VCC 4.3V GMhi 12 PFC COMP 9 S 4.0V Q R1 S Q R Q R2 Q S Q R Q 3.0V S Q WATCHDOG TIMER R1 R2 Q ZX 10 1.0V 7.6V 8 www.irf.com IR2167(S) BALLAST CONTROL SECTION TIMING DIAGRAMS NORMAL OPERATION 15.6V UVLO+ UVLO- VCC 7.6V 5.1V 4.0V VCPH 2.0V VRPH 2.0V VRUN FREQ fSTART fPREHEAT fRUN fMIN HO LO CS Over-Current Threshold CT HO PH IGN UVLO RUN UVLO CT CT HO HO LO LO CS www.irf.com LO CS CS 9 IR2167(S) BALLAST CONTROL SECTION TIMING DIAGRAMS FAULT CONDITION 15.6V UVLO+ UVLO- VCC 7.6V 5.1V 4.0V VCPH 2.0V VRPH 2.0V VRUN FREQ fSTART fPH fRUN fIGN SD 5.2V 2V HO LO CS PH IGN SD > 5.1V HO FAULT CT PH IGN UVLO RUN UVLO CT CT HO HO LO LO CS 10 LO CS CS www.irf.com IR2167(S) 6 4 5.5 EOL+ 3 EOL+, EOL- (V) SD(Preheat, Ignition) (V) 3.5 5 4.5 2.5 2 EOL- 1.5 1 0.5 4 0 -25 0 25 50 75 100 125 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) SD+ Threshold vs Temperature (IR2167) (Preheat, Ignition) EOL+, EOL- Threshold vs Temperature (IR2167) (Run Mode) 200 100 175 tRISE LO, t FALL LO (nS) 150 tDEAD ( S) 10 220pF 470pF 1 1nF tRISE 125 100 75 50 tFALL 3.3nF 25 10nF 0.1 0 1 10 RDT (KΩ) tDEAD vs RDT (IR2167) www.irf.com 100 -25 0 25 50 75 100 125 Temperature (°C) tRISELO, tFALLLO vs Temperature (IR2167) 11 IR2167(S) 5 15 13 VBUS+ VCCUV +, V CCUV - (V) VBUS+, V BUS- (V) 4.5 4 VBUS3.5 VCCUV+ 11 VCCUV- 9 7 3 -25 0 25 50 75 100 5 125 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) VBUS Threshold vs Temperature (IR2167) VCCUV +, VCCUV - vs Temperature (IR2167) 10 8 8 VCPH (IGN , RUN ) (V) VDC+, VDC- (V) VRUN 6 4 VIGN VDC+ 6 4 2 VDC- 2 0 0 -25 0 25 50 75 100 Temperature (°C) VCPH (IGN, 12 RUN) vs Temperature (IR2167) 125 -25 0 25 50 75 100 125 Temperature (°C) VDC+, VDC- vs Temperature (IR2167) www.irf.com IR2167(S) CT=220pF, RDT=5.6K 1000000 30 CT=470pF, RDT=2.7K 25 CT=1nF, RDT=1.2K Frequency (Hz) ILK ( A) 20 15 10 100000 5 0 -25 0 25 50 75 100 125 10000 1000 10000 Temperature (°C) 100000 RT (Ω) Frequency vs RT (IR2167) ILK vs Temperature (IR2167) tDEAD=1µsec 10 80 125°C 70 9 60 75°C 8 IQBS (uA) ICC (mA) 50 7 25°C 40 30 6 20 -25°C 5 10 4 10000 0 100000 Frequency (Hz) ICC vs Frequency (IR2167) 1000000 0 4 8 12 16 20 VBS (V) IQBS vs VBS vs Temperature (IR2167) RDT=5.6KΩ, CT=220pF www.irf.com 13 IR2167(S) 1000000 90 C T=220pF,R DT=11K C T=470pF,R DT=6.2K C T=1nF,RD T=3K 80 C T=4.7nF,RD T=1K C T=10nF,R DT=1K Tj (°C) Frequency (Hz) 70 100000 10000 60 50 40 30 1000 1000 10000 100000 20 10000 100000 Frequency (Hz) 1000000 RT (Ω) Frequency vs RT (IR2167) 14 Tj vs Frequency (IR2167 DIP) Driving IRF820's, VBUS=400V IC driven by square wave www.irf.com IR2167(S) Functional Description Under-voltage Lock-Out Mode (UVLO) The under-voltage lock-out mode is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. (To identify the different modes of the IC, refer to the State Diagram shown on page 2 of this document). During undervoltage lock-out mode, the HO, LO and PFC driver outputs are low and the CT pin is connected to COM through resistor RDT to disable the oscillator. Also, the internal supply to the RT pin circuitry is shut off and pins CPH, RUN, DT and COMP are internally pulled to COM. The IR2167 undervoltage lock-out mode is designed to maintain a very low supply current of less than 200µA, and to guarantee the IC is fully functional before the high side, low side and PFC drivers are activated. Figure 1 shows an efficient supply using the start-up current of the IR2167 together with a charge pump from the ballast stage (RSUPPLY, CVCC, DCP1 and DCP2). + VBUS + rectified AC Line R1 RSupply VDC R2 R3 HO 1 VS 2 C1 3 4 RUN 5 CT 6 DT 7 OC 8 VB CBS VCC DBS COM CVCC 18 IR2167 RT The IR2167 enters Preheat mode when VCC exceeds the UVLO positive-going threshold. Before Preheat mode begins, the CPH and RPH pins are connected to COM. (See Figure 3). As Preheat begins, the external capacitor CPH is charged up by an internal 3µA current source. CPH determines the preheat time which continues until the voltage on the CPH pin charges to 4.0V. Preheat mode is defined as the state the IC is in when the lamp filaments are being heated to their correct emission temperature. This is necessary for maximizing lamp life and reducing the required ignition voltage. At the onset of Preheat Mode, CVCC begins to discharge due to the increase in IC operating current (Figure 2) above the available current through resistor RSUPPLY. However, the half-bridge output also begins to oscillate and the charge pump, consisting of CSNUBBER, DCP1 and DCP2, supply the current to charge capacitor CVCC and thus the voltage to the IC. The VCC voltage supplied to the IC is VC1 19 RPH Preheat Mode Startup Mode Half-bridge output 20 CPH by the IC. The value of (RSUPPLY) is chosen to provide 2X the maximum start-up current to guarantee ballast start-up at low line input voltage. Once the capacitor voltage on the VCC pin reaches the start-up threshold, the SD lead is below 5.1 volts and VVDC is greater than 5.1V, the IC turns on and LO and HO begin to oscillate. PFC does not begin to oscillate until the IC reaches Preheat Mode. CVCC DISCHARGE CSNUBBER DCP1 17 VUVLO+ 16 DCP2 LO R4 15 VHYST VUVLOCS 14 SD 13 COMP 12 10 11 ZX DISCHARGE TIME RCS CHARGE PUMP OUTPUT PFC 9 INTERNAL VCC ZENER CLAMP VOLTAGE VBUS RSUPPLY & CVCC TIME CONSTANT t VBUS return Figure 1: Start-up and supply circuitry The VCC capacitor (CVCC) is charged by current through supply resistor (RSUPPLY) minus the start-up current drawn www.irf.com Figure 2: Supply Capacitor (CVCC) voltage limited by the internal 15.6V zener clamp. C VCC and CSNUBBER must be selected such that enough supply current 15 IR2167(S) is available over all ballast operating conditions. Bootstrap diode (DBS) and supply capacitor (CBS) comprise the supply voltage for the high-side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on HO, the first pulse from the output drivers comes from the LO pin. The Preheat mode oscillation frequency of the half-bridge output is determined by the parallel combination of RPH and RT with the values of CT, RDT and an internal circuit as 3.0uA CPH CPH 2 COMP1 M1 turns off and CRAMP begins to charge. CRAMP determines the time it takes for the oscillator to ramp down from the Preheat frequency to the Ignition Mode frequency. Once the voltage on the RPH lead reaches 2.0V, external resistor RPH has no effect on the frequency that is now determined by external components RT, CT and RDT. This is the minimum frequency. By this time, the oscillator will have ramped down toward the resonance of the load circuit causing the lamp to ignite. QUICK RESTART LOGIC 9.5V 5.1V 4.0V COMP2 3 RPH RT 2.0V 4.0V RPH CRAMP S Q R1 R2 Q M1 RT IRT 4 2.0V RRUN RUN 5 CT CT M2 ICT = IRT 6 RDT DT 7 Fault signal Figure 3: Oscillator section block diagram with external component connection shown in Figure 3. Note that at the onset of Preheat mode the initial startup frequency is much higher than the preheat frequency. The half-bridge output frequency then ramps down from this initial start-up frequency to the Preheat mode frequency. This is to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp Ignition Mode Run Mode When the voltage on the CPH pin reaches 5.1V, the IC enters Run mode. At this time, the output of COMP1 (figure 3) goes high which turns M2 on and pulls the RUN pin to COM. The frequency is now controlled by external components RT, RRUN, CT and RDT. In certain cases it is necessary to have the run frequency higher than the ignition frequency to control the power used by the load. Figure 4 shows the ballast control sequence explained in the previous paragraphs When the CPH pin charges up to 4.0V, ignition mode begins. At this time, the output of COMP2 (figure 3) goes low, 16 www.irf.com IR2167(S) frequency fStart fPH fRun fmin t 5V VCPH 2V VRPH Figure 5: Oscillator Waveforms This falling portion of the sawtooth waveform is referred to as deadtime, during which both HO and LO outputs are low. The deadtime can be programmed by means of the external RDT resistor. 2V VRUN Preheat mode Ignition Run mode Ramp mode Figure 4: IR2167 Ballast Control Sequence The control sequence used in the IR2167 allows the Run mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). This control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant LC component tolerances (please note that it is possible to use the IR2167 in systems where fstart > fph > fign > frun, simply by leaving the RUN pin open). The heart of this controller is an oscillator that resembles those found in many popular PWM voltage regulator ICs. In its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. The voltage across the timing capacitor CT is a sawtooth, where the rising portion of the ramp is determined by the current in the RT lead, and the falling portion of the ramp is determined by an external deadtime resistor RDT. The oscillograph in Figure 5 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. www.irf.com The RT input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0V. In order to maintain proper linearity between the RT pin current and the CT capacitor charging current, the value of the RT pin current should be kept between 50µA and 500µA. The RT pin can also be used as a feedback point for closed loop control. PFC Section In most AC to DC power converters it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. To achieve this, active power factor correction (PFC) can be implimented which, for an AC input line voltage, produces an AC input line current. It is also important to produce a sinusoidal input current which has a low total harmonic distortion (THD) and a high power factor (PF) (See Figure 6). . 17 IR2167(S) Figure 7: Inductor Current Figure 6: Input Voltage & Current PF=0.96, THD=22% The approach used in the IR2167 is classified as running in critical conduction mode, in which the inductor current discharges to zero with each switching cycle. There is no need to sense the rectified AC line input voltage because it is already sinusoidal. Therefore, the inductor current will naturally follow the sinusoidal voltage envelope as the PFC MOSFET is turned on and off at a much higher frequency (>10KHz) than the line input frequency (50 to 60Hz). The circuit compares the DC Bus voltage to a fixed reference voltage to determine the on-time of the PFC MOSFET. The off-time is determined by the time it takes the LPFC current to drop to zero. This zero current level is detected by a secondary winding in LPFC that is connected to the ZX pin. The result is a system where the switching frequency is freerunning and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks. (See Figures 7, 8 & 9). Figure 8: Boost Inductor Envelope & Line Voltage ILPFC 0 PFC pin 0 ZX pin 0 near peak region of rectified AC line near zero crossing region of rectified AC line Figure 9: Boost FET On Time vs Line Input 18 www.irf.com IR2167(S) As the external capacitor on the COMP pin begins to charge, the PFC MOSFET on time duration increases. The gain of OTA1 is at its maximum value (See Figures 10 & 11). Maximum gain is desireable to raise the Bus voltage to its nominal value as quickly as possible. When the voltage at the VBUS pin reaches 3V, the gain of OTA1 decreases to its Run Mode Signal MOSFET is turned on with minimum on time and LPFC is shorted to ground and begins charging. The PFC MOSFET then turns off and LPFC begins to discharge into the DC BUS capacitor. COMP4 has a 4.3V threshold with hysteresis so that if the voltage at the VBUS pin overshoots the 4.0V threshold, From Fault Detection Circuitry VBUS 11 COMP4 OTA1 VCC 4.0V 4.3V GM hi COMP1 RS2 4.0V COMP2 RS1 M1 S Q R1 R2 Q 12 PFC RS3 COMP5 COMP 9 S Q R Q WATCHDOG TIMER C1 M2 S Q RS4 R Q S Q R1 R2 Q 3.0V COMP3 ZX 10 1.0V 7.6V Figure 10: PFC Section nominal value. The BUS voltage continues to increase to its nominal value at which time the voltage measured at the VBUS pin equals 4V. The gain of OTA1 now increases to its maximum value and remains there until the Run mode. This is necessary because if VBUS overshoots its nominal value, the circuit can react quickly to correct the error. Also, during ignition, there is a sudden increase in load current which can cause the Bus voltage to sag. With maximum gain, OTA1 can quickly restore the DC Bus voltage to its nominal value. When the AC line voltage is applied to the ballast, VCC rises to 15V. The PFC section is not enabled until the beginning of the Preheat mode of operation. By not enabling the PFC section until the beginning of the Preheat mode, the DC Bus voltage in the ballast is not yet boosted to its nominal running value. This helps alleviate the initial flash of the lamp when the half-bridge driver section first begins to switch. When the PFC circuit is first enabled, (See Figure 10), the voltage at the VBUS and COMP pins is low. The PFC www.irf.com the PFC MOSFET will not turn on again until the voltage at the VBUS pin drops to approximately 4.0V. This effectively limits ths maximum bus voltage to approximately 8% greater than the regulated level. In some instances, the line voltage may be too high. This causes the AC rectified line current to directly charge the DC Bus capacitor without being boosted. Since the current never drops to zero, the ZX pin never goes high and the PFC MOSFET never turns on. The Watch Dog Timer circuit provides a pulse to turn on the PFC MOSFET if no pulse is detected at the ZX pin for 500mS. This enables the PFC circuitry to regulate the DC Bus voltage at its nominal value 19 IR2167(S) VVBUS 4.3 4.0 3.0 0 DRIVE SIGNALS 6.0 5.1 5.0 4.0 VCPH 2.0 0 6.0 4.0 VCOMP 2.0 0 Note 1 ICOMP 0 Note 1 Note 1 RESULTANT SIGNALS Note 1 1000 gm (max) 200 0 QUICK START MODE POWER UP MODE POWER BOOST MODE RUN MODE Note 1: ICOMP in these regions is the output saturation current of the OTA Error amplifier Figure 11: PFC Timing Sequence 20 www.irf.com IR2167(S) Lamp Protection & Automatic Restart Circuitry Operation +VBUS R1 R2 VDC 3.0V 1 S Q R Q 5.1V C1 1.0uA 2 CPH 9.5V from oscillator section QUICK RESTART LOGIC 5.1V T Q R Q 4.0V Q2 R3 Q D Q S Q R Q RCS CS 0.2V 14 CLK R R4 DT 7 50uA OC 8 ROC COC 7.6V FAULT COUNTER UNDERVOLTAGE DETECT OVERTEMP DETECT C3 3V 1meg R6 SD R7 13 1V 7.6V C2 5.1V from upper lamp cathode VCC 2V 7.6V R5 C4 from lower lamp cathode Figure 12: Lamp Protection & Automatic Restart circuitry block diagram with external component connection Sensing the AC Line Voltage The first of these protection pins senses the voltage on the AC line by means of an external resistor divider (R1, R2 and capacitor C1) and an internal comparator with hysterisis. When power is first supplied to the IC at system startup, three conditions are required before oscillation is initiated: 1.) the voltage on the VCC pin must exceed the rising undervoltage lockout threshold (11.5V), 2.) the voltage at the VDC pin must exceed 5.1V, and 3.) the voltage on the SD pin must be below approximately 4.85V. If a low ac line condition occurs during normal operation, or if power to the ballast is shut off, the ac line will collapse prior to the VCC of www.irf.com the chip (assuming theVCC is derived from a charge pump off of the output of the half-bridge). In this case, the voltage on the VDC pin will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switching. Approximately 2V of hysterisis has been designed into the internal comparator sensing the VDC pin, in order to account for variations in the ac line voltage under varying load conditions. When the ac line recovers, the chip restarts from the beginning of the control sequence, as shown in timing diagram (See Figure 13). 21 IR2167(S) automatically restarts the lamp in the proper manner. In the Run mode there are two additional thresholds enabled on the SD pin: 1V and 3V. These thresholds form a window and during normal lamp running the voltage appearing at the SD pin is maintained within these two levels. As a lamp nears its end-of-life, its running voltage will increase and the signal applied to the SD pin detects this by exceeding the window threshold width. The oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. 5 VDC 3 4 CT 8 + rectified AC Line CPH VDC HO 1 20 2 19 3 18 CPH VS 15 RPH VB RT 4 RUN 5 CT 6 DT 15 7 OC HO-VS IR2167 LO + VBUS RGHS CBLOCK LRES CBS RSupply VCC DBOOT COM CVCC CSNUBBER D1 17 16 CRES D2 LO 15 CS R3 RGLS R5 14 SD 8 13 9 12 COMP D3 R6 R4 PFC ZX VBUS 10 C2 C4 11 RCS R7 C3 RUN mode Low VDC Restart VBUS return Figure 13: VDC lead fault and auto restart Figure 14: Lamp presence detection circuit connection (shaded area) Lamp Presence and End-of-Life Detection The second protection pin, SD, is used for both shutdown and end-of-life detection. The SD pin would normally be connected to an external circuit that senses the presence of the lamp(s) and the voltage appearing across the lamp(s). An example circuit for a single lamp is shown in Figure 14. During all modes of operation if the SD pin exceeds 5.1V (approximately 150mV of hysterisis is included to increase noise immunity), signaling either a lamp fault or lamp removal, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. Since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted in the fixture, the SD pin would be pulled back to near ground potential. Under these conditions a reset signal would restart the chip from the beginning of the control sequence, as shown in the timing diagram in Figure 15. Thus, for a lamp removal and replacement, the ballast 22 www.irf.com IR2167(S) R OC = VCS+ , 55E - 6 5 SD or VCS + = 55E - 6 ⋅ ROC 4 CT rectified AC line 8 VDC HO 1 CPH VS 2 3 4 RUN 5 CT 6 DT 15 7 HO-VS OC 8 Restart Figure 15: SD lead fault and auto restart Half-Bridge Current Sensing and Protection The third pin used for protection is the CS pin, which is normally connected to a resistor in the source of the lower power MOSFET, as shown in Figure 16. The CS pin is used to sense fault conditions such as failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. If any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. The CS lead performs its sensing functions on a cycle-by-cycle basis in order to maximize ballast reliability. For the over-current, failure-to-strike, and hard switching fault conditions, an externally programmable, positive-going CS+ threshold is enabled at the end of the preheat time. The level of this positive-going threshold is determined by the value of the resistor ROC. The value of the resistor ROC is determined by the following formula: www.irf.com VCC DBOOT RSUPPLY CSNUBBE D1 R COM CVCC 16 LO Q2 15 CS RGLS D2 14 R3 SD 13 PFC 9 ZX SD mode /2 Bridge output CBOOT 17 COMP RUN mode 1 VB 18 IR2167 RT RGHS 19 RPH LO Q1 20 CPH 15 +VBUS ROC 10 12 VBUS 11 RCS VBUS return Figure 16: Half-bridge current sensing circuit connection (shaded area) For the under-current and under-resonance conditions, there is a negative-going CS- threshold of 0.2V which is enabled at the onset of the run mode. The sensing of this CSthreshold is synchronized with the falling edge of the LO output. Figures 17, 18 and 19 are oscillographs of fault conditions. Figure 17 shows a failure of the lamp to strike, Figure 18 shows a hard switching condition and Figure 19 shows an under-current condition. 23 IR2167(S) 24 Figure 17: Failure of lamp to strike Figure 19: Operation below resonance Figure 18: Hard switching condition Figure 20: Auto restart for lamp replacement www.irf.com IR2167(S) Recovery from such a fault condition is accomplished by cycling either the SD pin or the VCC pin. (See Figure 20). When a lamp is removed, the SD pin goes high, the fault latch is reset, and the chip is held off in an unlatched state. Lamp replacement causes the SD pin to go low again, reinitiating the startup sequence. The fault latch can also be reset by the undervoltage lockout signal, if VCC falls below the lower undervoltage threshold. Bootstrap Supply Considerations Power is normally supplied to the high-side circuitry by means of a simple charge pump from VCC, as shown in Figure 21. this CMOS circuitry is very low (typically 45µA in the onstate), the majority of the drop in the VBS voltage when Q1 is on occurs due to the transfer of charge from the bootstrap capacitor to the gate of the power MOSFET. Design Equations Note: The results from the following design equations can differ slightly from experimental measurements due to IC tolerances, component tolerances, and oscillator over- and under-shoot due to internal comparator response time. Step 1: Program Maximum Ignition Voltage rectified AC line VDC +V BUS HO 1 20 2 19 CPH Q1 VS RPH 3 4 RUN 5 CT 6 DT 7 OC 8 1/ VB C BOOT VCC DBOOT 18 IR2167 RT R GHS RSUPPLY 2 Bridge output C SNUBBER D1 17 COM CVCC 16 LO 15 Q2 CS R GLS D2 14 I CT = I RT = R3 SD 2.0V RT 13 COMP PFC 9 12 10 11 RCS VBUS ZX VBUS The value of this current should be kept between 50 µA and 500 µA. The value for CT is computed as follows: return Figure 21 : Typical bootstrap supply connection with VCC charge pump from half-bridge output (shaded area) A high voltage, fast recovery diode DBOOT (the so-called bootstrap diode) is connected between VCC (anode) and VB (cathode), and a capacitor CBOOT (the so-called bootstrap capacitor) is connected between the VB and VS leads. During half-bridge switching, when MOSFET Q2 is on and Q1 is off, the bootstrap capacitor CBOOT is charged from the VCC decoupling capacitor, through the bootstrap diode DBOOT, and through Q2. Alternately, when Q2 is off and Q1 is on, the bootstrap diode is reverse-biased, and the bootstrap capacitor (which ‘floats’ on the source of the upper power MOSFET) serves as the power supply to the upper gate driver CMOS circuitry. Since the quiescent current in www.irf.com Maximum lamp voltage is required during ignition. This will vary depending on the type of lamp, but 1600V is typical for a T8 lamp. As the frequency decreases from the preheat frequency to the resonant frequency, the voltage across the lamp increases. During ignition, only RT along with CT and DT determine the frequency. R PH and R RUN are not connected to COM at this time. The value of RT should be chosen so that the desired ignition voltage is reached. The RT pin current and timing capacitor charging current are both approximately: CT = 1 RT 1 − td 2 fign And the ignition mode frequency is: f IGN = RT = 1 2(RT CT + td ) 1 CT 1 − td 2 fign 25 IR2167(S) Deadtime is equal to: 250 td = 0.69 ⋅ RDT ⋅ CT The following graphs, figures 22 and 23, illustrate the relationship between the effective resistance (i.e. the parallel combination of resistors which programs the CT capacitor charging current) and the operating frequency. 200 CT=220pF, RDT=5.6K CT=470pF, RDT=2.7K CT=1nF, RDT=1.2K 150 FREQ (KHz) 100 150 FREQ (KHz) 50 CT=220pF,RDT=11K CT=470pF,RDT=6.2K CT=1nF,RDT=3K 100 0 0 5 10 15 20 25 30 35 40 RT (KΩ) Figure 23: fOSC vs effective RT (tDEAD=1.0µsec) 50 Figure 24 illustrates the relationship between deadtime vs RDT. 0 0 5 10 15 20 25 30 35 40 10 RT (KΩ) Figure 22: fOSC vs effective RT (tDEAD=2.0µsec) tDEAD (usec) CT = 220 pF CT = 470 pF CT = 1 nF 1 0.1 1 10 100 RDT (KΩ) Figure 24: Deadtime vs RDT 26 www.irf.com IR2167(S) Step 2: Program Maximum Ignition Current Step 4: Program preheat time The ignition current should be limited to the rating of the lamp resonant inductor and the half-bridge MOSFETS. The saturation current of the lamp resonant inductor should be much lower than the current rating of the MOSFETS. Under worst case conditions, the lamp resonant inductor should not be allowed to saturate. This current is controlled by the CS pin and the OC pin. The OC lead has an internal 50µA current source. This current through external resistor ROC determines the threshold on the CS pin. The preheat time is determined by external capacitor CPH. The preheat time required for a 4:1 hot to cold ratio can be observed by measuring the voltage across the filaments. The preheat time is calculated as follows: ROC = VCS + or 55E − 6 VCS + = 55E − 6 − ROC tPH = 4.0 E 6 ⋅ CPH The IR2167 is held in preheat until CPH is charged to 4.0V. Step 5: Program the ignition mode time The difference in time between the preheat mode and the run mode is the ignition mode. The rate at which the frequency changes from preheat to run is determined by external resistor RRAMP. If the current through external resistor RCS exceeds a predetermined value, the IC shuts off. Step 6. Program the run frequency Step 3: Program Preheat Frequency The preheat frequency is determined by the parallel combination of RPH and RT along with CT and RDT. The frequency should be chosen so that the voltage across the lamp is much lower than the ignition voltage but still provides adequate heating of the filaments. During preheat, the current through the filaments is constant. However, as the filaments heat up, their resistance increases. This results in an increase in the voltage measured across the filaments, which indicates the hot to cold ratio. f PH = RPH The run mode begins when external resistor RPH is charged to 5.1V. At this time, the run frequency is determined by the parallel combination of RT and RRUN along with RDT and CT. The run frequency can be programmed above or below the ignition frequency. fRUN is determined by the following equation: f RUN = 1 R ⋅R 2 ⋅ T PH ⋅ CT + td RT + RPH 1 2 f − td ph = 1 1 1− − td RT ⋅ CT 2 f ph 1 CT RRUN 1 R ⋅R 2 ⋅ T RUN ⋅ CT + td RT + RRUN 1 − td 2 f RUN = 1 1 1− − td RT ⋅ CT 2 f RUN 1 CT 4:1 is an acceptable ratio for proper heating www.irf.com 27 IR2167(S) Component Selection Tips Connecting the IC Ground (COM) to the Power Ground Supply Bypassing and pc Board Layout Rules Component selection and placement on the pc board is extremely important when using power control ICs. VCC should be bypassed to COM as close to the IC terminals as possible with a low ESR/ESL capacitor, as shown in Figure 25. CVCC IR2167 pin 1 (surface mount) CBOOT (surface mount) (surface DBoot mount) Both the low power control circuitry and low side gate driver output stage grounds return to this lead within the IC. The COM lead should be connected to the bottom terminal of the current sense resistor in the source of the low side power MOSFET using an individual pc board trace, as shown in Figure 26. In addition, the ground return path of the timing components and VCC decoupling capacitor should be connected directly to the IC COM lead, and not via separate traces or jumpers to other ground traces on the board. IR2167 pin 1 CVCC (surface mount) CVCC (through hole) CVCC (through hole) timing component s RCS (through hole) VBUS return Figure 25: Supply bypassing PCB layout example Figure 26: COM lead connection PCB layout example A rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (Ciss) of the power transistors being driven. This decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electrolytic (e.g., 10µF) placed immediately adjacent to the VCC and COM terminals will work well. These connection techniques prevent high current ground loops from interfering with sensitive timing component operation, and allows the entire control circuit to reject common-mode noise due to output switching. In a typical application circuit, the supply voltage to the IC is normally derived by means of a high value startup resistor (1/4W) from the rectified line voltage, in combination with a charge pump from the output of the half-bridge. With this type of supply arrangement, the internal 15.6V zener clamp diode from VCC to COM will determine the steady state IC supply voltage. 28 www.irf.com IR2167(S) Caseoutline 20 Lead SOIC (wide body) www.irf.com (MS-013AC) 01-3080 00 29 IR2167(S) Caseoutline 20 Lead PDIP (MS-001AD) 01-3079 00 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 8/19/2002 30 www.irf.com