TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 • • • • • • • • • • • • High-Resolution, Solid-State Frame-Transfer Image Sensor 17.2-mm Image-Area Diagonal 1000 (H) x 1018 (V) Active Elements in Image-Sensing Area Square Pixels Low Dark Current Electron-Hole Recombination Antiblooming Dynamic Range . . . More Than 60 dB High Sensitivity High Photoresponse Uniformity High Blue Response Single-Phase Clocking Solid-State Reliability With No Image Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics DUAL-IN-LINE PACKAGE (TOP VIEW) OUT1 1 24 ABG2 AMP GND 2 23 IAG2 OUT2 3 22 ABG1 ADB 4 21 IAG1 SUB 5 20 SUB RST2 6 19 TDB RST1 7 18 SUB CDB 8 17 SUB SRG1 9 16 IAG1 SRG2 10 15 ABG1 TRG 11 14 IAG2 IDB 12 13 ABG2 description The TC215 is a full-frame charge-coupled-device (CCD) image sensor that provides very high-resolution image acquisition for image-processing applications such as robotic vision, medical X-ray analysis, and metrology. The image format measures 12 mm horizontally by 12.216 mm vertically; the image-area diagonal is 17.2 mm. The image-area pixels are 12-µm square. The image area contains 1018 active lines with 1000 active pixels per line. Six additional dark reference lines give a total of 1024 lines in the image area, and 24 additional dark reference pixels per line give a total of 1024 pixels per horizontal line. The full-frame image sensor should be used with a shutter or with strobed illumination to prevent smearing of the image during readout. To prepare the imaging area for image capture, the photoelectric charge that has accumulated in the image pixels can be transferred into the clearing drain in one millisecond. After image capture (integration time), the readout is accomplished by transferring the charge, one line at a time, into two serial registers, each of which contains 512 data elements and 12 dummy elements. The typical serial-register clocking rate is 10 megapixels per second. Operating the TC215 at the typical data rate of one field per frame generates video output at a continuous 15 frames per second. Gated floating-diffusion detection structures are used with each serial register to convert charge to signal voltage. External reset allows the application of off-chip correlated clamp sample-and-hold amplifiers for low-noise performance. To provide high output-drive capability, both outputs are buffered by low-noise, two-stage, source-follower amplifiers. These two output signals can provide a data rate of 20 megapixels per second when combined off chip. At room temperature, the readout noise is 55 electrons and a minimum dynamic range of 60 dB is available. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-1 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 description (continued) The blooming protection incorporated into the sensor is based on recombining excess charge with charge of oppositie polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element. The TC215 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, good uniformity, and single-phase clocking. The TC215 is characterized for operation from –10°C to 40°C. functional block diagram Top Drain 19 TDB 16 IAG1 ABG1 IAG2 ABG2 21 15 Image Area With Blooming Protection 14 RST2 OUT2 RST1 OUT1 24 Dark Reference Elements 4 23 24 6 3 IAG2 ABG2 IDB 12 7 10 9 1 Multiplexer, Transfer Gates, and Serial Registers Clearing Drain 12 Dummy Elements 2 AMP GND 2-2 ABG1 13 Amplifiers ADB 22 IAG1 8 CDB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SRG2 SRG1 TRG TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 sensor topology diagram 1000 Pixels 1 Pixel 22 Pixels 1 Pixel 1018 Lines 6 Lines OPB 12 511 12 511 Dummy Pixels Terminal Functions TERMINAL I/O DESCRIPTION NAME ABG1† NO. 15 I Antiblooming gate for upper image area ABG1† ABG2† 22 I Antiblooming gate for upper image area 13 I Antiblooming gate for lower image area ABG2† 24 I Antiblooming gate for lower image area ADB 4 I Supply voltage for amplifier drain bias AMP GND 2 CDB IAG1† IAG1† 8 I Supply voltage for clearing drain bias 16 I Upper image-area gate 21 I Upper image-area gate IAG2† IAG2† 14 I Lower image-area gate 23 I Lower image-area gate IDB 12 I Supply voltage for input diode bias OUT1 1 O Output signal 1 OUT2 3 O Output signal 2 RST1 7 I Reset gate 1 RST2 6 I Reset gate 2 SRG1 9 I Serial-register gate 1 SRG2 SUB† 10 I Serial-register gate 2 5 Substrate and clock return SUB† SUB† 17 Substrate and clock return 18 Substrate and clock return SUB† 20 TDB 19 I TRG 11 I Amplifier ground Substrate and clock return Supply voltage for top drain bias Transfer gate † All terminals of the same name should be connected together externally (i.e., pin 15 to pin 22, pin 13 to pin 24, etc.). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-3 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 detailed description The TC215 consists of three basic functional blocks: (1) the image-sensing area, (2) the multiplexer block with serial registers and transfer gates, and (3) the low-noise signal-processing amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional block diagram. image-sensing area Figures 1 and 2 show cross sections with potential well diagrams and top views of image-sensing elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. After integration is complete, the signal charge is transferred in the dark to the two serial registers, where it is read out line by line. There are 24 full columns of elements at the left edge of the image-sensing area that are shielded from incident light; these elements provide the dark reference used in subsequent video-processing circuits to restore the video black level. There are also six dark lines at the bottom of the sensor. multiplexer with transfer gates and serial registers The multiplexer and transfer gates transfer charge line by line from the image-sensing columns into the corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse timing is shown in Figure 5. A drain is also included to provide the capability to clear the image-sensing area of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special circumstances. The clearing timing is illustrated in Figure 6. serial-register readout and video processing After transfer into the serial registers, the pixels are normally read out 180° out of phase (see Figure 7). Each serial register must be reset to the reference level before the next pixel is read out. The timing for the resets and their relationships to the serial-register pulses is shown in Figure 8. Figure 8 also shows the timing for the pixel clamp and sample and hold needed for an off-chip double-correlated sampling circuit. These two output signals can provide a data rate of 20 million pixels per second when combined off chip. After the charge is placed on the detection node, it is buffered and amplified by a low-noise, dual-stage source follower. Each serial register contains 12 dummy elements that are used to span the distance between the serial register and the output amplifier. A schematic is shown in Figure 9. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram. Figure 10 gives the timing for a single frame of video. Operating the TC215 at the typical data rate of one field per frame generates video output at a continuous 15 frames per second. 2-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 12 µm(H) Light Clocked Barrier φ-IAG 12 µm(V) Virtual Barrier φ-ABG Antiblooming Clocking Levels Antiblooming Gate Virtual Well Clocked Well Accumulated Charge Figure 1. Charge-Accumulation Process φ-IAG Clocked Phase Virtual Phase Channel Stops Figure 2. Charge-Transfer Process Channel Stops Channel Stop Clocked Wells SerialRegister Gate Virtual Well Clocked Well Multiplexing Gate Transfer Gate Figure 3. Multiplexing-Gate Layout POST OFFICE BOX 655303 Figure 4. Interface-Region Layout • DALLAS, TEXAS 75265 2-5 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 CSYNC CBLNK TRG SRG1 SRG2 RST1 High RST2 High CL1 Low CL2 Low SH1 Low SH2 Low IAG1, 2 ABG1, 2 CPOB1 CPOB2 Figure 5. Horizontal Timing 2-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 1 µs Line 1 Line 2 Line 1024 Line 1023 IAG1 IAG2 ABG1,2 TRG SRG1 SRG2 RST1 High RST2 High Figure 6. Clearing Timing Dummy 1 2 3 Black Reference 11 12 1 2 Image 11 12 1 2 3 SRG2 1 2 3 12 1 2 12 1 2 3 SRG1 NOTE A: A minimum of 524 clock pulses is required to transfer out all elements of a serial register. Overclocking is recommended. Figure 7. Start of Serial-Transfer Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-7 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 OUT CCD SRG Buffer RST Pixel Clamp Sampleand-Hold Amplifier CL SH SRG1 RST1 OUT1 CL1 SH1 SRG2 RST2 OUT2 CL2 SH2 NOTE A: The video-processing (off-chip) pulses are defined as follows: CL1 = Clamp pulse for video from OUT1 CL2 = Clamp pulse for video from OUT2 SH1 = Sample pulse for the sample-and-hold amplifier for video 1 SH2 = Sample pulse for the sample-and-hold amplifier for video 2 CSYNC = Composite video-sync pulse CBLNK = Composite video-blanking pulse CPOB1 = Dark-reference clamp pulse for video from OUT1 CPOB2 = Dark-reference clamp pulse for video from OUT2 Figure 8. Video-Process Timing 2-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 Reference Generator ADB CCD Register Clocked Virtual Gate Gate Reset Gate and Output Diode Detection Node Two-Stage SourceFollower Amplifier OUTn SRGn RSTn Figure 9. Buffer Amplifier and Charge-Detection Node Integration (shutter open) Readout 1024 Pulses Clearing IAG1,2 TRG 541 Pulses SRG1 SRG2 Start of Serial Transfer ABG1,2 RST1 RST2 Horizonal Timing Figure 10. Clock Timing Requirements – Single-Frame Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-9 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 spurious nonuniformity specification The spurious nonuniformity specification of the TC215 CCD grades – 30 and – 40 is based on several sensor characteristics: • • • Amplitude of the nonuniform line or pixel Polarity of the nonuniform pixel – Black – White Nonuniform line or pixel count The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 11. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 12. The pixel nonuniformity specification for the TC215 is as follows (CCD video-output signal is 50 mV ±10 mV): NONUNIFORMITY TYPE TC215- 30 TC215 - 40 Maximum amplitude = 1.4 mV Line Number with amplitude greater than 1 mV is ≤ 5 White spot (40°C) Maximum amplitude = 25 mV Maximum amplitude = 15 mV White spot (25°C) Maximum amplitude = 20 mV Number with amplitude greater than 10 mV = B Black spot (% of total illumination) Total number of nonuniformities Maximum amplitude = 25% Maximum amplitude = 30% Number with amplitude greater than 10% = C B + C < 20 mV Amplitude % of Total Illumination t Figure 11. Pixel Nonuniformity, Dark Condition 2-10 POST OFFICE BOX 655303 t Figure 12. Pixel Nonuniformity, Illuminated Condition • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range for ADB, CDB, IDB, TDB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 15 V Input voltage range for ABG1, ABG2, IAG1, IAG2, RST1, RST2, SRG1, SRG2, TRG . . . . . . –15 V to 15 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 40°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the substrate terminal. recommended operating conditions Supply voltage for ADB, CDB, IDB, TDB MIN NOM MAX 11 12 13 Substrate bias voltage 0 IAG1 IAG2 IAG1, SRG1 SRG2 SRG1, Input voltage, g VI‡ RST1 RST2 RST1, ABG1, ABG2 TRG Clock frequency, fclock Capacitive load V V High level 1.5 Low level –11 High level 1.5 Low level –11 High level 1.5 Low level –11 High level 5 5.5 Intermediate level§ –1.5 –1. 2 – 0.9 Low level –7.5 –7 – 6.5 High level 1.5 2 2.5 Low level –11 TRG, SRG1, SRG2, RST1, RST2 UNIT 2 2.5 2 2.5 2 2.5 –9 –9 –9 V 6 –9 10 IAG1, IAG2 1 ABG1, ABG2 1 OUT1, OUT2 8 MHz pF Operating free-air temperature, TA – 10 40 °C ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage levels. § Adjustment is required for optimal performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-11 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 electrical characteristics over recommended operating ranges of supply voltage and free-air temperature PARAMETER MIN Dynamic range (see Note 2) TYP† MAX 60 Charge conversion factor dB µV/e 6 Charge transfer efficiency (see Note 3) UNIT 0.99990 Signal response delay time, τ (see Note 4 and Figure 16) Gamma (see Note 5) 18 20 22 0.89 0.94 0.99 Output resistance 1000 1/f noise (5 kHz) Noise voltage 0.1 Random noise (f = 100 kHz) 60 Rejection ratio at 10 MHz ADB (see Note 6) 20 SRGn (see Note 7) 40 ABGn (see Note 8) 30 Supply current electrons dB 9 IAG1, IAG2 mA 15000 ABG1, ABG2 Input In ut ca capacitance acitance, Ci Ω µV/√Hz 0.08 Noise equivalent signal ns 8000 TRG 350 pF F SRG1, SRG2 200 † All typical values are at TA = 25 °C. NOTES: 2. Dynamic range is – 20 times the logarithm of the mean noise signal divided by the saturation output signal. 3. Charge transfer efficiency is one minus the charge loss per transfer in the output register (1046 transfers). The test is performed in the dark using an electrical input signal. 4. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state. 5. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve (this value represents points near saturation): ǒ Ǔ +ǒ Exposure (2) Exposure (1) g Ǔ Output signal (2) Output signal (1) 6. ADB rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ADB. 7. SRGn rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on SRGn. 8. ABGn rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ABGn. 2-12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 optical characteristics, TA = 25°C, integration time = 33 ms (unless otherwise noted) PARAMETER No IR filter Sensitivity (see Note 9) With IR filter MIN TYP MAX 518 Measured at VU (see Note 10) UNIT mV/lx 64 Saturation signal, Vsat (see Note 11) 320 mV Maximum usable signal, Vuse 200 mV Blooming overload ratio (see Note 12) 100 60 x 103 Image-area well capacity Dark current Dark signal (see Note 13) TA = 40°C Pixel uniformity Column uniformity Shading TA = 21°C TC215-30 electrons nA/cm2 0.027 5 TC215-40 5 TC215-30 15 TC215-40 20 TC215-30 1.4 TC215-40 1.4 VO = 1/2 VU (see Note 10) mV mV mV 15% NOTES: 9. Sensitivity is measured at an integration time of 33 ms with a source temperature of 2859 K. A CM-500 filter is used. Sensitivity is measured at any illumination level that gives an output voltage level less than VU. 10. VU is the output voltage that represents the threshold of operation of antiblooming. VU ≈ 1/2 saturation signal. 11. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal. 12. Blooming is the condition in which charge is induced in an element by light incident on another element. Blooming overload ratio is the ratio of blooming exposure to saturation exposure. 13. Dark-signal level is measured from the dark dummy pixels. timing requirements MIN IAG1, IAG2 SRG1, SRG2 tr Rise time Fall time UNIT 10 RST1, RST2 10 TRG 200 ABG1, ABG2 100 IAG1, IAG2 200 SRG1, SRG2 tf MAX 200 ns 10 RST1, RST2 10 TRG 200 ABG1, ABG2 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 2-13 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 PARAMETER MEASUREMENT INFORMATION Blooming Point With Antiblooming Enabled VO Blooming Point With Antiblooming Disabled Dependent on Well Capacity Vsat (min) Level Dependent Upon Antiblooming Gate High Level Vuse (max) Vuse (typ) DR Vn Lux (light input) DR (dynamic range) + camera whiteVn clip voltage Vn = noise floor voltage Vsat (min) = minimum saturation voltage Vuse (max) = maximum usable voltage Vuse (typ) = typical user voltage (camera white clip) NOTES: A. Vuse (typ) is defined as the voltage determined to equal the camera white clip. This voltage must be less than Vuse (max). B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the Vuse (typ), the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera. Figure 13. Typical Vsat, Vuse Relationship 2-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 PARAMETER MEASUREMENT INFORMATION VIH min 100% 90% Intermediate Level 10% VIL max 0% tf tr Figure 14. Typical Clock Waveform for ABG1, ABG2, IAG1, and IAG2 VIH min 100% 90% 10% VIL max 0% tr tf Figure 15. Typical Clock Waveform for RST1, RST2, SRG1, SRG2, and TRG 1.5 V to 2.5 V SRG –9V – 9 V to –11 V 0% OUT 90% 100% CCD DELAY τ 10 ns 15 ns Sample and Hold Figure 16. SRG and CCD OUT Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-15 TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 APPLICATION INFORMATION VSS OUT VCC GND GND V VCC TMS3473B Master Oscillator V IAG1 ABG1 GT1 CBLNK ABG2 CL2 GT2 CL1 IAG2 CSYNC RST2 SH2 RST1 SH1 SRG1 TRG SRG2 CLK CBLNK CL2 CL1 CSYNC SH2 SH1 VCC 1 2 3 4 5 6 7 8 9 10 VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG– IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VAGB+ VSS 20 19 18 17 16 15 14 13 12 11 ABLVL 2N3904 12 V VABG – 100 Ω Parallel Driver User-Defined Timer OUT 2 1 kΩ VABG + TMS3473B V VCC 1 2 3 4 5 6 7 8 9 10 IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VAGB+ VSS VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG – 20 19 18 17 16 15 14 13 12 11 2N3904 12 V 100 Ω TC215 1 2 3 4 5 6 7 8 9 10 11 12 VABG – VABG + SN28846 VCC SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT VSS VSS SEL0 NC VCC SRG3OUT SRG2OUT SRG1OUT TRGOUT VCC SEL1 20 19 18 17 16 15 14 13 12 11 12 V SN28846 VCC SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT VSS VSS SEL0 NC VCC SRG3OUT SRG2OUT SRG1OUT TRGOUT VCC SEL1 OUT1 AMP GND OUT2 ADB SUB RST2 RST1 CDB SRG1 SRG2 TRG IDB ABG2 IAG2 ABG1 IAG1 SUB TDB SUB SUB IAG1 ABG1 IAG2 ABG2 24 23 22 21 20 19 18 17 16 15 14 13 Image Sensor DC VOLTAGES 12 V ADB 5V VCC – 10 V VSS 2V V – 2.5 V ABLVL 4V VABG + –6 V VABG – Serial Driver 1 2 3 4 5 6 7 8 9 10 1 kΩ ABLVL Parallel Driver 1 2 3 4 5 6 7 8 9 10 OUT 1 20 19 18 17 16 15 14 13 12 11 Serial Driver SUPPORT CIRCUITS DEVICE PACKAGE APPLICATION FUNCTION SN28846DW 20 pin small outline Serial driver Driver for TRG, SRG1, SRG2, RST1, RST2 TMS3473BDW 20 pin small outline Parallel driver Driver for IAG1, IAG2, ABG1, ABG2 Figure 17. Typical Application Circuit Diagram 2-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 V TC215 1024- × 1024-PIXEL CCD IMAGE SENSOR SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 MECHANICAL DATA The package for the TC215 consists of a ceramic base, a glass window, and a 24-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and fit into mounting holes with 2,54 mm (0.1 in) center-to-center spacings. 30,91 (1.217) 30,05 (1.183) 2,67 (0.105) NOM 2,54 (1.000) 4,93 (0.194) MAX 12,50 (0.492) NOM 3,81 (0.150) NOM 0,33 (0.013) 0,17 (0.007) 2,00 (0.079) NOM DIA +0.01 (+0.0004) 6,80 (0.268) 5,80 (0.228) 22,83 (0.899) 22,38 (0.881) Optical Center and Package Center (see Note C) 20,93 (0.824) 20,83 (0.820) 23,29 (0.917) 22,43 (0.883) T.P. 20,93 (0.824) 20,83 (0.820) 1,40 (0.055) 0,64 (0.025) 6,30 (0.248) 4,70 (0.185) 2,54 (0.100) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 7/94 NOTES: A. Each pin centerline is located within 2,54 mm (0.1 inch) of its true longitudinal position. B. The center of the package and the center of the image area are not coincident. C. Maximum rotation is ± 3.5°. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-17 SOCS014B – AUGUST 1989 – REVISED DECEMBER 1991 2-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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