MOTOROLA MC145192

Order this document
by MC145192/D
SEMICONDUCTOR TECHNICAL DATA
$" &
#% %"!&
Includes On–Board 64/65 Prescaler
The MC145192 is a low–voltage single–package synthesizer with serial
interface capable of direct usage up to 1.1 GHz. A special architecture makes
this PLL very easy to program because a byte–oriented format is utilized. Due
to the patented BitGrabber registers, no address/steering bits are required for
random access of the three registers. Thus, tuning can be accomplished via a
3–byte serial transfer to the 24–bit A register. The interface is both SPI and
MICROWIRE compatible.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145192 phase/frequency detector B φ R and φ V outputs can be
powered from 2.7 to 5.5 V. This is optimized for 3.0 V systems. The
phase/frequency detector A PDout output must be powered from 4.5 to 5.5 V,
and is optimized for a 5 volt supply.
This part includes a differential RF input which may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
F SUFFIX
SOG PACKAGE
CASE 751J
20
1
DT SUFFIX
TSSOP
CASE 948D
20
1
ORDERING INFORMATION
MC145192F
MC145192DT
SOG Package
TSSOP
PIN ASSIGNMENT
REFout
1
20
REFin
LD
2
19
DATA IN
φR
3
18
CLOCK
φV
4
17
ENABLE
VPD
PDout
5
16
OUTPUT A
6
15
OUTPUT B
GND
7
14
VDD
Rx
8
13
TEST 2
TEST 1
9
12
VCC
11
fin
Maximum Operating Frequency: 1100 MHz @ Vin = 200 mV p–p
fin 10
Operating Supply Current: 6 mA Nominal at 2.7 V
Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.0 V
Operating Supply Voltage Range of Phase Frequency Detector A
(VPD Pin) = 4.5 to 5.5 V
Operating Supply Voltage Range of Phase Detector B (VPD Pin) = 2.7 to 5.5 V
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
Operating Temperature Range: – 40° to 85°C
R Counter Division Range: (1 and) 5 to 8191
N Counter Division Range: 5 to 4095
A Counter Division Range: 0 to 63
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 2 Megabits per Second
Output A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
Power–Saving Standby Feature with Patented Orderly Recovery for Minimizing Lock Times,
Standby Current: 30 µA
Evaluation Kit Available (Part Number MC145192EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3
1/98
TN98012200

Motorola, Inc. 1998
MOTOROLA
MC145192
1
BLOCK DIAGRAM
DATA OUT
REFin
20
OSC OR
4–STAGE
DIVIDER
(CONFIGURABLE)
1
REFout
fR
13–STAGE R COUNTER
PORT
fV
DATA IN
ENABLE
16
OUTPUT A
13
3
DOUBLE–BUFFERED
BitGrabber R REGISTER
16 BITS
CLOCK
SELECT
LOGIC
2
LOCK DETECTOR
AND CONTROL
18
SHIFT
REGISTER
AND
CONTROL
LOGIC
19
8
BitGrabber C REGISTER
8 BITS
24
STANDBY
LOGIC
17
6
PHASE/FREQUENCY
DETECTOR A AND CONTROL
LD
Rx
PDout
POR
3 φ
R
4 φV
PHASE/FREQUENCY
DETECTOR B AND CONTROL
2
BitGrabber A REGISTER
24 BITS
INTERNAL
CONTROL
6
4
12
15
6–STAGE
A COUNTER
12–STAGE
N COUNTER
64/65
PRESCALER
MODULUS
CONTROL
LOGIC
OUTPUT B
(OPEN–DRAIN
OUTPUT)
11
fin
10
fin
INPUT
AMP
SUPPLY CONNECTIONS:
PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCALER)
PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)
13
TEST 2
9
TEST 1
MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)
Symbol
Parameter
Value
Unit
– 0.5 to + 6.0
V
VCC,
VDD
DC Supply Voltage (Pins 12 and 14)
VPD
DC Supply Voltage (Pin 5)
VDD – 0.5 to + 6.0
V
Vin
DC Input Voltage
– 0.5 to VDD + 0.5
V
Vout
DC Output Voltage,
except Output B, PDout, φR, φV
Output B, PDout, φR, φV
– 0.5 to VDD + 0.5
– 0.5 to VPD + 0.5
V
DC Input Current, per Pin (Includes VPD)
± 10
mA
Iout
DC Output Current, per Pin
± 20
mA
IDD
DC Supply Current, VDD and GND Pins
± 30
mA
PD
Power Dissipation, per Package
300
mW
Tstg
Storage Temperature
– 65 to + 150
°C
260
°C
Iin, IPD
TL
Lead Temperature, 1 mm from Case for
10 Seconds
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to
this high–impedance circuit.
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables
or Pin Descriptions section.
MC145192
2
MOTOROLA
ELECTRICAL CHARACTERISTICS (VDD = VCC = 2.7 to 5.0 V, Voltages Referenced to GND, TA = – 40° to 85°C, unless otherwise
stated; Phase/Frequency Detector A VPD = 4.5 to 5.5 V with VDD ≤ VPD; Phase/Frequency Detector B VPD = 2.7 to 5.5 V with VDD ≤ VPD)
Symbol
Parameter
Test Condition
Guaranteed
Limit
Unit
VIL
Maximum Low–Level Input Voltage
(Data In, Clock, Enable, REFin)
Device in Reference Mode, DC Coupled
0.2 x VDD
V
VIH
Minimum High–Level Input Voltage
(Data In, Clock, Enable, REFin)
Device in Reference Mode, DC Coupled
0.8 x VDD
V
VHys
Minimum Hysteresis Voltage
(Clock, Enable)
VDD = 2.7 V
VDD = 5.0 V
100
300
mV
VOL
Maximum Low–Level Output Voltage
(REFout, Output A)
Iout = 20 µA, Device in Reference Mode
0.1
V
VOH
Minimum High–Level Output Voltage
(REFout, Output A)
Iout = – 20 µA, Device in Reference Mode
VDD – 0.1
V
IOL
Minimum Low–Level Output Current
(REFout, LD)
Vout = 0.4 V
0.25
mA
IOL
Minimum Low–Level Output Current
(φR, φV)
Vout = 0.4 V
VDD, VPD = 2.7 V
0.36
mA
IOL
Minimum Low–Level Output Current
(Output A)
Vout = 0.4 V
0.6
mA
IOL
Minimum Low–Level Output Current
(Output B)
Vout = 0.4 V
1.0
mA
IOH
Minimum High–Level Output Current
(REFout, LD)
Vout = VDD – 0.4 V
– 0.25
mA
IOH
Minimum High–Level Output Current
(φR, φV)
Vout = VPD – 0.4 V
VDD, VPD = 2.7 V
– 0.36
mA
IOH
Minimum High–Level Output Current
(Output A Only)
Vout = VDD – 0.4 V
– 0.35
mA
Iin
Maximum Input Leakage Current
(Data In, Clock, Enable, REFin)
Vin = VDD or GND, Device in XTAL Mode
± 1.0
µA
Iin
Maximum Input Current
(REFin)
Vin = VDD or GND, Device in Reference Mode
± 150
µA
(PDout) Vout = VPD – 0.5 V or 0.5 V, Output in High–Impedance
State
± 200
nA
± 10
µA
IOZ
Maximum Output Leakage Current
(Output B) Output in High–Impedance State
ISTBY
IPD
IT
Maximum Standby Supply Current
(VDD + VPD Pins)
Vin = VDD or GND; Outputs Open; Device in Standby
Mode, Shut–Down Crystal Mode or REFout–Static–Low
Reference Mode; Output B Controlling VCC per Figure 22
30
µA
Maximum Phase Detector
Quiescent Current (VPD Pin)
Bit C6 = High Which Selects Phase Detector A,
PDout = Open, PDout = Static Low or High, Bit C4 = Low
Which is NOT Standby, IRx = 113 µA, VPD = 5.5 V
600
µA
Bit C6 = Low Which Selects Phase Detector B, φR and
φV = Open, φR and φV = Static Low or High, Bit
C4 = Low Which is NOT Standby
30
Total Operating Supply Current
(VDD + VPD + VCC Pins)
fin = 1.1 GHz; REFin = 13 MHz @ 1 V p–p;
Output A = Inactive and No Connect; VDD = VCC,
REFout, φV, φR, PDout, LD = No Connect;
Data In, Enable, Clock = VDD or GND, Phase Detector A
Off
*
mA
* The nominal values are:
6 mA at VDD = 2.7 V and VPD = 2.7 V
9 mA at VDD = 5.0 V and VPD = 5.5 V
These are not guaranteed limits.
MOTOROLA
MC145192
3
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PDout
(Iout ≤ 2 mA, VDD = VCC = 2.7 to 5.0 V, Voltages Referenced to GND, VDD = VCC ≤ VPD)
Parameter
Maximum Source Current Variation Part–to–Part
Maximum Sink–versus–Source Mismatch
Test Condition
Vout = 0.5 x VPD
Vout = 0.5 x VPD
(Note 3)
Output Voltage Range
Iout variation ≤ 20%
(Note 3)
VPD
Guaranteed
Limit
Unit
4.5
± 20
%
5.5
± 20
4.5
12
5.5
12
4.5
0.5 to 4.0
5.5
0.5 to 5.0
%
V
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value) / Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40° to 85°C.
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.0 V, TA = – 40° to 85°C, CL = 50 pF, Input tr = tf = 10 ns, VPD = 2.7 to 5.5 V with VDD ≤ VPD)
Symbol
fclk
Parameter
Serial Data Clock Frequency (Figure 1)
NOTE: Refer to Clock tw below
Guaranteed
Limit
Unit
dc to 2.0
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Output A (Selected as Data Out) (Figures 1 and 5)
200
ns
tPLH,
tPHL
Maximum Propagation Delay, Enable to Output A (Selected as Port) (Figures 2 and 5)
200
ns
tPZL,
tPLZ
Maximum Propagation Delay, Enable to Output B (Figures 2 and 6)
200
ns
tTLH,
tTHL
Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B
(Figures 1, 5, and 6)
200
ns
Maximum Input Capacitance — Data In, Clock, Enable
10
pF
Cin
TIMING REQUIREMENTS (VDD = VCC = 2.7 to 5.0 V, TA = – 40° to 85°C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
Guaranteed
Limit
Unit
tsu, th
Minimum Setup and Hold Times, Data In versus Clock (Figure 3)
50
ns
tsu, th,
trec
Minimum Setup, Hold and Recovery Times, Enable versus Clock (Figure 4)
100
ns
tw
Minimum Pulse Width, Enable (Figure 4)
*
cycles
tw
Minimum Pulse Width, Clock (Figure 1)
250
ns
Maximum Input Rise and Fall Times, Clock (Figure 1)
100
µs
tr, tf
* The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
MC145192
4
MOTOROLA
SWITCHING WAVEFORMS
tf
tr
VDD
90%
CLOCK 50%
10%
ENABLE
GND
GND
tw
tPLH
tw
1/fclk
OUTPUT A
tPLH
tPHL
50%
tPHL
tPLZ
90%
50%
10%
OUTPUT A
(DATA OUT)
VDD
50%
OUTPUT B
tTLH
tPZL
50%
10%
tTHL
Figure 1.
Figure 2.
VALID
tw
tw
VDD
VDD
ENABLE
50%
DATA IN
50%
GND
tsu
th
GND
th
tsu
VDD
trec
VDD
50%
CLOCK
GND
Figure 3.
CLOCK
50%
FIRST
CLOCK
LAST
CLOCK
GND
Figure 4.
+VPD
TEST POINT
TEST POINT
7.5 k
DEVICE
UNDER
TEST
CL*
DEVICE
UNDER
TEST
CL*
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 5. Test Circuit
Figure 6. Test Circuit
MOTOROLA
MC145192
5
LOOP SPECIFICATIONS (VDD = VCC = 2.7 to 5.0 V unless otherwise indicated, TA = – 40° to 85°C)
Guaranteed
Operating Range
Symbol
Parameter
Test Condition
Vin
Input Voltage Range, fin
(Figure 7)
100 MHz ≤ fin < 250 MHz
250 MHz ≤ fin ≤ 1100 MHz
fref
Input Frequency, REFin Externally Driven in
Reference Mode (Figure 8)
Vin ≥ 400 mV p–p
Min
Max
Unit
400
200
1500
1500
mV p–p
VDD = 2.7 V
VDD = 3.0 V
VDD = 3.5 V
VDD = 4.5 to 5 V
1
4.5
5.5
12
20
20
20
27
VDD = 2.7 V
VDD = 3.0 V
VDD = 3.5 V
VDD = 4.5 to 5 V
1
1.5
2
4.5
20
20
20
27
MHz
Vin ≥ 1 V p–p
fXTAL
fout
f
tw
tTLH,
tTHL
Cin
MHz
Crystal Frequency, Crystal Mode
(Figure 9)
C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
Capacitance
2
10
MHz
Output Frequency, REFout (Figures 10 and 12)
CL = 30 pF
dc
5
MHz
dc
1
MHz
Output Pulse Width, φR, φV, and LD
(Figures 11 and 12)
fR in Phase with fV, CL = 50 pF,
VPD = 2.7 V, VDD = VCC = 2.7 V
20
140
ns
Output Transition Times, LD, φV, and φR
(Figures 11 and 12)
CL = 50 pF, VPD = 2.7 V,
VDD = VCC = 2.7 V
—
80
ns
—
5
pF
Operating Frequency of the Phase Detectors
Input Capacitance, REFin
1000 pF
SINE WAVE
GENERATOR
fin
50 Ω*
OUTPUT A
(fv)
DEVICE
1000 pF
Vin
fin UNDER
TEST
TEST
POINT
0.01 µF
SINE WAVE
GENERATOR
REFin OUTPUT A
DEVICE
UNDER
TEST
REFout
VCC GND VDD
Vin
50 Ω*
VCC GND VDD
V+
Figure 7. Test Circuit
C2
V+
REFin OUTPUT A
DEVICE
UNDER
TEST
REFout
VCC GND VDD
Figure 8. Test Circuit–Reference Mode
TEST
POINT
(fR)
1 / f REFout
REFout
V+
50%
Figure 10. Switching Waveform
Figure 9. Test Circuit–Crystal Mode
TEST POINT
DEVICE
UNDER
TEST
tw
OUTPUT
50%
90%
10%
tTHL
Figure 11. Switching Waveform
MC145192
6
TEST
POINT
* Characteristic Impedance
* Characteristic Impedance
C1
(fR)
TEST
POINT
CL*
* Includes all probe and
fixture capacitance.
tTLH
Figure 12. Test Circuit
MOTOROLA
fin (PIN 11)
SOG PACKAGE
1
2
3
4
Marker
Frequency
(MHz)
Resistance
(Ω)
Capacitive
Reactance
(Ω)
Capacitance
(pF)
1
100
574
– 881
1.81
2
500
57.9
– 242
1.31
3
800
38.3
– 148
1.34
4
1100
31.6
– 103
1.40
Figure 13. Normalized Input Impedance at fin — Series Format (R + jX)
(100 MHz to 1100 MHz)
MOTOROLA
MC145192
7
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Data In (Pin 19)
Serial Data Input. The bit stream begins with the MSB and
is shifted in on the low–to–high transition of Clock. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 1). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by Enable.
CAUTION
The value programmed for the N–counter must
be greater than or equal to the value of the A–
counter.
The 13 LSBs of the R register are double–buffered. As indicated above, data is latched into the first buffer on a 16–bit
transfer. (The 3 MSBs are not double–buffered and have an
immediate effect after a 16–bit transfer.) The second buffer of
the R register contains the 13 bits for the R counter. This second buffer is loaded with the contents of the first buffer when
the A register is loaded (a 24–bit transfer). This allows presenting new values to the R, A, and N counters simultaneously. If this is not required, then the 16–bit transfer may
be followed by pulsing Enable low with no signal on the Clock
pin. This is an alternate method of transferring data to the
second buffer of the R register. See Figure 17.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided. That is, the registers may be accessed in any sequence. Data is retained in
the registers over a supply range of 2.7 to 5.0 V. The formats
are shown in Figures 15, 16, and 17.
Data In typically switches near 50% of VDD to maximize
noise immunity. This input can be directly interfaced to
CMOS devices with outputs guaranteed to switch near rail–
to–rail. When interfacing to NMOS or TTL devices, either a
level shifter (MC74HC14A, MC14504B) or pull–up resistor of
1 kΩ to 10 kΩ must be used. Parameters to consider when
sizing the resistor are worst–case IOL of the driving device,
maximum tolerable power consumption, and maximum data
rate.
Table 1. Register Access
(MSBs are shifted in first, C0, R0, and A0 are the LSBs)
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
24
Other Values ≤ 32
Values > 32
C Register
R Register
A Register
Not Allowed
See Figures 24
to 27
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
Clock (Pin 18)
Serial Data Clock Input. Low–to–high transitions on Clock
shift bits available at the Data pin, while high–to–low transitions shift bits from Output A (when configured as Data Out,
see Pin 16). The 24–1/2–stage shift register is static,
MC145192
8
allowing clock rates down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A register. See Table 1 and Figures 15, 16, and 17. The number of
clocks required for cascaded devices is shown in Figures 25
through 27.
Clock typically switches near 50% of V DD and has a
Schmitt–triggered input buffer. Slow Clock rise and fall times
are allowed. See the last paragraph of Data In for more
information.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the Clock pin must be held at
GND (with Enable being a don’t care) or Enable
must be held at the potential of the V+ pin (with
Clock being a don’t care) during power–up. As an
alternative, the bit sequence of Figure 18 may be
used.
Enable (Pin 17)
Active–Low Enable Input. This pin is used to activate the
serial interface to allow the transfer of data to/from the device. When Enable is in an inactive high state, shifting is inhibited and the port is held in the initialized state. To transfer
data to the device, Enable (which must start inactive high) is
taken low, a serial transfer is made via Data In and Clock,
and Enable is taken back high. The low–to–high transition on
Enable transfers data to the C or A registers and first buffer
of the R register, depending on the data stream length per
Table 1.
NOTE
Transitions on Enable must not be attempted
while Clock is high. This will put the device out of
synchronization with the microcontroller. Resynchronization occurs when Enable is high and
Clock is low.
This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of Data
In for more information.
For POR information, see the note for the Clock pin.
Output A (Pin 16)
Configurable Digital Output. Output A is selectable as fR,
fV, Data Out, or Port. Bits A22 and A23 in the A register control the selection; see Figure 16.
If A23 = A22 = high, Output A is configured as fR. This signal is the buffered output of the 13–stage R counter. The fR
signal appears as normally low and pulses high. The fR signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits R0 through R12 in the R register. Also, direct access to the phase detectors via the REFin
pin is allowed by choosing a divide value of one. See Figure 17. The maximum frequency at which the phase detectors operate is 1 MHz. Therefore, the frequency of fR should
not exceed 1 MHz.
If A23 = high and A22 = low, Output A is configured as fV.
This signal is the buffered output of the 12–stage N counter.
MOTOROLA
The fV signal appears as normally low and pulses high. The
fV signal can be used to verify the operation of the prescaler,
A counter, and N counter. The divide ratio between the fin
input and the fV signal is N × 64 + A. N is the divide ratio of
the N counter and A is the divide ratio of the A counter. These
ratios are determined by bits loaded into the A register. See
Figure 16. The maximum frequency at which the phase detectors operate is 1 MHz. Therefore, the frequency of fV
should not exceed 1 MHz.
If A23 = low and A22 = high, Output A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the Clock input. Upon power up, Output A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, Output A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit is
high.
Output B (Pin 15)
Open–Drain Digital Output. This signal is a general–purpose digital output which may be used as an MCU port expander. This signal is low when the Out B bit (C0) of the
C register is low. When the Out B bit is high, Output B assumes the high–impedance state. Output B may be pulled up
through an external resistor or active circuitry to any voltage
less than or equal to the potential of the VPD pin. Note: the
maximum voltage allowed on the VPD pin is 5.5 V for the
MC145192.
Upon power–up, power–on reset circuitry forces Output B
to a low level.
REFERENCE PINS
REFin and REFout (Pins 20 and 1)
Configurable Pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 17.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–resonant crystal. Frequency–setting capacitors of appropriate
values as recommended by the crystal supplier are connected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external resistor of 1 MΩ to 15 MΩ is connected directly across the pins
to ensure linear operation of the amplifier. The device is designed to operate with crystals up to 10 MHz; the required
connections are shown in Figure 9. To turn on the oscillator,
bits R15, R14, and R13 must have an octal value of one (001
in binary). This is the active–crystal mode shown in
Figure 17. In this mode, the crystal oscillator runs and the
R Counter divides the crystal frequency, unless the part is in
standby. If the part is placed in standby via the C register, the
oscillator runs, but the R counter is stopped. However, if bits
R15 to R13 have a value of 0, the oscillator is stopped, which
saves additional power. This is the shut–down crystal mode
shown in Figure 17, and can be engaged whether in standby
or not.
In the reference mode, REFin (Pin 20) accepts a signal up
to 20 MHz from an external reference oscillator, such as a
TCXO. A signal swinging from at least the VIL to VIH levels
MOTOROLA
listed in the Electrical Characteristics table may be directly
coupled to the pin. If the signal is less than this level, ac coupling must be used as shown in Figure 8. The ac–coupled
signal must be at least 400 mV p–p. Due to an on–board resistor which is engaged in the reference modes, an external
biasing resistor tied between REF in and REF out is not
required.
With the reference mode, the REFout pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REFout is
the REFin frequency divided by 16. In addition, Figure 17
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REFout pin is
5 MHz for VDD to VSS swing. Therefore, for REFin frequencies above 5 MHz, the one–to–one ratio may not be used for
large signal swing requirements. Likewise, for REFin frequencies above 10 MHz, the ratio must be more than two.
If REFout is unused, an octal value of two should be used
for R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption and
electromagnetic interference (EMI).
LOOP PINS
fin and fin (Pins 11 and 10)
Frequency Input from the VCO. These pins feed the on–
board RF amplifier which drives the 64/65 prescaler. These
inputs may be fed differentially. However, they are usually
used in a single–ended configuration as shown in Figure 7.
Note that fin is driven while fin must be tied to ground via a
capacitor.
Motorola does not recommend driving fin while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
PDout (Pin 6)
Single–Ended Phase/Frequency Detector Output. This is
a 3–state current–source/sink output for use as a loop error
signal when combined with an external low–pass filter. The
phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is
described below and is shown in Figure 19.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: current–
sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
MC145192
9
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: current–
sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the floating state
by utilization of the disable feature in the C register (bit C6).
This is a patented feature. Similarly, PDout is forced to the
floating state when the device is put into standby (STBY bit
C4 = high).
The PDout circuit is powered by VPD. The phase detector
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PDout current divided by 2π.
φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs.
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented technique, the detector’s dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a
linear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 19.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: φV = negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV = essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time period when
both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR = negative pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR = essentially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time period when
both pulse low in phase
These outputs can be enabled, disabled, and interchanged via C register bits C6 or C4. This is a patented feature. Note that when disabled or in standby, φR and φV are
forced to their rest condition (high state).
The φR and φV output signal swing is approximately from
GND to VPD.
The LD output signal swing is approximately from GND to
VDD.
Rx (Pin 8)
External Resistor. A resistor tied between this pin and
GND, in conjunction with bits in the C register, determines
the amount of current that the PDout pin sinks and sources.
When bits C2 and C3 are both set high, the maximum current
is obtained at PDout; see Figure 15 for other values of current. To achieve a maximum current of 2 mA, the resistor
should be about 22 kΩ when VPD is 5 V.
When the φR and φV outputs are used, the Rx pin may be
floated.
TEST POINT PINS
Test 1 (Pin 9)
Modulus Control Signal. This pin may be used in conjunction with the Test 2 pin for access to the on–board 64/65
prescaler. When Test 1 is low, the prescaler divides by 65.
When high, the prescaler divides by 64.
CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin may be
attached to an isolated pad with no trace.
Test 2 (Pin 13)
Prescaler Output. This pin may be used to access to the
on–board 64/65 prescaler output.
CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin may be
attached to an isolated pad with no trace.
POWER SUPPLY PINS
VDD (Pin 14)
Positive Supply Potential. This pin supplies power to the
main CMOS digital portion of the device. The voltage range
is + 2.7 to + 5.0 V with respect to the GND pin.
For optimum performance, VDD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
LD (Pin 2)
Lock Detector Output. This output is essentially at a high
level with narrow low–going pulses when the loop is locked
(fR and fV of the same phase and frequency). The output
pulses low when fV and fR are out of phase or different frequencies. LD is the logical ANDing of φR and φV. See Figure 19.
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip initialization circuitry disables LD to a static low logic level to prevent
a false lock signal. If unused, LD should be disabled and left
open.
MC145192
10
VCC (Pin 12)
Positive Supply Potential. This pin supplies power to the
RF amp and 64/65 prescaler. The voltage range is + 2.7 to
+ 5.0 V with respect to the GND pin. In the standby mode, the
VCC pin still draws a few milliamps from the power supply.
This current drain can be eliminated with the use of transistor
Q1 as shown in Figure 23.
For optimum performance, VCC should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
MOTOROLA
VPD (Pin 5)
Positive Supply Potential. This pin supplies power to both
phase/frequency detectors A and B. The voltage applied on
this pin must be ≥ VDD but not more than 5.5 V. The voltage
range for V PD is 4.5 to 5.5 V with respect to the GND pin
when using PD OUT and 2.7 to 5.5 V when using φR, φV outputs.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND (Pin 7)
Common ground.
100
90
PDout CURRENT SET TO 100%;
PDout VOLTAGE IS FORCED TO ONE–HALF OF VPD.
80
Rx, EXTERNAL RESISTOR (kΩ )
70
60
50
40
30
20
VPD = 5.5 V
VPD = 5.0 V
VPD = 4.5 V
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
Iout, SOURCE CURRENT (mA)
Nominal MC145192 PDout Source Current vs Rx Resistance
NOTE: The MC145192 is optimized for Rx values in the 18 kΩ to 40 kΩ range. For example, to achieve 0.3 mA of output current,
it is preferable to use a 30–kΩ resistor for Rx and bit settings for 25% (as shown in Table 3).
Figure 14.
MOTOROLA
MC145192
11
ENABLE
1
CLOCK
2
3
4
5
6
7
MSB
C7
DATA IN
*
8
LSB
C6
C5
C4
C3
C2
C1
C0
* At this point, the new byte is transferred to the C register and stored. No other registers are affected.
C7 – POL:
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout
and interchanges the φR function with φV as depicted in Figure 19. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.
C6 – PDA/B:
Selects which phase/frequency detector is to be used. When set high, enables the output of phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR and φV to the static
high state. When cleared low, phase/frequency detector B is enabled (φR and φV) and phase/frequency
detector A is disabled with PDout forced to the high–impedance state. This bit is cleared low at power
up.
C5 – LDE:
Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.
C4 – STBY:
When set high, places the CMOS section of device, which is powered by the VDD and VPD pins,
in the standby mode for reduced power consumption: PDout is forced to the high–impedance state,
φR and φV are forced high, the A, N, and R counters are inhibited from counting, and the Rx current
is shut off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change).
C5 high forces LD static high. During standby, data is retained in the A, R, and C registers. The
condition of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and
R15. However, if REFout = static low is selected, the internal feedback resistor is disconnected and
the input is inhibited when in standby; in addition, the REFin input only presents a capacitive load.
NOTE: Standby does not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in 2 steps. First, the REFin (only in one mode)
resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and fV signals
are inhibited from toggling the phase/frequency detectors and lock detector. Second, when the first
fV pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together. At
this point, the fR and fV pulses are enabled to the phase and lock detectors. This is a patented feature.
C3, C2 – I2, I1:
Controls the PDout source/sink current per Tables 2 and 3. With both bits high, the maximum current
(as set by Rx) is available. Also, see C1 bit description.
C1 – Port:
When the Output A pin is selected as “Port” via bits A22 and A23, C1 determines the state of Output A.
When C1 is set high, Output A is forced high; C1 low forces Output A low. When Output A is not
selected as “Port,” C1 controls whether the PDout step size is 10% or 25%. (See Tables 2 and 3.)
When low, steps are 10%. When high, steps are 25%. Default is 10% steps when Output A is selected
as “Port.” The Port bit is not affected by the standby mode.
C0 – Out B:
Determines the state of Output B. When C0 is set high, Output B is high–impedance; C0 low forces
Output B low. The Out B bit is not affected by the standby mode. This bit is cleared low at power
up.
Figure 15. C Register Access and Format (8 Clock Cycles Are Used)
Table 2. PDout Current, C1 = Low with Output A NOT
Selected as “Port”; Also, Default Mode When
Output A Selected as “Port”
C3
C2
0
0
1
1
0
1
0
1
MC145192
12
PDout Current
70%
80%
90%
100%
Table 3. PDout Current, C1 = High with Output A NOT
Selected as “Port”
C3
C2
PDout Current
0
0
1
1
0
1
0
1
25%
50%
75%
100%
MOTOROLA
MOTOROLA
DATA IN
CLOCK
ENABLE
MSB
1
A22
2
3
4
A19
5
A18
6
A17
7
A16
8
A15
9
A14
10
A13
11
A12
12
A11
13
A10
14
A9
15
A8
16
A7
17
A6
18
A5
19
20
21
A2
22
23
LSB
24
NOTE 3
0
1
0
1
PORT
DATA OUT
fV
fR
1
1
BOTH BITS
MUST BE
HIGH
A20
A21
F
F
F
E
0
1
2
3
4
5
6
7
.
.
.
HEXADECIMAL VALUE
FOR N COUNTER
F
0
0
0
0
0
0
0
0
.
.
.
F
0
0
0
0
0
0
0
0
.
.
.
N COUNTER = ÷ 4095
N COUNTER = ÷ 4094
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
N COUNTER = ÷ 5
N COUNTER = ÷ 6
N COUNTER = ÷ 7
0
1
2
3
.
.
.
E
F
0
1
.
.
.
F
0
0
0
0
.
.
.
3
3
4
4
.
.
.
F
= ÷0
= ÷1
= ÷2
= ÷3
A COUNTER
A COUNTER
A COUNTER
A COUNTER
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
A COUNTER = ÷ 62
A COUNTER = ÷ 63
A0
A1
HEXADECIMAL VALUE
FOR A COUNTER
A3
A4
NOTES:
1. A power–on initialize circuit forces the Output A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register’s second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.
BINARY OUTPUT A
VALUE FUNCTION
(NOTE 1)
0
0
1
1
A23
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Figure 16. A Register Access and Format (24 Clock Cycles are Used)
MC145192
13
ENABLE
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
R15
DATA IN
16
NOTE NOTE
4
5
LSB
R14
R13
R12
R11
R10
0 CRYSTAL MODE, SHUT DOWN
1 CRYSTAL MODE, ACTIVE
2 REFERENCE MODE, REFin ENABLED and REFout
STATIC LOW
3 REFERENCE MODE, REFout = REFin (BUFFERED)
4 REFERENCE MODE, REFout = REFin/2
5 REFERENCE MODE, REFout = REFin/4
6 REFERENCE MODE, REFout = REFin/8 (NOTE 3)
7 REFERENCE MODE, REFout = REFin/16
OCTAL VALUE
R9
0
0
0
0
0
0
0
0
0
·
·
·
1
1
R8
0
0
0
0
0
0
0
0
0
·
·
·
F
F
R7
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
1
2
3
4
5
6
7
8
·
·
·
E
F
R6
R5
R4
R3
R2
R1
R0
NOT ALLOWED
R COUNTER = ÷ 1 (NOTE 6)
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
R COUNTER = ÷ 5
R COUNTER = ÷ 6
R COUNTER = ÷ 7
R COUNTER = ÷ 8
R COUNTER = ÷ 8190
R COUNTER = ÷ 8191
BINARY VALUE
HEXADECIMAL VALUE
NOTES:
1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
3. A power–on initialize circuit forces a default REFin to REFout ratio of eight.
4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12
are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet
and retains the previous ratio loaded. The C and A registers are not affected.
5. At this point, bits R0 through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio
after completing the rest of the present count cycle. Clock must be low during the Enable pulse, as shown. Also, see note 3 of Figure 16
for an alternate method of loading the second buffer in the R register. The C and A registers are not affected. The first buffer of the R register is not affected.
6. Allows direct access to reference input of phase/frequency detectors.
Figure 17. R Register Access and Format (16 Clock Cycles Are Used)
MC145192
14
MOTOROLA
100 ns MINIMUM
ENABLE
CLOCK
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
DATA IN
NOTE: It may not be convenient to control the Enable or Clock pins high during power up per the Pin Descriptions. If this is the case,
the part may be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the Clock must remain high at least 100 ns after Enable is brought high. Note that 3 groups of 5 bits are needed.
Figure 18. Initializing the PLL through the Serial Port
fR
REFERENCE
REFin ÷ R
fV
FEEDBACK
fin ÷ (N x 64 + A)
VH
VL
VH
VL
SOURCING CURRENT
*
FLOAT
PDout
φR
φV
LD
SINKING CURRENT
VH
VL
VH
VL
VH
VL
VH = High voltage level
VL = Low voltage level
* At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
NOTE: The PDout either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output
is high impedance and the voltage at that pin is determined by the low pass filter capacitor. PDout, φR, and φV are shown with
the polarity bit (POL) = low; see Figure 15 for POL.
Figure 19. Phase/Frequency Detectors and Lock Detector Output Waveforms
MOTOROLA
MC145192
15
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency synthesizers.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REFin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REFin
may be used. See Figure 8.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar
publications.
DESIGN AN OFF–CHIP REFERENCE
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 20 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven; monitor the output
frequency (fR) at Output A as a function of supply voltage.
(REFout is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
Note that the oscillator start–up time is proportional to the
value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful.
See Table 4.
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin. (See Figure 8.) For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
FREQUENCY
SYNTHESIZER
REFin
R1*
USE OF THE ON–CHIP OSCILLATOR CIRCUITRY
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 20.
The crystal should be specified for a loading capacitance,
CL , which does not exceed approximately 20 pF when used
at the highest operating frequency of 10 MHz. Assuming
R1 = 0 Ω, the shunt load capacitance, CL , presented across
the crystal can be estimated to be:
CL =
CinCout
+ Ca + Cstray +
Cin + Cout
C1
C2
* May be needed in certain cases. See text.
Figure 20. Pierce Crystal Oscillator Circuit
Ca
REFin
REFout
Cin
C1 • C2
Cout
C1 + C2
Cstray
where
Cin = 5 pF (see Figure 21)
Cout = 6 pF (see Figure 21)
Ca = 1 pF (see Figure 21)
C1 and C2 = external capacitors (see Figure 20)
Cstray = the total equivalent external circuit stray capacitance appearing across the crystal terminals
The oscillator can be “trimmed” on–frequency by making
either a portion or all of C1 variable. The crystal and associated components must be located as close as possible to
the REF in and REF out pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
appropriate stray value to the values for C in and C out . For
this approach, the term Cstray becomes zero in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 22. The maximum drive level specified
MC145192
16
REFout
Rf
Figure 21. Parasitic Capacitances of the Amplifier
and Cstray
RS
1
2
CS
LS
1
2
CO
1
Re
Xe
2
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 22. Equivalent Crystal Networks
MOTOROLA
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
Table 4. Partial List of Crystal Manufacturers
Motorola — Internet Address http://motorola.com
(Search for resonators)
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend one supplier over another and in no way suggests
that this is a complete listing of crystal manufacturers.
MOTOROLA
MC145192
17
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
(A)
PDout
Kφ KVCO
NC
ωn =
VCO
R
Kφ KVCOC
N
ζ = R
2
C
=
ωnRC
2
1 + sRC
Z(s) =
sC
NOTE:
For (A), using Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/
filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′ should be
chosen such that ωn is not significantly affected.
(B)
R2
φR
R1
–
φV
+
R1
R2
C
C
A
Kφ KVCO
NCR1
ωn =
VCO
ζ =
ωnR2C
2
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
R2sC + 1
R1sC
NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the
midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not
significantly affect ωn.
* The φR and φV outputs are fed to an external combiner/loop filter. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = IPDout / 2π amps per radian for PDout
Kφ (Phase Detector Gain) = VPD / 2π volts per radian for φV and φR
2π∆fVCO
KVCO (VCO Transfer Function) =
radians per volt
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ωn ≈ (2πfR / 50) where fR
is the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional
filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253/D, An Improved PLL Design Method Without ωn and ζ, Motorola Semiconductor Products, Inc., 1995.
MC145192
18
MOTOROLA
THRESHOLD
DETECTOR
+3 V
1 REF
out
2 LD
INTEGRATOR
LOW–PASS
FILTER
3 φR
4 φV
ENABLE
6
7
VPD
OUTPUT A
PDout
OUTPUT B
GND
8
NC
20
DATA IN 19
18
CLOCK
5
+3V
REFin
9
10
Rx
TEST 1
fin
VDD
TEST 2
VCC
fin
MCU
17
GENERAL–PURPOSE
DIGITAL OUTPUT
16
15
+3 V
14
13
NC
Q1
NOTE 2
12
11
1000 pF
UHF
VCO
UHF OUTPUT
BUFFER
NOTES:
1. When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked
Loop — Low–Pass Filter Design page for additional information.
2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section of the device
to be shut down via use of the general–purpose digital pin, Output B. If the standby feature is not needed,
tie Pin 12 directly to the power supply.
3. For optimum performance, bypass the VCC, VDD, and VPD pins to GND with low–inductance capacitors.
4. The R counter is programmed for a divide value = REFin / fR. Typically, fR is the tuning resolution required
for the VCO. Also, the VCO frequency divided by fR = NT = N x 64 + A; this determines the values (N, A)
that must be programmed into the N and A counters, respectively.
Figure 23. Example Application
DEVICE #1
DATA IN
OUTPUT A
CLOCK ENABLE (DATA OUT)
DEVICE #2
DATA IN
OUTPUT A
CLOCK ENABLE (DATA OUT)
CMOS
MCU
OPTIONAL
NOTE: See related Figures 25, 26, and 27.
Figure 24. Cascading Two Devices
MOTOROLA
MC145192
19
MC145192
20
CLOCK
ENABLE
X
1
X
2
7
X
8
C7
9
C6
10
15
16
X
17
X
18
23
X
24
25
X
26
31
X
32
33
34
39
40
*
C REGISTER BITS OF DEVICE #2
IN FIGURE 23
C0
X
*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.
DATA IN
C6
C0
C REGISTER BITS OF DEVICE #1
IN FIGURE 23
C7
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Figure 25. Accessing the C Registers of Two Cascaded Devices
MOTOROLA
MOTOROLA
CLOCK
ENABLE
X
1
X
2
8
A23
9
10
15
16
17
23
24
25
31
32
33
39
40
46
47
48
55
56
*
A22
A15
A8
A REGISTER BITS OF DEVICE #2
IN FIGURE 23
A16
A7
A0
A23
A9
A8
A REGISTER BITS OF DEVICE #1
IN FIGURE 23
A16
A0
*At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the 13 LSBs in each of the first buffers of the R registers are
transferred to the respective R register’s second buffer. Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.
DATA IN
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Figure 26. Accessing the A Registers of Two Cascaded Devices
MC145192
21
MC145192
22
CLOCK
ENABLE
X
1
X
2
8
9
10
15
16
17
23
24
25
31
32
33
39
40
41
47
48
NOTE 1 NOTE 2
R15
R14
R7
R REGISTER BITS OF DEVICE #2
IN FIGURE 23
R8
R0
X
X
R15
R7
R REGISTER BITS OF DEVICE #1
IN FIGURE 23
R8
R0
NOTES APPLICABLE TO EACH DEVICE:
1. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through R12 are loaded into the first buffer in the double–
buffered section of the R register. Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded. The C and A registers are not affected.
2. At this point, the bits R0 through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count
cycle. Clock must be low during the Enable pulse, as shown. Also, see note of Figure 25 for an alternate method of loading the second buffer in the R register. The C and A registers
are not affected. The first buffer of the R register is not affected.
DATA IN
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Figure 27. Accessing the R Registers of Two Cascaded Devices
MOTOROLA
PACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 751J–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
-A20
11
1
10
-BJ
G
S
K
10 PL
0.13 (0.005)
B
M
M
DIM
A
B
C
D
G
J
K
L
M
S
C
D
0.13 (0.005)
0.10 (0.004)
L
20 PL
M
T B
-TA
S
S
M
SEATING
PLANE
MILLIMETERS
MIN
MAX
12.55 12.80
5.40
5.10
2.00
—
0.45
0.35
1.27 BSC
0.23
0.18
0.85
0.55
0.20
0.05
7°
0°
7.40
8.20
INCHES
MIN
MAX
0.494 0.504
0.201 0.213
0.079
—
0.014 0.018
0.050 BSC
0.007 0.009
0.022 0.033
0.002 0.008
7°
0°
0.291 0.323
DT SUFFIX
TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)
CASE 948D–03
A
20X
0.200 (0.004)
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE –U–.
K REF
M
T
11
L
B
PIN 1
IDENTIFICATION
10
1
C
-U0.100 (0.004)
-T-
D
SEATING
PLANE
H
G
A
K
K1
J1
M
J
SECTION A-A
MOTOROLA
A
F
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
–––
6.60
4.30
4.50
–––
1.20
0.05
0.25
0.45
0.55
0.65 BSC
0.275
0.375
0.09
0.24
0.09
0.18
0.16
0.32
0.16
0.26
6.30
6.50
0°
10°
INCHES
MIN
MAX
–––
0.260
0.169
0.177
–––
0.047
0.002
0.010
0.018
0.022
0.026 BSC
0.011
0.015
0.004
0.009
0.004
0.007
0.006
0.013
0.006
0.010
0.248
0.256
0°
10 °
MC145192
23
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
Mfax: [email protected] – TOUCHTONE 1–602–244–6609
Motorola Fax Back System
– US & Canada ONLY 1–800–774–1848
– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/
MC145192
24
◊
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CUSTOMER FOCUS CENTER: 1–800–521–6274
MC145192/D
MOTOROLA