IRF IRL540N

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PD - 9.1495
IRL540N
PRELIMINARY
HEXFET® Power MOSFET
l
l
l
l
l
l
Logic-Level Gate Drive
Advanced Process Technology
Isolated Package
High Voltage Isolation = 2.5KVRMS …
Sink to Lead Creepage Dist. = 4.8mm
Fully Avalanche Rated
D
VDSS = 100V
RDS(on) = 0.044Ω
G
ID = 30A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 watts. The low thermal
resistance and low package cost of the TO-220
contribute to its wide acceptance throughout the
industry.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Units
30
21
120
94
0.63
± 16
310
18
9.4
4.3
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
To Order
Typ.
Max.
Units
–––
0.50
–––
1.6
–––
62
°C/W
8/14/96
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IRL540N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
100
–––
–––
–––
–––
1.0
14
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
11
81
39
62
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
1800
350
170
V(BR)DSS
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, I D = 250µA
––– V/°C Reference to 25°C, I D = 1mA
0.044
VGS = 10V, ID = 18A „
0.053
Ω
VGS = 5.0V, I D = 18A „
0.063
VGS = 4.0V, I D = 15A „
2.0
V
VDS = VGS , ID = 250µA
–––
S
VDS = 25V, I D = 18A
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
74
ID = 18A
9.4
nC VDS = 5.0V
38
VGS = 5.0V, See Fig. 6 and 13 „
–––
VDD = 50V
–––
I D = 18A
ns
–––
RG = 5.0Ω, VGS = 5.0V
–––
RD = 2.7Ω, See Fig. 10 „
Between lead,
–––
nH
6mm (0.25in.)
G
from package
–––
and center of die contact
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) †
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
30
––– –––
showing the
A
G
integral reverse
––– ––– 120
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 18A, VGS = 0V „
––– 190 290
ns
TJ = 25°C, IF = 18A
––– 1.1 1.7
µC di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 1.9mH
RG = 25Ω, IAS = 18A. (See Figure 12)
.
ƒ I SD ≤ 18A, di/dt ≤ 180A/µs, VDD ≤ V(BR)DSS ,
TJ ≤ 175°C
„ Pulse width ≤ 300µs; duty cycle ≤ 2%
To Order
D
S
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IRL540N
ID , Drain-to-Source Current (A)
TOP
BOTTOM
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
2.5V
TOP
ID , Drain-to-Source Current (A)
1000
100
10
2.5V
20µs PULSE WIDTH
T J = 25°C
1
0.1
1
10
BOTTOM
100
10
2.5V
A
20µs PULSE WIDTH
T J = 175°C
1
100
0.1
V DS , Drain-to-Source Voltage (V)
1
10
A
100
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics,
TJ = 25oC
Fig 2. Typical Output Characteristics,
TJ = 175oC
1000
3.0
I D = 30A
2.5
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
2.5V
100
TJ = 25°C
TJ = 175°C
10
V D S = 50V
20µs PULSE WIDTH
1
2
4
6
8
10
A
2.0
1.5
1.0
0.5
V G S = 10V
0.0
V G S , Gate-to-Source Voltage (V)
-60 -40 -20
0
20
40
60
80
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 3. Typical Transfer Characteristics
To Order
A
100 120 140 160 180
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IRL540N
3000
+gsC
15
f = 1MHz
, Cgd SHORTED
ds
gd
2000
C, Capacitance (pF)
V D S = 80V
V D S = 50V
V D S = 20V
12
C iss
C oss
1000
I D = 18A
gd
+dsC
V G S , Gate-to-Source Voltage (V)
V G S= 0V,
C iss = C
C rss= C
C oss= C
C rss
0
9
6
3
A
1
10
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
V DS , Drain-to-Source Voltage (V)
20
40
60
80
A
100
Q G, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
100
I D , Drain Current (A)
I SD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R DS(on)
TJ = 175°C
TJ = 25°C
10
100
10µs
100µs
10
1ms
VG S = 0V
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
A
1
1.8
1
10ms
A
10
100
V DS, Drain-to-Source Voltage (V)
V SD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
T C = 25°C
T J = 175°C
Single Pulse
Fig 8. Maximum Safe Operating Area
To Order
1000
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IRL540N
30
RD
VDS
VGS
25
D.U.T.
I D, Drain Current (Amps)
RG
+
- VDD
20
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
10
Fig 10a. Switching Time Test Circuit
VDS
5
90%
A
0
25
50
75
100
125
150
175
T C, Case Temperature (°C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z
thJC
)
10
1
D = 0.50
0.20
0.10
0.1
PD M
0.05
t
0.02
0.01
t
2
N ote s:
1. Duty fac tor D = t / t 2
1
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
1
2. Pe ak TJ = P DM x Z thJ C + T C
0.0001
0.001
0.01
0.1
t 1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
To Order
A
1
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IRL540N
800
15 V
L
VD S
D .U .T
RG
IA S
10V
tp
D R IV E R
+
V
- DD
A
0 .0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
E A S , Single Pulse Avalanche Energy (mJ)
TOP
BOTTOM
I D
7.3A
13A
18A
600
400
200
A
0
25
50
V (BR )D SS
75
100
125
150
Starting T J , Junction Temperature (°C)
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
12V
QG
.2µF
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
To Order
175
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IRL540N
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
Driver Gate Drive
Period
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
-
VDD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
To Order
*
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IRL540N
Package Outline
TO-220AB Outline
Dimensions are shown in millimeters (inches)
2 . 8 7 ( .1 1 3 )
2 . 6 2 ( .1 0 3 )
1 0 . 5 4 (. 4 1 5 )
1 0 . 2 9 (. 4 0 5 )
-B -
3 . 7 8 (. 1 4 9 )
3 . 5 4 (. 1 3 9 )
4 . 6 9 ( .1 8 5 )
4 . 2 0 ( .1 6 5 )
-A -
1 .3 2 (. 0 5 2 )
1 .2 2 (. 0 4 8 )
6 . 4 7 (. 2 5 5 )
6 . 1 0 (. 2 4 0 )
4
1 5 . 2 4 ( .6 0 0 )
1 4 . 8 4 ( .5 8 4 )
1 . 1 5 ( .0 4 5 )
M IN
1
2
1 4 . 0 9 (.5 5 5 )
1 3 . 4 7 (.5 3 0 )
3X
L E A D A S S IG N M E N T S
1 - G A TE
2 - D R AIN
3 - SO URCE
4 - D R AIN
3
1 .4 0 (. 0 5 5 )
1 .1 5 (. 0 4 5 )
4 . 0 6 (. 1 6 0 )
3 . 5 5 (. 1 4 0 )
0 . 9 3 ( .0 3 7 )
3 X 0 . 6 9 ( .0 2 7 )
0 .3 6 (. 0 1 4 )
3 X 0 . 5 5 (. 0 2 2 )
0 . 4 6 (. 0 1 8 )
M
B A
M
2 .9 2 (. 1 1 5 )
2 .6 4 (. 1 0 4 )
2 . 5 4 ( .1 0 0 )
2X
NO TE S :
1 D I M E N S IO N I N G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 .
2 C O N T R O L L I N G D IM E N S IO N : I N C H
3 O U T L IN E C O N F O R M S T O J E D E C O U T L I N E T O -2 2 0 A B .
4 H E A T S IN K & L E A D M E A S U R E M E N T S D O N O T IN C L U D E B U R R S .
Part Marking Information
TO-220AB
E XEAM
PLE
: T: HITSHI IS
A NA NIRFIRF
1010
X AM
PLE
S IS
1010
W IT
A SASSESMB
LY LY
WHIT H
E MB
LOLO
T CO
DEDE
9B 9B
1M1M
T CO
A A
IN TE
R NA
T ION
A LA L
IN TE
R NA
T ION
R EC
T IFTIER
R EC
IF IER
IR FIR1010
F 1010
LOLO
GOGO
9246
9246
9B 9B 1M1M
A SASSEM
B LY
S EM
B LY
LOLO
T T COCO
DEDE
P APRT
NUNU
M BE
R R
A RT
M BE
D ADTE
C OD
E E
A TE
C OD
(Y YW
W )W )
(Y YW
Y YY =Y YE
A RA R
= YE
WW
W W= W
= EWEK
E EK
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Data and specifications subject to change without notice.
8/96
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