ES3880 Video CD MPEG Processor Product Brief DESCRIPTION The ES3880 Video CD MPEG processor is ESS’ third generation highly integrated, optimal quality, and costeffective single chip solution for Video CD players. The ES3880 is the best quality available for both video and audio and easily passes the highest graded level for the China VCD standard. The ES3880 integrates MPEG-1 video and audio processing and a full-fledged MPEG system bit stream parser. The ES3880 can be used as a microcontroller to provide system control, while also performing such basic video operations as arbitrary scaling and video filtering. The MPEG-1 system layer bitstream is decoded at up to 9 Mb/s at Standard Intermediate Format (SIF) resolution with a picture rate of 30 frames per second. Two channels of MPEG-1 Layer 1 or Layer 2 audio are decoded simultaneously. The ES3880 supports SmartScale advanced scaling techniques, along with SmartStream for audio and video error concealment, and SmartZoom for enabling in/out zooming of a particular area of a still picture or movie. Additional features include DiscScan, TrackScan, QuickScan, OnScreen-Display (OSD), Karaoke, Playback Control (PBC) for Video CD 2.0, and entertainment game software. System control and house-keeping functions (keypad and remote control) are also provided. The ES3880 can be implemented with the ES3883 Video CD Video Encoder, which integrates most of the analog discrete components required for a Video CD player. Figure 1 shows a typical Video CD system using the ES3880 and the companion ES3883 video encoder. When the ES3880 and ES3883 are used in the design, enhanced support for 3DSound and SurroundSound is realized, along with support for interactive games. The ES3880 is available in an industry-standard 100-pin Plastic Quad Flat Pack (PQFP) package. FEATURES • • • • • • • • • • • • • • • • • • • • • • • • • Programmable Multimedia Processor (PMP) architecture MPEG-1 audio/video decoder and system parser CD block decoder functions Video interlacing hardware Color Space Conversion (CSC) STC interpretation and video/audio Phase-lock Loop (PLL) Supports both 8- and 16-bit YUV output 256/384 frame sampling frequency for audio system clock Programmable master clock for external audio DAC Independent bit clock for audio transmit and receive SmartScale video scaling supports X- and Y-axis interpolation SmartZoom supports 4X picture enlargement and reduction SmartStream supports audio and video bit stream error concealment SmartVocal: cancels the vocal on an audio-CD Karaoke function Video Fader for fading video image (in and out) On-screen-Display (OSD) Playback Control (PBC) for Video CD 2.0 Trick mode functions (Repeat, Goto, Set A-B, etc.) DiscScan, TrackScan, and QuickScan Video CD 1.1 and 2.0, and Audio CD compatible Power management 3.6 V power supply with 5 V tolerant I/O’s 100-pin PQFP Can be used with either serial or parallel interfaces ES3883 Video CD Companion Chip Keypad Panel Interface CD-ROM DRAM 256K X 16 ROM Echo ES3880 Video CD MPEG Processor Microphone Audio Audio DAC Speakers Video NTSC/PAL Encoder Television Interrupt DSC I/O Expansion IR Figure 1 ES3880 System Block Diagram ESS Technology, Inc. SAM0191-052901 1 ES3880 PRODUCT BRIEF ES3880 PINOUT ES3880 PINOUT VDD AUX6 AUX7 AUX5 LD0 LD1 LD3 LD2 LD4 LD5 LD6 LD7 LWR# LOE# LCS3# LCS1# LCS0# LA0 LA1 LA2 LA3 LA4 LA6 LA5 LA7 LA8 LA9 LA11 LA10 VSS Figure 2 shows the ES3880 device pinout. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VPP 81 50 VSS LA12 LA13 82 83 49 48 AUX4 LA14 47 AUX2 LA15 84 85 LA16 86 AUX1 AUX0 LA17 ACLK 87 88 AOUT/SEL_PLL0 89 46 45 44 43 42 ATCLK 90 91 41 40 HSYNC 39 38 37 YUV7 YUV6 36 35 34 33 32 YUV4 PCLK PCLK2X CPUCLK VSYNC YUV5 YUV3 YUV2 YUV1 YUV0 VDD VSS DBUS14 DBUS15 RESET# DBUS13 DBUS12 DBUS11 DBUS10 DBUS9 DBUS8 DBUS7 DBUS6 DBUS5 31 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DBUS3 DBUS4 5 6 7 DBUS2 4 DBUS1 2 3 DBUS0 1 DA8 VSS DA7 99 100 DA6 98 CAS# DA5 TDMFS DA4 97 DA2 DA3 TDMDR DA1 TDMCLK 95 96 DA0 ARFS 100-pin PQFP DWE# AIN ARCLK 92 93 94 VDD DA9/DOE# ES3880 RAS# ATFS/SEL_PLL1 AUX3 Figure 2 ES3880 Device Pinout 2 SAM0191-052901 ESS Technology, Inc. ES3880 PRODUCT BRIEF PIN DESCRIPTION PIN DESCRIPTION Table 1 lists the pin descriptions for the ES3880. Table 1 ES3880 Pin Descriptions List Name Number I/O Definition VDD 1, 31, 51 I 3.3V power supply. RAS# 2 O Row address strobe. DWE# 3 O DRAM write enable. DA[8:0] 12:4 O DRAM multiplexed row and column address bus. DBUS[15:0] 28:13 I/O DRAM data bus. 29 I System reset. 30, 50, 80, 100 I Ground. RESET# VSS YUV[7:0] 39:32 O YUV[7:0] 8-bit video data bus. VSYNC 40 I/O Vertical sync. HSYNC 41 I/O Horizontal sync. CPUCLK 42 I PCLK2X 43 I/O Doubled 54 MHz pixel clock. PCLK 44 I/O 27 MHz pixel clock. 54:52, 49:45 I/O Auxiliary control pins 7:0. AUX0 and AUX1 are open collectors. LD[7:0] 62:55 I/O RISC interface data bus. LWR# 63 O RISC interface write enable. LOE# 64 O RISC interface output enable. 65, 66, 67 O RISC interface chip select. AUX[7:0] LCS[3,1,0]# LA[17:0] RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00 to bypass PLL. 87:82, 79:68 O RISC interface address bus. VPP 81 I 5.0V power supply. ACLK 88 I/O Master clock for external audio DAC. O Audio interface serial data output when selected. I System and DSCK output clock frequency selection at reset time. The matrix below lists the available clock frequencies and their respective PLL bit settings. AOUT SEL_PLL0 89 ATCLK 90 ATFS SEL_PLL1 0 0 1 1 SEL_PLL0 0 1 0 1 I/O Audio transmit bit clock. DCLK Bypass PLL (input mode) 54 MHz (output mode) Default 67.5 MHz (output mode) 81.0 MHz (output mode) O Audio transmit frame sync. SEL_PLL1 91 I Refer to the description and matrix for SEL_PLL0 pin 89. DA9 92 O DRAM multiplexed row and column address line 9. O DRAM output enable. DOE# AIN 93 I Audio serial data input. ARCLK 94 I Audio receive bit clock. ARFS 95 I Audio receive frame sync. TDMCLK 96 I TDM serial clock. ESS Technology, Inc. SAM0191-052901 3 ES3880 PRODUCT BRIEF BLOCK DIAGRAM Table 1 ES3880 Pin Descriptions List (Continued) Name Number I/O Definition TDMDR 97 I TDM serial data receive. TDMFS 98 I TDM frame sync. CAS# 99 O DRAM column address strobe. BLOCK DIAGRAM Figure 3 provides a functional block diagram of the ES3880. Processor Interface DRAM Interface LA[17:0] LD[7:0] LCS3#, LCS#[1:0] LWR# LOE# ACLK ATCLK AIN AOUT ARFS ATFS ARCLK Serial Audio Interface RISC Processor Serial Audio Interface Huffman Decoder 2Kx32 ROM SEL_PLL[1:0] TDMCLK TDMDR TDMFS DRAM 512x32 SRAM MPEG Processor 64x32 ROM 32x32 SRAM Video Output Registers TDM Interface RAS# DA[9:0] DBUS[15:0] DOE# DWE# CAS# On Screen Display TDM Interface AUX[7:0] AUX YUV[7:0] PCLK2X PCLK VSYNC HSYNC Screen Display CPUCLK RESET# Misc. DRAM DMA Controller Figure 3 ES3880 Functional Block Diagram ORDERING INFORMATION Part Number Description Package ES3880 Video CD MPEG Processor 100-pin PQFP No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. (P) U.S. Patent 4,384,169 and others, other patents pending. SmartScale™, SmartStream™, and VideoDrive™ are trademarks of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. MPEG is the Moving Picture Experts Group of the ISO/ IEC. References to MPEG2 in this document refer to the ISO/IEC 13818-1. All specifications are subject to change without prior notice. All other trademarks are owned by their respective holders and are used for identification purposes only. ESS Technology, Inc. assumes no responsibility for any errors contained herein. 4 © 2000 ESS Technology, Inc. All rights reserved. SAM0191-052901