MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc. MPC99J93 Freescale Semiconductor, Inc... Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features: • Fully Integrated PLL • • • • • Order Number: MPC99J93/D Rev 1, 08/2003 FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Dynamic Switch Logic Inp0bad Man_Override Qb0 Qb0 Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB OR Qb1 Qb1 ÷2 PLL ÷4 200 -- 360 MHz MR Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Figure 1. Block Diagram This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. E Motorola Inc. 2003 MOTOROLA TIMING SOLUTIONS 1 For More Information On This Product, Go to: www.freescale.com Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 VCC 24 23 22 21 20 19 18 17 Qa1 25 16 VCC Qa1 26 15 Inp0bad Qa0 27 14 Inp1bad Qa0 28 13 Clk_Selected VCC 29 12 GND VCC_PLL 30 11 Ext_FB Man_Override 31 10 Ext_FB PLL_En 32 MPC99J93 2 3 4 5 6 7 8 Alarm_Reset CLK0 CLK0 Sel_Clk CLK1 CLK1 GND 9 1 MR Freescale Semiconductor, Inc... VCC Freescale Semiconductor, Inc. MPC99J93 GND Figure 2. 32--Lead Pinout (Top View) Table 1. Pin Descriptions Pin Name I/O Pin Definition CLK0, CLK0 CLK1, CLK1 LVPECL Input LVPECL Input Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Ext_FB, Ext_FB LVPECL Input Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Qa0:1, Qa0:1 LVPECL Output Differential 1x output pairs. Connect one QAx pair to Ext_FB. Qb0:2, Qb0:2 LVPECL Output Differential 2x output pairs Inp0bad LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Inp1bad LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Clk_Selected LVCMOS Output ‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected Alarm_Reset LVCMOS Input ‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one--shotted” (50kΩ pullup) Sel_Clk LVCMOS Input ‘0’ selects CLK0, ‘1’ selects CLK1 (50kΩ pulldown) Manual_Override LVCMOS Input ‘1’ disables internal clock switch circuitry (50kΩ pulldown) PLL_En LVCMOS Input ‘0’ bypasses selected input reference around the phase--locked loop (50kΩ pullup) MR LVCMOS Input ‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50kΩ pullup) VCCA Power Supply PLL power supply VCC Power Supply Digital power supply GNDA Power Supply PLL ground GND Power Supply Digital ground 2 MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC99J93 Table 2. ABSOLUTE MAXIMUM RATINGSa Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage temperature -65 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. GENERAL SPECIFICATIONS Freescale Semiconductor, Inc... Symbol Characteristics Min Typ Max VCC - 2 Unit VTT Output termination voltage MM ESD Protection (Machine model) 175 V HBM ESD Protection (Human body model) 1500 V CDM ESD Protection (Charged device model 1000 V 100 LU Latch-up immunity CIN Input Capacitance θJA Thermal resistance junction to ambient JESD 51-3, single layer test board V mA 4.0 JESD 51-6, 2S2P multilayer test board θJC Thermal resistance junction to case TJ Operating junction temperaturea (continuous operation) MTBF = 9.1 years Condition pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 110 °C a. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MOTOROLA TIMING SOLUTIONS 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC99J93 Table 4. DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = --40° to +85°C) Symbol Characteristics Min Typ Max Unit Condition VCC + 0.3 V 0.8 V ±100 µA VIN=VCC or GND V IOH=-24 mA 0.55 V IOL= 24 mA 0.1 1.3 V Differential operation VCC-1.8 VCC-0.3 V Differential operation ±100 µA VIN=VCC or GND LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset) VIH Input High Voltage VIL Input Low Voltage IIN Input 2.0 Currenta LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad) VOH Output High Voltage VOL Output Low Voltage LVPECL clock inputs (CLK0, CLK1, Freescale Semiconductor, Inc... VPP 2.0 Ext_FB)b DC Differential Input Voltagec VCMR Differential Cross Point IIN Input Currenta Voltaged LVPECL clock outputs (QA[1:0], QB[2:0]) VOH Output High Voltage VCC-1.20 VCC-0.95 VCC-0.70 V Termination 50Ω to VTT VOL Output Low Voltage VCC-1.90 VCC-1.75 VCC-1.45 V Termination 50Ω to VTT Supply Current a. b. c. d. IGND Maximum Power Supply Current 180 mA GND pins ICC_PLL Maximum PLL Supply Current 15 mA VCC_PLL pin Inputs have internal pull-up/pull-down resistors affecting the input current. Clock inputs driven by differential LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4 MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC99J93 Table 5. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a Symbol Freescale Semiconductor, Inc... fref Characteristics Input Reference Frequency Rangeb fVCO VCO Frequency fMAX Output Frequency frefDC Reference Input Duty Cycle t(∅) Propagation Delay VPP Differential input voltaged Min Typ Max Unit Condition PLL locked ÷4 feedback 50 90 MHz ÷4 feedback 200 360 MHz QA[1:0] QB[2:0] 50 100 90 180 MHz MHz 25 75 % offsetc SPO, static phase CLK0, CLK1 to any Q -0.15 0.9 +0.17 1.8 ns ns (peak-to-peak) 0.25 1.3 V VCC-1.7 VCC-0.3 V 50 80 ps ps 20 10 200 100 50 25 400 200 ps ps ps ps 50 55 % 10 ms 0.70 ns VCMR Differential input crosspoint tsk(O) Output-to-output Skew ∆per/cycle Rate of change of period DC Output Duty Cycle tJIT(CC) Cycle-to-Cycle Jitter tLOCK Maximum PLL Lock Time tr, tf Output Rise/Fall Time voltagee within QA[2:0] or QB[1:0] within device QA[1:0]f QB[2:0]f QA[1:0]g QB[2:0]g 45 RMS (1 σ) 25 0.05 PLL locked PLL_EN=1 PLL_EN=0 ps 20% to 80% a. b. c. d. AC characteristics apply for parallel output termination of 50Ω to VCC - 2V. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO ÷ FB. CLK0, CLK1 to Ext_FB. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Applicable to CLK0, CLK1 and Ext_FB. e. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-topart skew. Applicable to CLK0, CLK1 and Ext_FB. f. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (±180_). Delta period change per cycle is averaged over the clock switch excursion. MOTOROLA TIMING SOLUTIONS 5 For More Information On This Product, Go to: www.freescale.com MPC99J93 Freescale Semiconductor, Inc. APPLICATIONS INFORMATION The MPC99J93 is a dual clock PLL with on--chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Freescale Semiconductor, Inc... Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it’s CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset. Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one--shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it’s INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC99J93’s, the following procedure should be used. Assuming that the input CLKs to all MPC9993’s are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an MPC99J93 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC99J93 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC99J93 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De--assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode. 6 MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC99J93 OUTLINE DIMENSIONS FA SUFFIX PLASTIC LQFP PACKAGE CASE 873A--03 ISSUE B 4X 0.20 H A--B D 6 D1 e/2 D1/2 PIN 1 INDEX 32 3 25 1 E1/2 A F B Freescale Semiconductor, Inc... 6 E1 E 4 F DETAIL G 17 8 9 7 E/2 DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08--mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07--mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm FROM THE LEAD TIP. D D/2 4 D 4X 0.20 C A--B D H SEATING PLANE 28X e C 32X 0.1 C DETAIL AD BASE METAL PLATING b1 c 8X 0.20 R R2 A2 GAUGE PLANE (S) L (L1) DETAIL AD θ_ M 5 C A--B D SECTION F--F 0.25 A1 c1 b ( θ1_) R R1 A A, B, D 8 DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 θ θ1 R1 R2 S MOTOROLA TIMING SOLUTIONS MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 -----0.20 REF 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... MPC99J93 Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. E Motorola Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1--800--521--6274 or 480--768--2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3--20--1, Minami--Azabu, Minato--ku, Tokyo 106--8573, Japan 81--3--3440--3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852--26668334 HOME PAGE: http://motorola.com/semiconductors 8 ◊ For More Information On This Product, Go to: www.freescale.com MOTOROLA TIMING SOLUTIONS MPC99J93/D