50 dB GSM PA Controller AD8315 Its high sensitivity allows control at low signal levels, thus reducing the amount of power that needs to be coupled to the detector. FEATURES Complete RF Detector/Controller Function >50 dB Range at 0.9 GHz (–49 dBm to +2 dBm re 50 ) Accurate Scaling from 0.1 GHz to 2.5 GHz Temperature-Stable Linear-in-dB Response Log Slope of 23 mV/dB, Intercept at –60 dBm at 0.9 GHz True Integration Function in Control Loop Low Power: 20 mW at 2.7 V, 38 mW at 5 V Power Down to 10.8 W For convenience, the signal is internally ac-coupled. This high-pass coupling, with a corner at approximately 0.016 GHz, determines the lowest operating frequency. Thus, the source may be dc grounded. The AD8315 provides a voltage output, VAPC, that has the voltage range and current drive to directly connect to most handset power amplifiers’ gain control pin. VAPC can swing from 250 mV above ground to within 200 mV below the supply voltage. Load currents of up to 6 mA can be supported. APPLICATIONS Single, Dual, and Triple Band Mobile Handset (GSM, DCS, EDGE) Transmitter Power Control The setpoint control input is applied to pin VSET and has an operating range of 0.25 V–1.4 V. The associated circuit determines the slope and intercept of the linear-in-dB measurement system; these are nominally 23 mV/dB and –60 dBm for a 50 W termination (–73 dBV) at 0.9 GHz. Further simplifying the application of the AD8315, the input resistance of the setpoint interface is over 100 MW, and the bias current is typically 0.5 mA. PRODUCT DESCRIPTION The AD8315 is a complete low cost subsystem for the precise control of RF power amplifiers operating in the frequency range 0.1 GHz–2.5 GHz and over a typical dynamic range of 50 dB. It is intended for use in cellular handsets and other battery-operated wireless devices. The log amp technique provides a much wider measurement range and better accuracy than controllers using diode detectors. In particular, its temperature stability is excellent over a specified range of –30∞C to +85∞C. The AD8315 is available in MSOP and lead frame chip scale (LFCSP) packages and consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered down, the sleep current is 4 mA. FUNCTIONAL BLOCK DIAGRAM VPOS LOW NOISE BAND GAP REFERENCE LOW NOISE GAIN BIAS ENBL OUTPUT ENABLE DELAY 1.35 DET DET DET DET DET VAPC HI-Z LOW NOISE (25nV/ Hz) RAIL-TO-RAIL BUFFER RFIN 10dB 10dB 10dB FLTR 10dB V-I OFFSET COMP’N INTERCEPT POSITIONING VSET 23mV/dB 250mV to 1.4V = 50dB COMM REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD8315–SPECIFICATIONS (V = 2.7 V, T = 25C, 52.3 termination on RFIN, unless otherwise noted.) S Parameter OVERALL FUNCTION Frequency Range1 Input Voltage Range Equivalent dBm Range Logarithmic Slope2 Logarithmic Intercept2 Equivalent dBm Level Conditions Min To Meet All Specifications ± 1 dB Log Conformance, 0.1 GHz 0.1 –57 –44 21.5 –79 –66 0.1 GHz 0.1 GHz RF INPUT INTERFACE Input Resistance3 Input Capacitance3 Pin RFIN 0.1 GHz 0.1 GHz OUTPUT Minimum Output Voltage Pin VAPC VSET £ 200 mV, ENBL High ENBL Low RL ≥ 800 W 85∞C, VPOS = 3 V, IOUT = 6 mA 2.7 V £ VPOS £ 5.5 V, RL = • Source/Sink Maximum Output Voltage vs. Temperature4 General Limit Output Current Drive Output Buffer Noise Output Noise Small Signal Bandwidth Slew Rate Response Time ENABLE INTERFACE Logic Level to Enable Power Input Current when Enable High Logic Level to Disable Power Enable Time Pin ENBL POWER INTERFACE Supply Voltage Quiescent Current Over Temperature Disable Current6 Over Temperature 0.25 Unit 24 –70 –57 2.5 –11 +2 25.5 –64 –51 GHz dBV dBm mV/dB dBV dBm 0.27 0.02 kW pF VPOS – 0.1 5/200 25 130 V V V V V mA/mA nV÷Hz nV/÷Hz 30 13 150 MHz V/ms ns 2.45 2.54 RF Input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF 0.2 V to 2.6 V Swing 10%–90%, 1.2 V Step (VSET), Open Loop5 FLTR = Open, Refer to TPC 24 Pin VSET Corresponding to Central 50 dB Power-On/Enable Time Max 2.8 0.9 SETPOINT INTERFACE Nominal Input Range Logarithmic Scale Factor Input Resistance Slew Rate Disable Time Typ 0.3 2.6 0.25 1.4 V dB/V kW V/ms VPOS 43.5 100 16 1.8 4 0.8 5 V mA V ms 8 9 ms 2 3 ms 100 200 ns 5.5 10.7 12.9 10 13 V mA mA mA mA 20 Time from ENBL High to VAPC within 1% of Final Value, VSET £ 200 mV, Refer to TPC 21 Time from ENBL Low to VAPC within 1% of Final Value, VSET £ 200 mV, Refer to TPC 21 Time from VPOS/ENBL High to VAPC within 1% of Final Value, VSET £ 200 mV, Refer to TPC 26 Time from VPOS/ENBL Low to VAPC within 1% of Final Value, VSET £ 200 mV, Refer to TPC 26 Pin VPOS 2.7 ENBL High –30∞C £ TA £ +85∞C ENBL Low –30∞C £ TA £ +85∞C 8.5 4 NOTES 1 Operation down to 0.02 GHz is possible. 2 Mean and Standard Deviation specifications are available in Table I. 3 See TPC 9 for plot of Input Impedance vs. Frequency. 4 This parameter is guaranteed but not tested in production. Limit is –3 sigma from the mean. 5 Response time in a closed-loop system will depend upon the filter capacitor (C FLT) used and the response of the variable gain element. 6 This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the +6 sigma value. Specifications subject to change without notice. –2– REV. B AD8315 Table I. Typical Specifications at Selected Frequencies at 25C (Mean and Sigma) Frequency – GHz Slope – mV/dB Mean Sigma Intercept – dBV Mean Sigma 1 dB Dynamic Range Low Point – dBV High Point – dBV Mean Sigma Mean Sigma 0.1 0.9 1.9 2.5 23.8 23.2 22.2 22.3 –70.1 –72.6 –73.8 –75.6 –57.7 –61.0 –62.9 –64.0 0.3 0.4 0.3 0.4 1.8 1.8 1.6 1.5 ABSOLUTE MAXIMUM RATINGS* 1.3 1.3 0.9 1.1 –10.6 –11.2 –18.5 –20.0 0.8 0.8 1.7 1.7 PIN CONFIGURATION Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V Temporary Overvoltage VPOS (100 cycles, 2 seconds duration, ENBL Low) . . . . . . . 6.3 V VAPC, VSET, ENBL . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 dBm Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.6 V rms Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 60 mW qJA (MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200∞C/W qJA (LFCSP, Paddle Soldered) . . . . . . . . . . . . . . . . . . 80∞C/W qJA (LFCSP, Paddle not Soldered) . . . . . . . . . . . . . 200∞C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature Range (Soldering 60 sec) MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8 RFIN 1 ENBL 2 VSET 3 AD8315 VPOS VAPC TOP VIEW 6 NC (Not to Scale) FLTR 4 7 COMM 5 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 RFIN ENBL 3 VSET 4 FLTR 5 6 7 COMM NC VAPC 8 VPOS RF Input Connect to VPOS for Normal Operation Connect pin to ground for Disable Mode Setpoint Input. Nominal input range 0.25 V to 1.4 V. Integrator Capacitor. Connect between FLTR and COMM. Device Common (Ground) No Connection Output. Control voltage for gain control element. Positive Supply Voltage: 2.7 V to 5.5 V ORDERING GUIDE Model Temperature Range Package Descriptions Package Option Branding Information AD8315ARM AD8315ARM-REEL AD8315ARM-REEL7 AD8315-EVAL AD8315ACP-REEL –30∞C to +85∞C Tube, 8-Lead MSOP 13" Tape and Reel 7" Tape and Reel MSOP Evaluation Board 13" Tape and Reel, 8-Lead LFCSP 7" Tape and Reel LFCSP Evaluation Board RM-8 J7A CP-8 J7A AD8315ACP-REEL7 AD8315ACP-EVAL –30∞C to +85∞C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8315 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– WARNING! ESD SENSITIVE DEVICE 23 0 13 3 –10 –20 –7 0.1GHz –30 –17 –40 –27 0.9GHz 2.5GHz –37 –50 –47 –60 4 3 2.5GHz 2 ERROR – dB 1 RF INPUT AMPLITUDE – dBm RF INPUT AMPLITUDE – dBV AD8315 –Typical Performance Characteristics 1.9GHz 0.1GHz 0.9GHz 1 0 –1 –2 1.9GHz –70 –80 0.2 0.4 0.6 0.8 1.0 VSET – V 1.2 –57 –3 –67 –4 0.2 1.4 0.4 TPC 1. Input Amplitude vs. VSET 0.8 1.0 VSET – V 1.2 1.4 1.6 TPC 4. Log Conformance vs. VSET 10 –30C 0 0.6 4 10 4 3 0 3 2 (+3dBm) –10 +25C 1 –20 +85C 0 –30 +25C –40 –1 –50 –2 RF INPUT AMPLITUDE – dBV –30C 2 +85C –30C –20 1 –30 0 +25C –40 –1 ERROR – dB +85C ERROR – dB RF INPUT AMPLITUDE – dBV (+3dBm) –10 –2 –50 +25C –70 0.1 ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.3 0.5 0.7 0.9 VSET – V 1.1 1.3 (–47dBm) –60 –3 +85C 0 –30C +25C 0 3 2 (+3dBm) –10 –30 0 –1 –2 ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C (–47dBm) –60 –70 0.1 0.3 0.5 0.7 0.9 VSET – V 1.1 1.3 –4 1.5 3 1 –50 1.3 4 –30C +25C 1.1 10 –20 –40 0.7 0.9 VSET – V –3 4 RF INPUT AMPLITUDE – dBV +85C ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C TPC 5. Input Amplitude and Log Conformance vs. VSET at 1.9 GHz ERROR – dB RF INPUT AMPLITUDE – dBV (+3dBm) –10 –30C 0.3 0.5 –70 0.1 –4 1.5 TPC 2. Input Amplitude and Log Conformance vs. VSET at 0.1 GHz 10 +85C 2 –30C +85C 1 –20 0 –30 +25C –40 –1 –2 –50 –3 +25C (–47dBm) –60 +85C –4 1.5 –70 0.1 TPC 3. Input Amplitude and Log Conformance vs. VSET at 0.9 GHz ERROR – dB (–47dBm) –60 –30C 0.3 0.5 ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.7 0.9 VSET – V 1.1 1.3 –3 –4 1.5 TPC 6. Input Amplitude and Log Conformance vs. VSET at 2.5 GHz –4– REV. B AD8315 4 –30C 3 3 2 2 1 1 ERROR – dB ERROR – dB 4 0 –1 +85C –2 –4 –80 –70 –60 –50 –40 –30 –20 RF INPUT AMPLITUDE – dBV (–47dBm) –10 –4 –80 0 +85C ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C –70 (+3dBm) –50 –40 –30 –20 –60 RF INPUT AMPLITUDE – dBV (–47dBm) –10 0 (+3dBm) TPC 10. Distribution of Error at Temperature after Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz 4 4 3 3 30C 2 1 1 ERROR – dB 2 0 –1 85C –2 ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C –3 –4 –80 –70 –10 (+3dBm) 2700 –200 2400 –400 FREQUENCY MSOP Chip Scale (LFCSP) R – jX (GHz) R – jX –600 2900 – j1900 2700 – j1500 0.1 700 – j240 0.9 730 – j220 –800 130 – j80 1.9 460 – j130 170 – j70 2.5 440 – j110 –1000 1200 R 900 X R (LFCSP) 600 –50 –40 –30 –20 –60 RF INPUT AMPLITUDE – dBV –1200 –10 0 (+3dBm) 10 8 –1400 X (MSOP) –70 +85C TPC 11. Distribution of Error at Temperature after Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz REACTANCE – 0 X (LFCSP) ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C (–47dBm) 3000 1500 –1 –4 –80 0 TPC 8. Distribution of Error at Temperature after Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz 1800 0 –3 –60 –50 –40 –30 –20 RF INPUT AMPLITUDE – dBV (–47dBm) 2100 –30C –2 SUPPLY CURRENT – mA ERROR – dB –1 –3 TPC 7. Distribution of Error at Temperature after Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz RESISTANCE – 0 –2 ERROR AT +85C AND –30C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C –3 –30C 6 4 DECREASING VENBL INCREASING VENBL 2 –1600 –1800 300 R (MSOP) 0 0 0.5 1 1.5 FREQUENCY – GHz 2 0 1.3 –2000 2.5 TPC 9. Input Impedance REV. B 1.4 1.5 VENBL – V 1.6 TPC 12. Supply Current vs. VENBL –5– 1.7 AD8315 25 –66 –68 24 +85C INTERCEPT – dBV SLOPE – mV/dB –70 +85 C 23 –30 C 22 +25 C –72 +25C –74 –30C –76 21 –78 20 –80 0 0.5 1.0 1.5 FREQUENCY – GHz 2.0 2.5 0 TPC 13. Slope vs. Frequency; –30 ∞C, +25 ∞C, and +85 ∞C 24 0.5 1.0 1.5 FREQUENCY – GHz 2.0 2.5 TPC 16. Intercept vs. Frequency; –30 ∞C, +25 ∞C, and +85 ∞C –68 0.1GHz 0.1GHz –70 INTERCEPT – dBV SLOPE – mV/dB 0.9GHz 23 1.9GHz 22 –72 0.9GHz –74 1.9GHz –76 2.5GHz 2.5GHz –78 21 2.5 3.0 3.5 4.0 VS – V 4.5 5.0 –80 2.5 5.5 CFLT = 0pF CFLT = 220pF 100 1k 10k 100k FREQUENCY – Hz 1M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 10000 NOISE SPECTRAL DENSITY – nV/ Hz 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 10 3.5 4.0 VS – V 4.5 5.0 5.5 TPC 17. Intercept vs. Supply Voltage PHASE – Degrees AMPLITUDE – dB TPC 14. Slope vs. Supply Voltage 3.0 CFLT = 220PF, RF INPUT = 2GHz RF INPUT –51dBV –48dBV –33dBV –43dBV 1000 –23dBV –13dBV 100 –53dBV AND –63dBV 10 100 10M TPC 15. AC Response from VSET to VAPC 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 18. VAPC Noise Spectral Density –6– REV. B AD8315 3.5 2.8 3.3 2mA VAPC – V VAPC – V 2.7 0mA 3.1 2.9 4mA 2.6 6mA 2.7 2.5 2.5 SHADING INDICATES 3 SIGMA 2.3 2.7 2.8 2.9 3.0 3.1 3.2 SUPPLY VOLTAGE – V 3.3 3.4 2.4 2.7 3.5 TPC 19. Maximum VAPC Voltage vs. Supply Voltage by Load Current 2.8 2.9 SUPPLY VOLTAGE – V TPC 22. Maximum VAPC Voltage vs. Supply Voltage with 4 mA Load Current AVERAGE = 16 SAMPLES AVERAGE = 16 SAMPLES VAPC 1V PER VERTICAL DIVISION 200mV PER VERTICAL DIVISION VAPC GND GND 1V PER VERTICAL DIVISION 2 s PER HORIZONTAL DIVISION PULSED RF 0.1GHz, –13dBV RF INPUT GND 100ns PER HORIZONTAL DIVISION VENBL GND TPC 20. ENBL Response Time R AND S SMT03 SIGNAL GENERATOR 10MHz REF OUTPUT TPC 23. VAPC Response Time, Full-Scale Amplitude Change, Open-Loop R AND S SMT03 10MHz REF OUTPUT SIGNAL GENERATOR PULSE PULSE MODE IN MODULATION MODE TRIG TIMEBASE STANFORD DS345 OUT PULSE GENERATOR PULSE OUT RF OUT 0.1F AD8315 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 6 4 FLTR COMM 5 RF SPLITTER –3dB –3dB TRIG OUT 2.7V TEK P6205 FET PROBE 0.1 F AD8315 TEK TDS694C SCOPE 52.3 220pF NC = NO CONNECT 1 RFIN VPOS 8 2.7V 2 ENBL VAPC 7 0.3V 3 VSET NC 6 NC 4 FLTR COMM 5 TRIG TEK P6205 FET PROBE TEK TDS694C SCOPE NC = NO CONNECT TPC 21. Test Setup for ENBL Response Time REV. B OUT PICOSECOND PULSE LABS PULSE GENERATOR PULSE OUT TRIG TEK P6205 FET PROBE EXT TRIG RF OUT 2.7V 52.3 3.0 TPC 24. Test Setup for VAPC Response Time –7– AD8315 AVERAGE = 16 SAMPLES 500mV PER VERTICAL DIVISION VAPC GND 200mV PER VERTICAL DIVISION VAPC GND VS AND VENBL 2 s PER HORIZONTAL DIVISION 1V PER VERTICAL DIVISION 2s PER HORIZONTAL DIVISION 1V PER VERTICAL DIVISION VS GND GND AVERAGE = 16 SAMPLES TPC 25. Power-On and -Off Response with VSET Grounded 10MHz REF R AND S OUTPUT SMT03 SIGNAL GENERATOR EXT TRIG TPC 27. Power-On and -Off Response with VSET and ENBL Grounded 10MHz REF R AND S OUTPUT SMT03 SIGNAL GENERATOR TRIG STANFORD DS345 OUT PULSE GENERATOR PULSE OUT RF OUT TRIG EXT TRIG STANFORD DS345 OUT PULSE GENERATOR PULSE OUT RF OUT AD811 AD811 49.9 49.9 732 AD8315 52.3 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 6 4 FLTR COMM 5 732 AD8315 TEK P6205 FET PROBE TRIG 52.3 TEK P6205 FET PROBE 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 6 4 FLTR COMM 5 TEK TDS694C SCOPE 220pF TEK P6205 FET PROBE TEK P6205 FET PROBE TRIG TEK TDS694C SCOPE 220pF NC = NO CONNECT NC = NO CONNECT TPC 26. Test Setup for Power-On and -Off Response with VSET Grounded TPC 28. Test Setup for Power-On and -Off Response with VSET and ENBL Grounded GENERAL DESCRIPTION AND THEORY of 24 mV/dB was chosen, and the intercept VZ was placed at the equivalent of –70 dBV for a sine wave input (316 mV rms). This corresponds to a power level of –57 dBm when the net resistive part of the input impedance of the log amp is 50 W. However, both the slope and the intercept are dependent on frequency (see TPC 13 and TPC 16). The AD8315 is a wideband logarithmic amplifier (log amp) similar in design to the AD8313 and AD8314. However, it is strictly optimized for use in power control applications rather than as a measurement device. Figure 1 shows the main features in block schematic form. The output (Pin 7, VAPC) is intended to be applied directly to the automatic power-control (APC) pin of a power amplifier module. Keeping in mind that log amps do not respond to power but only to voltages and that the calibration of the intercept is waveform dependent and is only quoted for a sine wave signal, the equivalent power response can be written as: Basic Theory Logarithmic amplifiers provide a type of compression in which a signal having a large range of amplitudes is converted to one of smaller range. The use of the logarithmic function uniquely results in the output representing the decibel value of the input. The fundamental mathematical form is: VOUT = VSLP log10 VIN VZ VOUT = VDB (PIN – PZ ) (2) where the input power PIN and the equivalent intercept PZ are both expressed in dBm (thus, the quantity in parentheses is simply a number of decibels), and VDB is the slope expressed as so many mV/dB. For a log amp having a slope VDB of 24 mV/dB and an intercept at –57 dBm, the output voltage for an input power of –30 dBm is 0.024 [–30 – (–57)] = 0.648 V. (1) Here VIN is the input voltage, VZ is called the intercept (voltage) because when VIN = VZ the argument of the logarithm is unity and thus the result is zero, and VSLP is called the slope (voltage), which is the amount by which the output changes for a certain change in the ratio (VIN/VZ). When BASE-10 logarithms are used, denoted by the function log10, VSLP represents the “volts/decade,” and since a decade corresponds to 20 dB, VSLP/20 represents the “volts/dB.” For the AD8315, a nominal (low frequency) slope Further details about the structure and function of log amps can be found in data sheets for other log amps produced by Analog Devices. Refer to data sheets for the AD640 and AD8307, both of which include a detailed discussion of the basic principles of operation and explain why the intercept depends on waveform, an important consideration when complex modulation is imposed on an RF carrier. –8– REV. B AD8315 (PRECISE GAIN CONTROL) (PRECISE SLOPE CONTROL) (ELIMINATES GLITCH) LOW NOISE GAIN BIAS LOW NOISE BAND GAP REFERENCE OUTPUT ENABLE DELAY VPOS ENBL (CURRENT-MODE SIGNAL) 1.35 DET DET DET DET DET VAPC HI-Z LOW NOISE (25nV/ Hz) RAIL-TO-RAIL BUFFER RFIN 10dB 10dB 10dB FLTR 10dB (CURRENTNULLING MODE) OFFSET COMP’N COMM (PADDLE) INTERCEPT POSITIONING (WEAK GM STAGE) (CURRENT-MODE FEEDBACK) V-I (SMALL INTERNAL FILTER CAPACITOR FOR GHz RIPPLE) VSET 23mV/dB 250mV to 1.4V = 50dB Figure 1. Block Schematic The intercept need not correspond to a physically realizable part of the signal range for the log amp. Thus, the specified intercept is –70 dBV, at 0.1 GHz, whereas the smallest input for accurate measurement (a +1 dB error, see Table I) at this frequency is higher, being about –58 dBV. At 2.5 GHz, the +1 dB error point shifts to –64 dBV. This positioning of the intercept is deliberate and ensures that the VSET voltage is within the capabilities of certain DACs, whose outputs cannot swing below 200 mV. Figure 2 shows the 100 MHz response of the AD8315; the vertical axis represents not the output (at pin VAPC) but the value required at the power control pin VSET to null the control loop. This will be explained next. 1.5 24 m V/ dB 1.416V @ –11dBV SL O PE VSET = 1.0 ACTUAL 0.5 0.288V @ –58dBV –70dBV IDEAL 0 100V 1mV –80dBV –60dBV –67dBm –47dBm 10mV –40dBV –27dBm 100mV 1V (RMS) –20dBV 0dBV –7dBm +13dBm (RE 50) VIN, dBVIN, PIN Figure 2. Basic Calibration of the AD8315 at 0.1 GHz Controller-Mode Log Amps The AD8315 combines the two key functions required for the measurement and control of the power level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals in a chain of four amplifier/limiter cells (see Figure 1), each having a small signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square- REV. B law detector cell that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added before the first stage. These five detectors are separated by 10 dB, spanning some 50 dB of dynamic range. Their outputs are each in the form of a differential current, making summation a simple matter. It is readily shown that the summed output can closely approximate a logarithmic function. The overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the log conformance error, can be judged by reference to TPC 4, which shows that errors across the central 40 dB are moderate. Other performance curves show how conformance to an ideal logarithmic function varies with supply voltage, temperature, and frequency. In a device intended for measurement applications, this current would then be converted to an equivalent voltage, to provide the log(VIN) function shown in Equation 1. However, the design of the AD8315 differs from standard practice in that its output needs to be a low noise control voltage for an RF power amplifier, not a direct measure of the input level. Further, it is highly desirable that this voltage be proportional to the time-integral of the error between the actual input VIN and a dc voltage VSET (applied to Pin 3, VSET) which defines the setpoint, that is, a target value for the power level, typically generated by a D/A converter. This is achieved by converting the difference between the sum of the detector outputs (still in current form) and an internally generated current proportional to VSET to a single-sided current-mode signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the low-pass filter capacitor node), to provide a close approximation to an exact integration of the error between the power present in the termination at the input of the AD8315 and the setpoint voltage. Finally, the voltage developed across the ground-referenced filter capacitor CFLT is buffered by a special low noise amplifier of low voltage gain (¥1.35) and presented at Pin 7 (VAPC) for use as the control voltage for the RF power amplifier. This buffer can provide “rail-to-rail” swings and can drive a substantial load current, including large capacitors. Note: The RF power is assumed to increase monotonically with an increasingly positive delivered by the amplifier under control of the AD8315 voltage on its APC control pin. –9– AD8315 where VSLP is the volts-per-decade slope from Equation 1, having a value of 480 mV/decade, and T is an effective time constant for the integration, being equal to 4.15 kW ¥ CFLT/1.35; the resistor value comes from the setpoint interface scaling Equation 4 and the factor 1.35 arises because of the voltage gain of the buffer. So the integration time constant can be written as: Control Loop Dynamics In order to understand how the AD8315 behaves in a complete control loop, an expression for the current in the integration capacitor as a function of the input VIN and the setpoint voltage VSET must be developed. Refer to Figure 3. VSET 3 VSET RFIN 1 VIN SETPOINT INTERFACE LOGARITHMIC RF DETECTION SUBSYSTEM ISET = VSET/4.15k T = 3.07 CFLT in ms , when C is expressed in nF FLTR IDET To simplify our understanding of the control loop dynamics, begin by assuming that the power amplifier gain function actually is linear-in-dB. Also use voltages to express the signals at the power amplifier input and output, for the moment. Let the RF output voltage be VPA and its input be VCW. Further, to characterize the gain control function, this form is used: VAPC 1.35 4 7 IERR CFLT IDET = ISLPLOG10 (VIN/VZ) Figure 3. Behavioral Model of the AD8315 VPA = GOVCW 10(V APC /VGBC ) First, the summed detector currents are written as a function of the input: IDET = ISLP log10 (VIN /VZ ) (3) where IDET is the partially filtered demodulated signal, whose exact average value will be extracted through the subsequent integration step; ISLP is the current-mode slope and has a value of 115 mA per decade (that is, 5.75 mA/dB); VIN is the input in volts-rms; and VZ is the effective intercept voltage, which, as previously noted, is dependent on waveform but is 316 mV rms (–70 dBV) for a sine wave input. Now the current generated by the setpoint interface is simply: I SET = VSET / 4.15 kW = VSET / 4.15 kW – ISLP log10 (VIN /VZ ) sCFLT where GO is the gain of the power amplifier when VAPC = 0 and VGBC is the gain-scaling. While few amplifiers will conform so conveniently to this law, it provides a clearer starting point for understanding the more complex situation that arises when the gain control law is less ideal. VAPC ( s ) = (4) (5) (6) The control output VAPC is slightly greater than this, since the gain of the output buffer is ¥1.35. Also, an offset voltage is deliberately introduced in this stage; this is inconsequential since the integration function implicitly allows for an arbitrary constant to be added to the form of Equation 6. The polarity is such that VAPC will rise to its maximum value for any value of VSET greater than the equivalent value of VIN. In practice, the VAPC output will rail to the positive supply under this condition unless the control loop through the power amplifier is present. In other words, the AD8315 seeks to drive the RF power to its maximum value whenever it falls below the setpoint. The use of exact integration results in a final error that is theoretically zero, and the logarithmic detection law would ideally result in a constant response time following a step change of either the setpoint or the power level, if the power-amplifier control function were likewise linear-in-dB. This latter condition is rarely true, however, and it follows that in practice, the loop response time will depend on the power level, and this effect can strongly influence the design of the control loop. (VSET VGBC )/VSLP – VGBC log10 (kGO VCW /VZ ) (10) 1 + sTO where k is the coupling factor from the output of the power amplifier to the input of the AD8315 (e.g., ¥ 0.1 for a “20 dB coupler”), and TO is a modified time constant (VGBC /VSLP)T. This is quite easy to interpret. First, it shows that a system of this sort will exhibit a simple single-pole response, for any power level, with the customary exponential time domain form for either increasing or decreasing step polarities in the demand level VSET or the carrier input VCW. Second, it reveals that the final value of the control voltage VAPC will be determined by several fixed factors: VAPC (t = •) = (VSET VGBC ) / VSLP – log10 (kGO VCW / VZ ) (11) Example Assume that the gain magnitude of the power amplifier runs from a minimum value of ¥0.316 (–10 dB) at VAPC = 0 to ¥100 (40 dB) at VAPC = 2.5 V. Applying Equation 9, GO = 0.316 and VGBC = 1 V. Using a coupling factor of k = 0.0316 (that is, a 30 dB directional coupler) and recalling that the nominal value of VSLP is 480 mV and VZ = 316 V for the AD8315, first calculate the range of values needed for VSET to control an output range of 33 dBm to –17 dBm. This can be found by noting that, in the steady state, the numerator of Equation 7 must be zero, that is: VSET = VSLP log10 (kVPA /VZ ) (12) when VIN is expanded to kVPA, the fractional voltage sample of the power amplifier output. Now, for +33 dBm, VPA = 10 V rms, this evaluates to: Equation 6 can be restated as: V - VSLP log10 (VIN /VZ ) VAPC (s ) = SET sT (9) This idealized control loop is shown in Figure 4. With some manipulation, it is found that the characteristic equation of this system is: The difference between this current and IDET is applied to the loop filter capacitor CFLT. It follows that the voltage appearing on this capacitor, VFLT, is the time integral of the difference current: VFLT (s ) = ( ISET – IDET )/ sCFLT (8) VSET (max ) = 0.48 log10 ( 316 mV / 316 mV ) = 1.44 V (7) (13) For a delivered power of –17 dBm, VPA = 31.6 mV rms: VSET (min) = 0.48 log10 (1 mV / 316 mV ) = 0.24 V –10– (14) REV. B AD8315 Check: The power range is 50 dB, which should correspond to a voltage change in VSET of 50 dB ¥ 24 mV/dB = 1.2 V, which agrees. Now, the value of VAPC is of interest, although it is a dependent parameter, inside the loop. It depends on the characteristics of the power amplifier, and the value of the carrier amplitude VCW. Using the control values derived above, that is, GO = 0.316 and VGBC = 1 V, and assuming the applied power is fixed at –7 dBm (so VCW = 100 mV rms), the following is true using Equation 11: of the curve shown in Figure 5) will be slower. Note also that it is sometimes useful to add a zero in the closed-loop response by placing a resistor in series with CFLT. For more about these matters, refer to the Applications section. V2, P2 33 23 PRF – dBm VAPC (max ) = (VSETVGBC )/VSLP – log10 kGOV CW /VZ = (1.44 ¥ 1)/ 0.48 – log10 (0.0316 ¥ 0.316 ¥ 0.1 / 316 mV ) (15) = 3.0 – 0.5 = 2.5V VAPC (min) = (VSETVGBC )/VSLP – log10 kGOV CW /VZ = (0.24 ¥ 1)/ 0.48 – log10 (0.0316 ¥ 0.316 ¥ 0.1 / 316 mV ) (16) = 0.5 – 0.5 = zero 13 3 both of which results are consistent with the assumptions made about the amplifier control function. Note that the second term is independent of the delivered power and a fixed function of the drive power. –7 0 0.5 V1, P1 1.0 1.5 2.0 2.5 VAPC – V Figure 5. Typical Power-Control Curve A Note About Power Equivalency DIRECTIONAL COUPLER VRF VCW RF PA RF DRIVE: UP TO 2.5GHz VIN = kVRF VSET VAPC AD8315 RESPONSE-SHAPING OF OVERALL CONTROLLOOP (EXTERNAL CAP) CFLT Figure 4. Idealized Control Loop for Analysis Finally, using the loop time constant for these parameters and an illustrative value of 2 nF for the filter capacitor CFLT: TO = (VGBC /VSLP ) T = (1/ 0.48) 3.07 ms ¥ 2 ( nF ) = 12.8 ms (17) Practical Loop At the present time, power amplifiers, or VGAs preceding such amplifiers, do not provide an exponential gain characteristic. It follows that the loop dynamics (the effective time constant) will vary with the setpoint, since the exponential function is unique in providing constant dynamics. The procedure must, therefore, be as follows. Beginning with the curve usually provided for the power output versus the APC voltage, draw a tangent at the point on this curve where the slope is highest (see Figure 5). Using this line, calculate the effective minimum value of the variable VGBC and use it in Equation 17 to determine the time constant. Note that the minimum in VGBC corresponds to the maximum rate of change in the output power versus VAPC. For example, suppose it is found that, for a given drive power, the amplifier generates an output power of P1 at VAPC = V1 and P2 at VAPC = V2. Then, it is readily shown that: VGBC = 20 (V2 – V1 )/( P2 – P 1) (18) In using the AD8315, it must be understood that log amps do not fundamentally respond to power. It is for this reason that dBV (decibels above 1 V rms) are used rather than the commonly used metric of dBm. The dBV scaling is fixed, independent of termination impedance, while the corresponding power level is not. For example, 224 mV rms is always –13 dBV (with one further condition of an assumed sinusoidal waveform; see the AD640 data sheet for more information about the effect of waveform on logarithmic intercept), and this corresponds to a power of 0 dBm when the net impedance at the input is 50 W. When this impedance is altered to 200 W, however, the same voltage corresponds to a power level that is four times smaller (P = V2/R) or –6 dBm. A dBV level may be converted to dBm in the special case of a 50 W system and a sinusoidal signal by simply adding 13 dB (0 dBV is then, and only then, equivalent to 13 dBm). Therefore, the external termination added ahead of the AD8315 determines the effective power scaling. This will often take the form of a simple resistor (52.3 W will provide a net 50 W input), but more elaborate matching networks may be used. The choice of impedance determines the logarithmic intercept, that is, the input power for which the VSET versus PIN function would cross the baseline if that relationship were continuous for all values of VIN. This is never the case for a practical log amp; the intercept (so many dBV) refers to the value obtained by the minimum error straight line fit to the actual graph of VSET versus PIN (more generally, VIN). Where the modulation is complex, as in CDMA, the calibration of the power response needs to be adjusted; the intercept will remain stable for any given arbitrary waveform. When a true power (waveform independent) response is needed, a mean-responding detector, such as the AD8361, should be considered. The logarithmic slope, VSLP in Equation 1, which is the amount by which the setpoint voltage needs to be changed for each decibel of input change (voltage or power), is, in principle, independent of waveform or termination impedance. In practice, it usually falls off somewhat at higher frequencies, due to the declining gain of the amplifier stages and other effects in the detector cells (see TPC 13). This should be used to calculate the filter capacitance. The response time at high and low power levels (on the “shoulders” REV. B –11– AD8315 Basic Connections Figure 6 shows the basic connections for operating the AD8315, and Figure 7 shows a block diagram of a typical application. The AD8315 is typically used in the RF power control loop of a mobile handset. A supply voltage of 2.7 V to 5.5 V is required for the AD8315. The supply to the VPOS pin should be decoupled with a low inductance 0.1 mF surface-mount ceramic capacitor, close to the device. The AD8315 has an internal input coupling capacitor. This negates the need for external ac-coupling. This capacitor, along with the low frequency input impedance of the device of approximately 2.8 kW, sets the minimum usable input frequency to around 0.016 GHz. A broadband 50 W input match is achieved in this example by connecting a 52.3 W resistor between RFIN and ground. A plot of input impedance versus frequency is shown in TPC 9. Other coupling methods are also possible (see Input Coupling Options section). R1 52.3 AD8315 VPOS 8 +VS 2 ENBL VAPC 7 VSET 3 VSET NC 6 4 FLTR COMM 5 +VS (2.7V TO 5.5V) +VAPC Figure 6. Basic Connections RFIN GAIN CONTROL VOLTAGE ATTENUATOR VAPC AD8315 VSET RFIN For setpoint voltages of less than approximately 250 mV, VAPC will remain unconditionally at its minimum level of approximately 250 mV. This feature can be used to prevent any spurious emissions during power-up and power-down phases. The time domain response of power amplifier control loops, using any kind of controller, is only partially determined by the choice of filter which, in the case of the AD8315, has a true integrator form 1/sT as shown in Equation 7, with a time constant given by Equation 8. The large signal step response is also strongly dependent on the form of the gain-control law. Nevertheless, some simple rules can be applied. When the filter capacitor CFLT is very large, it will dominate the time domain response, but the incremental bandwidth of this loop will still vary as VAPC traverses the nonlinear gain-control function of the PA, as sketched in Figure 5. This bandwidth will be highest at the point where the slope of the tangent drawn on this curve is greatest—that is, for power outputs near the center of the PA’s range—and will be much reduced at both the minimum and the maximum power levels, where the slope of the gain control curve is lowest, due to its S-shaped form. NC = NO CONNECT POWER AMP The relationship between the RF input level and the setpoint voltage follows from the nominal transfer function of the device (see TPCs 2, 3, 5, and 6). At 0.9 GHz, for example, a voltage of 1 V on VSET indicates a demand for –30 dBV (–17 dBm re 50 W) at RFIN. The corresponding power level at the output of the power amplifier will be greater than this amount due to the attenuation through the directional coupler. Transient Response CFLT DIRECTIONAL COUPLER Range on VSET and RFIN Above 250 mV, VSET will have a linear control range up to 1.4 V, corresponding to a dynamic range of 50 dB. This results in a slope of 23 mV/dB or approximately 43.5 dB/V. C1 0.1F 1 RFIN RFIN VAPC can swing from 250 mV to within 100 mV of the supply rail and can source up to 6 mA. If the control input of the PA needs to source current, a suitable load resistor can be connected between VAPC and COMM. The output swing and current sourcing capability of VAPC is shown in TPC 19. DAC 52.3 FLTR CFLT Figure 7. Typical Application In a power control loop, the AD8315 provides both the detector and controller functions. A sample of the power amplifier’s (PA) output power is coupled to the RF input of the AD8315, usually via a directional coupler. In dual mode applications, where there are two PAs and two directional couplers, the outputs of the directional couplers can be passively combined (both PAs will never be turned on simultaneously) before being applied to the AD8315. A setpoint voltage is applied to VSET from the controlling source (generally this will be a DAC). Any imbalance between the RF input level and the level corresponding to the setpoint voltage will be corrected by the AD8315’s VAPC output that drives the gain control terminal of the PA. This restores a balance between the actual power level sensed at the input of the AD8315 and the value determined by the setpoint. This assumes that the gain control sense of the variable gain element is positive, that is, an increasing voltage from VAPC will tend to increase gain. Using smaller values of CFLT, the loop bandwidth will generally increase, in inverse proportion to its value. Eventually, however, a secondary effect will appear, due to the inherent phase lag in the power amplifier’s control path, some of which may be due to parasitic or deliberately added capacitance at the VAPC pin. This results in the characteristic poles in the ac loop equation moving off the real axis and thus becoming complex (and somewhat resonant). This is a classic aspect of control loop design. The lowest permissible value of CFLT needs to be determined experimentally for a particular amplifier. For GSM and DCS power amplifiers, CFLT will typically range from 150 pF to 300 pF. In many cases, some improvement in the worst-case response time can be achieved by including a small resistance in series with CFLT; this generates an additional zero in the closed-loop transfer function, that will serve to cancel some of the higher order poles in the overall loop. A combination of main capacitor CFLT shunted by a second capacitor and resistor in series will also be useful in minimizing the settling time of the loop. Mobile Handset Power Control Example Figure 8 shows a complete power amplifier control circuit for a dual mode handset. The PF08107B (Hitachi), a dual mode (GSM, DCS) PA, is driven by a nominal power level of 3 dBm. –12– REV. B AD8315 3.5V 4.7F 4.7F 1000pF 1000pF BAND SELECT 0V/2V TO ANTENNA POUT GSM 35dBm MAX LDC15D190A0007A 7 1 8 4 49.9 5 3 2 VCTL PF08107B 500 ATTN 20dB (OPTIONAL, SEE TEXT) 0.1F R1 52.3 8-BIT RAMP DAC 0V–2.55V R2* 600 PIN DCS 3dBm VAPC POUT DCS 32dBm MAX 6 PIN GSM 3dBm ENABLE 0V/2.7V R3* 1k AD8315 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 6 4 FLTR COMM 5 +VS 2.7V 150pF *R2, R3 OPTIONAL, *SEE TEXT 1.5k NC = NO CONNECT Figure 8. Dual Mode (GSM/DCS) PA Control Example The PA has a single gain control line; the band to be used is selected by applying either 0 V or 2 V to the PA’s VCTL input. Some of the output power from the PA is coupled off using a dual-band directional coupler (Murata part number LDC15D190A0007A). This has a coupling factor of approximately 19 dB for the GSM band and 14 dB for DCS and an insertion loss of 0.38 dB and 0.45 dB, respectively. Because the PF08107B transmits a maximum power level of +35 dBm for GSM and +32 dBm for DCS, additional attenuation of 20 dB is required before the coupled signal is applied to the AD8315. This results in peak input levels to the AD8315 of –4 dBm (GSM) and –2 dBm (DCS). While the AD8315 gives a linear response for input levels up to +2 dBm, for highly temperaturestable performance at maximum PA output power, the maximum input level should be limited to approximately –2 dBm (see TPC 3 and TPC 5). This does, however, reduce the sensitivity of the circuit at the low end. The operational setpoint voltage, in the range 250 mV to 1.4 V, is applied to the VSET Pin of the AD8315. This will typically be supplied by a digital-to-analog converter (DAC). The AD8315’s VAPC output drives the level control pin of the power amplifier directly. VAPC reaches a maximum value of approximately 2.5 V on a 2.7 V supply while delivering the 3 mA required by the level control input of the PA. This is more than sufficient to exercise the gain control range of the PA. During initialization and completion of the transmit sequence, VAPC should be held at its minimum level of 250 mV by keeping VSET below 200 mV. REV. B In this example, VSET is supplied by an 8-bit DAC that has an output range from 0 V to 2.55 V or 10 mV per bit. This sets the control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times 10 mV). If finer resolution is required, the DAC’s output voltage can be scaled using two resistors as shown. This converts the DAC’s maximum voltage of 2.55 V down to 1.6 V and increases the control resolution to 0.25 dB/bit. A filter capacitor (CFLT) must be used to stabilize the loop. The choice of CFLT will depend to a large degree on the gain control dynamics of the power amplifier, something that is frequently poorly characterized, so some trial and error may be necessary. In this example, a 150 pF capacitor is used and a 1.5 kW series resistor is included. This adds a zero to the control loop and increases the phase margin, which helps to make the step response of the circuit more stable when the PA output power is low and the slope of the PA’s power control function is the steepest. A smaller filter capacitor can be used by inserting a series resistor between VAPC and the control input of the PA. A series resistor will work with the input impedance of the PA to create a resistor divider and will reduce the loop gain. The size of the resistor divider ratio depends upon the available output swing of VAPC and the required control voltage on the PA. This technique can also be used to limit the control voltage in situations where the PA cannot deliver the power level being demanded by VAPC. Overdrive of the control input of some PAs causes increased distortion. It should be noted, however, that if the control loop opens (i.e., VAPC goes to its maximum value in an effort to balance the loop), the quiescent current of the AD8315 will increase somewhat, particularly at supply voltages greater than 3 V. –13– AD8315 Figure 9 shows the relationship between VSET and output power (POUT) at 0.9 GHz . The overall gain control function is linear in dB for a dynamic range of over 40 dB. Note that for VSET voltages below 300 mV, the output power drops off steeply as VAPC drops toward its minimum level of 250 mV. In Figure 10b, the matching components are drawn as generic reactances. Depending on the frequency, the input impedance and the availability of standard value components, either a capacitor or an inductor will be used. As in the previous case, the input impedance at a particular frequency is plotted on a Smith Chart and matching components are chosen (shunt or series L, shunt or series C) to move the impedance to the center of the chart. 4 40 +85 C 30 3 +25 C 2 20 +85 C 1 10 –30 C 0 0 –1 –10 ERROR – dB POUT – dBm +25 C A reactive match can also be implemented as shown in Figure 10b. This is not recommended at low frequencies as device tolerances will dramatically vary the quality of the match because of the large input resistance. For low frequencies, Option 10a or Option 10c is recommended. AD8315 –30 C –2 –20 RFIN RSHUNT 52.3 –3 –30 –40 0 0.2 0.4 0.6 0.8 VSET – V 1.0 1.2 1.4 CC CIN RIN –4 1.6 Figure 9. POUT vs. VSET at 0.9 GHz for Dual Mode Handset Power Amplifier Application; –30 ∞C, +25 ∞C, and +85 ∞C a. Broadband Resistive AD8315 Enable and Power-On The AD8315 may be disabled by pulling the ENBL pin to ground. This reduces the supply current from its nominal level of 7.4 mA to 4 mA. The logic threshold for turning on the device is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch is shown in TPC 20. Alternatively, the device can be completely disabled by pulling the supply voltage to ground. To minimize glitch in this mode, ENBL and VPOS should be tied together. If VPOS is applied before the device is enabled, a narrow 750 mV glitch will result (see TPC 27). X1 RFIN CC CIN X2 RIN b. Narrow Band Reactive ANTENNA In both situations, the voltage on VSET should be kept below 200 mV during power-on and power-off to prevent any unwanted transients on VAPC. AD8315 RFIN STRIPLINE RATTN Input Coupling Options The internal 5 pF coupling capacitor of the AD8315, along with the low frequency input impedance of 2.8 kW, give a high-pass input corner frequency of approximately 16 MHz. This sets the minimum operating frequency. Figure 10 shows three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at RFIN (Figure 10a). This 52.3 W resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the AD8315 to give a broadband input impedance of 50 W. While the input resistance and capacitance (CIN and RIN) of the AD8315 will vary from device to device by approximately ± 20%, and over frequency (TPC 9), the dominance of the external shunt resistor means that the variation in the overall input impedance will be close to the tolerance of the external resistor. This method of matching is most useful in wideband applications or in multiband systems where there is more than one operating frequency. CC CIN RIN PA c. Series Attenuation Figure 10. Input Coupling Options Figure 10c shows a third method for coupling the input signal into the AD8315. A series resistor, connected to the RF source, combines with the input impedance of the AD8315 to resistively divide the input signal being applied to the input. This has the advantage of very little power being “tapped off” in RF power transmission applications. –14– REV. B AD8315 Using the Chip Scale Package On the underside of the chip scale package, there is an exposed paddle. This paddle is internally connected to the chip’s ground. There is no thermal requirement to solder the paddle down to the printed circuit board’s ground plane. However, soldering down the paddle has been shown to increase the stability over frequency of the AD8315 ACP’s response at low input power levels (i.e., at around –45 dBm) in the DCS and PCS bands. J1 R2 52.3 R1 0 RFIN VPOS SW1 C1 0.1F 1 RFIN VPOS 8 2 ENBL VAPC 7 R3 0 J3 VSET C4 (OPEN) Evaluation Board Figure 11 shows the schematic of the AD8315 MSOP evaluation board. The layout and silkscreen of the component side are shown in Figures 12 and 13. An evaluation board is also available for the LFCSP package (for exact part numbers, see Ordering Guide). Apart from the slightly smaller device footprint, the LFCSP evaluation board is identical to the MSOP board. The board is powered by a single supply in the range, 2.7 V to 5.5 V. The power supply is decoupled by a single 0.1 F capacitor. Table II details the various configuration options of the evaluation board. TP1 AD8315 3 VSET NC 6 4 FLTR COMM 5 TP2 VPOS R4 (OPEN) J2 VAPC C2 (OPEN) NC = NO CONNECT LK1 LK2 VPOS C3 0.1F C5 0.1F R7 16.2k R8 10k AD8031 R6 17.8k R5 10k Figure 11. Evaluation Board Schematic Table II. Evaluation Board Configuration Options Component Function Default Condition TP1, TP2 SW1 Supply and Ground Vector Pins Device Enable: When in Position A, the ENBL pin is connected to VPOS and the AD8315 is in operating mode. In Position B, the ENBL pin is grounded putting the device in power-down mode. Input Interface: The 52.3 W resistor in Position R2 combines with the AD8315’s internal input impedance to give a broadband input impedance of around 50 W. A reactive match can be implemented by replacing R2 with an inductor and R1 (0 W) with a capacitor. Note that the AD8315’s RF input is internally ac-coupled. Output Interface: R4 and C2 can be used to check the response of VAPC to capacitive and resistive loading. R3/R4 can be used to reduce the slope of VAPC. Power Supply Decoupling: The nominal supply decoupling consists of a 0.1 mF capacitor. Filter Capacitor: The response time of VAPC can be modified by placing a capacitor between FLTR (Pin 4) and ground. Measurement Mode: A quasi-measurement mode can be implemented by installing LK1 and LK2 (connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET. In this mode, a large capacitor (0.01 mF or greater) must be installed in C4. Not Applicable SW1 = A R1, R2 R3, R4, C2 C1 C4 LK1, LK2 REV. B –15– R2 = 52.3 W (Size 0603) R1 = 0 W (Size 0402) R4 = C2 = Open (Size 0603) R3 = 0 W (Size 0603) C1 = 0.1 mF (Size 0603) C4 = Open (Size 0603) LK1, LK2 = Installed AD8315 For operation in controller mode, both jumpers, LK1 and LK2, should be removed. The setpoint voltage is applied to VSET, RFIN is connected to the RF source (PA output or directional coupler), and VAPC is connected to the gain control pin of the PA. When used in controller mode, a capacitor must be installed in C4 for loop stability. For GSM/DCS handset power amplifiers, this capacitor should typically range from 150 pF to 300 pF. Figure 12. Layout of Component Side (MSOP) A quasi-measurement mode (where the AD8315 delivers an output voltage that is proportional to the log of the input signal) can be implemented, to establish the relationship between VSET and RFIN, by installing the two jumpers, LK1 and LK2. This mimics an AGC loop. To establish the transfer function of the log amp, the RF input should be swept while the voltage on VSET is measured, that is, the SMA connector labeled VSET now acts as an output. This is the simplest method to validate operation of the evaluation board. When operated in this mode, a large capacitor (0.01 mF or greater) must be installed in C4 (filter capacitor) to ensure loop stability. Figure 13. Silkscreen of Component Side (MSOP) –16– REV. B AD8315 OUTLINE DIMENSIONS 8-Lead microSOIC Package [MSOP] (RM-8) Dimensions shown in millimeters 3.00 BSC 8 5 4.90 BSC 3.00 BSC 1 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.80 0.40 8 0 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA 8-Lead Lead Frame Chip Scale Package [LFCSP] 2 mm 3 mm Body (CP-8) Dimensions shown in millimeters 1.89 1.74 1.59 3.25 3.00 2.75 PIN 1 INDICATOR 1.00 0.90 0.80 SEATING PLANE 0.60 0.45 0.30 2.25 2.00 1.75 1.95 1.75 1.55 5 BOTTOM VIEW 4 2.95 2.75 2.55 0.50 BSC 12 0 1.00 MAX 0.65 NOM 0.30 0.23 0.18 0.05 0.02 0.00 0.20 REF NOTES 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2. PADDLE IS COPPER PLATED WITH LEAD FINISH. REV. B –17– 0.55 0.40 0.30 8 0.15 0.10 0.05 1 0.25 0.20 0.15 AD8315 Revision History Location Page 1/03—Data Sheet changed from REV. 0 to REV. B. Edits to PRODUCT DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TPC 9 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to TPC 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edit to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Equation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Equation 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Example section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Basic Connections section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Input Coupling Options section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table III becomes Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table II Recommended Components deleted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Using the Chip-Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8-Lead Chip Scale Package (CP-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 –18– REV. B –19– –20– PRINTED IN U.S.A. C01520-0-1/03(B)

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