= Dual PCI Hot-PlugTM Controller Preliminary Technical Data PAUXONA ADM1014 3.3V Cmos Input 30 7 +3.3VAux AUXGA 31 AUXINA S Q FAULT LATCH 3.3V Cmos Output FAUXA G RESET 5 D OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3VAUX SET Q P-CHANNEL MOSFET 8 AUXOA AUXINA AUXINA 3.3VAUX POWER-ON RESET 100µA CHANNEL A LOW WHEN AUXINA < 2.5V EXTERNAL N-CHANNEL POWER MOSFETS VOCSET OCSET 6 COMMON TO BOTH CHANNELS +5V IN CIRCUIT OPERATES FROM 3.3VAUX POWER SUPPLY +3.3V IN CIRCUIT OPERATES FROM 3.3VAUX AND +12V POWER SUPPLY 33 CHANNEL A PWRONA 3 OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +5V 34 OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3V 36 3V5VGA 5VSA RSENSE5A 35 37 5VISENA 3VSA 3VISENA RSENSE3A 9 12VGA Q FLTNA RESET 4 Q 32 G SET 12VIN A 5V REGULATOR GND S FAULT LATCH 12VIN A 12V IN POWER-ON RESET LOW WHEN 12VINA < 10V COMBINING LOGIC OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +12V P-CHANNEL MOSFET 29 12VIN A +5V OUTA +3.3V OUTA D 10 12VOA 2 -12VGA 38 -12VINA S G COMMON TO BOTH CHANNELS OVERCURRENT COMPARATOR FOR -12V N-CHANNEL MOSFET D 1 -12VOA 14 AUXGB 26 AUXINB EXTERNAL N-CHANNEL POWER MOSFETS +3.3V +5V IN IN 13 AUXOB PAUXONB 27 25 3V5VGB +3.3VAux 24 CHANNEL B 5VSB 5VISENB RSENSE5B 23 FAUXB 15 ( IDENTICAL TO CHANNEL A ) 22 PWRONB 17 21 12 FLTNB 16 3VSB 3VISENB RSENSE3B 12VGB 28 12VINB 11 12VOB 18 -12VGB 20 -12VINB +5V OUTA +3.3V OUTA 19 -12VOB FUNCTIONAL BLOCK DIAGRAM REV. PrN 1/02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. TM Hot Plug is a trademark of Core International, Inc. One Technology Way, Tel: 781/329-4700 Fax: 781/326-8703 P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com © Analog Devices, Inc., 2002 ADM1014–SPECIFICATIONS The ADM1014 operates from a +12V and +3.3V AUX supply and controls five independent supplies (+3.3V, +3.3VAUX, +5V, +12V and –12V) on two separate channels (A and B). The power switches for the +3.3VAUX, +12V and –12V supplies are integrated onto the chip, and internal current limiting is provided. For the +3.3V and +5V supplies, the device drives external, N-channel, power MOSFETs, and provides overcurrent protection by sensing the voltage drop across external current-sense resistors. FEATURES Controls Two PCI Slots Controls all Four PCI Supplies, +3.3V, +5V, +12V, -12V, plus 3.3V auxiliary supply Internal MOSFET Switches for +3.3V AUX, +12V and –12V outputs Adjustable Overcurrent Protection for all Outputs Undervoltage Protection on +3.3V, +5V, +12V and +3.3V AUX Supplies Open-Drain Fault Output with Adjustable Delay Logic Control of Outputs Adjustable Soft-start The current limits for all 10 supplies are set by a single resistor to GND, connected to the OCSET pin. Undervoltage sensing is provided on the +3.3V, +5V, +12V and +3.3VAux supplies. Overcurrent sensing is provided on all supplies. In the event of an overcurrent or undervoltage fault on any of the outputs of either channel, all outputs on that channel will be turned off. APPLICATIONS Compact PCI PCI Hot-PlugTM GENERAL DESCRIPTION Turn-on slew rate may be controlled using eight external capacitors, connected to the gate drives of all of the supplies. The ADM1014 is a dual PCI voltage bus controller that allows hot-plugging of adapter cards into and out of an active or passive backplane. The device requires only four external power MOSFETs and a few discrete components for a complete power-control solution for two PCI slots. Logic control of the four main outputs is provided by the PWRONA and PWRONB pins. When these pins are high, the outputs are turned on, when low, the outputs are turned off. The +3.3VAUX supplies have their own control inputs, PAUXA and PAUXB. (Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, VCC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.) Parameter 5V/ 3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Overcurrent Threshold Voltage 5V Undervoltage Trip Threshold 5V Undervoltage Fault Response Time 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Overcurrent Threshold Voltage 3V Undervoltage Trip Threshold 3V Undervoltage Fault Response Time 3V5VG Undervoltage Enable Threshold Voltage 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3V5VG Vout High Gate Output Charge Current Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time +12V SUPPLY CONTROL On Resistance of Internal PMOS On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold 12V Undervoltage Trip Threshold Undervoltage Fault Response Time Min Typ Max Units Test Conditions/Comments 33 70 4.42 - 8 42 80 4.65 110 9.75 50 90 4.7 160 - A mV mV V ns ms See Typical Application Diagram VOCSET = 0.6V VOCSET = 1.2V 41 89 2.74 - 10 52 98 2.86 110 9.6 62 108 2.9 160 - A mV mV V ns V - 9.75 - ms 11.5 19 - 11.8 25.0 280 29 - V µA µs C3V5VG = 0.033µF, C3VOUT = 2000µF, RL = 0.43⍀ PWRON = High, FLTN = High PWRON = High, V3V5VG = 4V C3V5VG = 0.033µF,3V5VG Rising 10% to 90% - 2 - µs C3V5VG = 0.033µF, 3V5VG Falling 90% to 10% 0.6 1.25 10.25 - 0.3 0.35 0.75 1.50 10.6 110 0.35 0.5 0.9 1.8 10.8 - ⍀ ⍀ A A V ns PWRON = High, ID = 0.5A, TA= TJ= 25oC PWRON = High, ID = 0.5A, TA= TJ= 70oC VOCSET = 0.6V VOCSET = 1.2V –2– C3V5VG = 0.033µF, C5VOUT = 2000µF, RL = 1⍀ See Typical Application Diagram OCSET = 0.6V OCSET = 1.2V REV. PrN 1/02 ADM1014–SPECIFICATIONS (Continued) (Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, VCC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.) Parameter Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS On Resistance of Internal NMOS Overcurrent Threshold Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time M12VIN Input Bias Current +3.3VAUX SUPPLY CONTROL On Resistance of Internal PMOS On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold 3.3VAUX Undervoltage Trip Threshold Undervoltage Fault Response Time Gate Charge Current Turn-On Time (PAUXON High to AUXG = 1V) Turn-Off Time 3.3VAUX Power On Reset Threshold CONTROL PINS 12VIN Supply Current AUXIN Supply Current OCSET Current Overcurrent to Fault Response Time PWRONA/B, PAUXA/B Threshold Voltage 12V Power On Enable Threshold 12V Power On Reset Threshold FAULT O/P PINS FLTA/B Output Low Voltage FLTA/B Output High Voltage FLTA/B, Output Latch Threshold FAUXA/B Output Low Voltage FAUXA/B Output High Voltage FAUXA/B Output Latch Threshold Min Typ Max Units Test Conditions/Comments 19 - 25.0 16 29 - µA ms PWRON = High, V 12VG = 10V C12VG = 0.033µF, 12VG Falling 90% - 10% - 4.5 - µs C12VG = 0.033µF, 12VG Rising 10% - 90% 0.13 0.23 19 - 0.7 1 0.18 0.38 25 16 1 1.3 0.25 0.52 29 - ⍀ ⍀ A A µA ms PWRON = High, ID = 0.1A, TA=TJ=25oC PWRON = High, ID = 0.1A, TA=TJ=70oC VOCSET = 0.6V VOCSET = 1.2V PWRON = High, VM12VG = -10V CM12VG = 0.033µF, CM12VO= 50µF,RL= 120⍀ - 3 2.5 5 µs mA CM12VG=0.033µF,M12VG Falling 90% -10% PWRON = High 19 0.25 0.25 0.5 1.0 2.9 110 25.0 TBD TBD TBD TBD TBD 29 ⍀ ⍀ A A V ns µA PAUXON = High, ID = 0.375A, TA=TJ=25oC PAUXON = High, ID = 0.375A, TA=TJ=70oC VOCSET = 0.6V VOCSET = 1.2V PAUXON = High, VAUXG = 3V - 16 3 2.5 - ms µs V CAUXG = 0.033µF CAUXG = 0.033µF, AUXG Rising 10% - 90% AUXIN Voltage Rising 93 1.0 9.4 8.9 5.3 3 100 500 1.6 10 9.1 8 TBD 107 960 2.1 10.2 9.3 mA mA µA ns V V V 12VINA Voltage Rising 12VINA Voltage Falling V V V V V V IFLT = 2mA IFLT = 0 IFLT High to Low transition IFAUX = 2mA IFAUX = 0 IFAUX High to Low transition - 0.5 AUXIN-0.5 AUXIN-0.1 0.7 TBD 1.6 TBD 0.5 0.7 AUXIN-0.5 AUXIN-0.1 TBD 1.6 TBD NOTES Specifications subject to change without notice. REV. PrN 1/02 –3– ADM1014–SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (TA = +25°C unless otherwise noted) VCC , 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO, 12VG, 3V5VG . . . . . . . . . . -0.5V to V 12VIN +0.5V -12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V -12VO, -12VG . . . . . . . . . . . . . . . . . . . V-12VIN -0.5V to +0.5V 3VISEN, 5VISEN . . . -0.5V to the Lesser of 12VIN or +7.0V Voltage, Any Other Pin . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A -12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A Continuous Power Dissipation (TA = +70oC) . . . . . . 667mW TSSOP (derate 8.3mW/oC above +70oC) Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Model Temperature Range Package Description Package Option ADM1014JRU 0°C to +70°C 38-Pin TSSOP RU-38 PIN CONFIGURATION M12VOA 1 38 M12VINA M12VGA 2 37 3VISENA PWRONA 3 36 3VSA FLTNA 4 35 5VISENA FAUXA 5 34 5VSA OCSET 6 33 3V5VGA AUXGA 7 32 GND AUXOA 8 12VGA 9 ADM1014 30 PAUXONA 12VOA 10 29 12VINA 12VOB 11 TOP VIEW (Not to Scale) 12VGB 12 27 PAUXONB THERMAL CHARACTERISTICS AUXOB 13 26 AUXINB 38-Pin TSSOP Package: qJA = 100°C/Watt, qJC = 10°C/Watt AUXGB 14 FAUXB 15 25 3V5VGB 24 5VSB FLTNB 16 23 5VISENB PWRONB 17 22 3VSB M12VGB 18 21 3VISENB M12VOB 19 20 M12VINB *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. –4– 31 AUXINA 28 12VINB REV. PrN 1/02 ADM1014 PIN FUNCTION DESCRIPTION Pin Mnemonic Function 1 M12VOA Switched -12V output for channel A. Rated for 100mA. 2 M12VGA Gate of channel A internal NMOS transistor. A capacitor connected from this pin to -12VOA (pin 1) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. 3 PWRONA Power on control for channel A. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONA high = outputs on, PWRONA low = outputs off. 4 FLTNA Active-low, 5V compatible, Open Drain fault output for channel A. A pull-up resistor connects the pin to 3.3VAux. 4.7k⍀ is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. 5 FAUXA Active-low, 3.3V compatible, Open Drain fault output for Aux channel A. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. 6 OCSET Overcurrent set for all 10 outputs. A resistor connected from this pin to ground sets the overcurrent trip point of all eight supplies. All eight overcurrent trip-points can be programmed by changing the value of this resistor. The default value of 6.04k⍀, ±1% is compatible with the maximum currents allowed by the PCI specification. 7 AUXGA Gate of channel A +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOA (pin 8) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25µA current source. 8 AUXOA Switched 3.3V auxiliary output for channel A. Rated for 0.375A. 9 12VGA Gate of channel A internal PMOS transistor. A capacitor connected from this pin to 12VOA (pin 10) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 12VGA rises above 1.2V. If the capacitor on pin 7 (AUXGA) or pin 33 (3V5VGA) is more than 25% larger than the capacitor on pin 9 (12VGA) a false undervoltage condition may be detected during startup. 10 12VOA Switched 12V output for channel A. Rated for 0.5A. 11 12VOB Switched 12V output for channel B. Rated for 0.5A. 12 12VGB Gate of channel B internal PMOS transistor. A capacitor connected from this pin to 12VOB (pin 11) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 12VGB rises above 1.2V. If the capacitor on the pin 25 (3V5VGB) or pin 14 (AUXGB) is more than 25% larger than the capacitor on pin 12 (12VGB) a false undervoltage condition may be detected during startup. 13 AUXOB Switched 3.3V auxiliary output for channel B. Rated for 0.375A. 14 AUXGB Gate of channel B +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOB (pin 13) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25µA current source. 15 FAUXB Active-low, 3.3V compatible, Open Drain fault output for Aux channel B. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. 16 FLTNB Active-low, 5V compatible, Open Drain fault output for channel B. A pull-up resistor connects the pin to 3.3VAux. 4.7k⍀ is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. 17 PWRONB Power on control for channel B. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONB high = outputs on, PWRONB low = outputs off. 18 M12VGB Gate of channel B internal NMOS transistor. A capacitor connected from this pin to -12VOB (pin 19) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. 19 M12VOB Switched -12V output for channel B. Rated for 100mA. REV. PrN 1/02 –5– ADM1014 PIN FUNCTION DESCRIPTION (CONTINUED) Pin Mnemonic Function 20 M12VINB -12V supply input for channel B. Also provides power to the -12V overcurrent circuitry. 21 3VISENB 3.3V current sense for channel B. A current-sensing resistor is connected between this pin and 3VSB (pin 22). Connect to the load side of the current sense resistor. 22 3VSB 3.3V source for channel B. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 21. 23 5VISENB 5V current sense for channel B. A current-sensing resistor is connected between this pin and 5VSB (pin 24). Connect to the load side of the current sense resistor. 24 5VSB 5V source for channel B. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 23. 25 3V5VGB 3.3V and 5V gate output for channel B, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 3V5VGB falls below 12VIN-1.2V. 26 AUXINB +3.3V auxiliary supply input for channel B. 27 PAUXONB Power on control for channel B +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONB high = outputs on, PAUXONB low = outputs off. 28 12VINB Switched +12V supply input for channel B. 29 12VINA Switched +12V supply input for channel A and for OCSET and power-on RESET circuits. 30 PAUXONA Power on control for channel A +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONA high = outputs on, PAUXONA low = outputs off. 31 AUXINA +3.3V auxiliary supply input for channel A. 32 GND Ground for all chip circuits. Connect to common of power supplies. 33 3V5VGA 3.3V and 5V gate output for channel A, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 3V5VGA falls below 12VIN-1.2V. 34 5VSA 5V source for channel A. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 35. 35 5VISENA 5V current sense for channel A. A current-sensing resistor is connected between this pin and 5VSA (pin 34). Connect to the load side of the current sense resistor. 36 3VSA 3.3V source for channel A. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 37. 37 3VISENA 3.3V current sense for channel A. A current-sensing resistor is connected between this pin and 3VSA (pin 36). Connect to the load side of the current sense resistor. 38 M12VINA -12V supply input for channel A. Also provides power to the -12V overcurrent circuitry. –6– REV. PrN 1/02 ADM1014 FA U X AUXG VC VC AUXIN C C PAUXON COMP CURRENT TRACKING AND I-V CONVERTER VOCSET/1.2 COMP AUXO 4.6V INHIBIT COMP 2.9V INHIBIT FLT COMP 10.8V INHIBIT 5VISEN VOCSET/14.5 COMP 5VS VCC 3V5VG ZENER REFERENCE 3VISEN COMP VCC VOCSET/11.5 3VS COMMON TO BOTH CHANNELS 12VG VCC 100µA 12VIN VOCSET OCSET VCC 12V IN POWER-ON RESET LOW WHEN VCC < 10V COMP VOCSET/0.8 CURRENT TRACKING AND I-V CONVERTER 12VO -12VG GND -12VIN VCC -12VIN PWRON COMP VOCSET/3.3 CURRENT TRACKING AND I-V CONVERTER VCC -12VO 3V5VG CIRCUIT OF ONE CHANNEL SHOWN, BOTH CHANNELS ARE IDENTICAL. RESET AND OCSET CIRCUITRY WITHIN DASHED LINE IS COMMEON TO BOTH CHANNELS Figure 1. Simplified Schematic REV. PrN 1/02 –7– ADM1014 Note: The OCSET current source obtains its power supply from 12VINA. FUNCTIONAL DESCRIPTION VOLTAGE OUTPUTS The ADM1014 consists of two independent, identical channels, A and B, each of which controls four main power supply voltages and an auxiliary voltage. As the channels are identical, the following description applies to either channel, except where otherwise stated. An on-chip PMOS transistor connected between 12VIN and 12VO switches the +12V supply at currents up to 1.5A, whilst an on-chip NMOS transistor connected between -12VIN and -12VO switches the –12V supply at currents up to 0.38A. The +3.3V and +5V supplies are switched by external, N-channel MOSFETs, whose gate drive is provided by the 3V5VG pins. Using suitable MOSFETs, singly or in parallel, currents of several amps may be switched with very low voltage drops. INTERNAL CURRENT LIMIT The +3.3VAUX, +12V and –12V supplies have the power MOSFET switches on-chip. These devices are protected and overcurrent shutdown is provided by a completely self-contained current sensing system. The output current through the on-chip power MOSFET is tracked at a lower level by a second, smaller MOSFET. The current through this MOSFET is then converted to a voltage, which is compared to a reference voltage determined by RSET. In the case of the +12V and -12V outputs, if the current-sense voltage exceeds this reference voltage, the comparator output will go high, the fault latch will be set and all four main outputs and the auxiliary output will be turned off. Similarly in the case of the auxiliary output, if the currentsense voltage exceeds the reference voltage, the comparator output will go high, the fault latch will be set, FAUXN/FLTN will go low, and the auxiliary output and the four main outputs will turn off. The four main power supplies may be switched on and off under control of the PWRON pin. The 3.3V auxiliary supply has an on-chip PMOS transistor, which can switch currents at up to 1A. This supply is controlled independently of the other four supplies by the PAUXON pin. The typical internal limiting currents may be calculated as follows: ILIMIT (+3.3VAUX) = VOCSET /1.2 = (10-4 ⫻ RSET)/1.2 All five supplies are protected against overcurrent and the four positive supplies are also protected against undervoltage. ILIMIT (+12V) = 1.25 ⫻ 10-4 ⫻ RSET EXTERNAL CURRENT LIMIT The external power MOSFETs are protected and overcurrent shutdown is provided on the +3.3V and +5V supplies by external current-sense resistors and on-chip comparators. ILIMIT (-12V) = VOCSET /3.3 = (10-4 ⫻ RSET)/3.3 Where: Current-sensing resistors are connected between the +5V output pin and the 5VISEN pin, and between the +3.3V output pin and the 3.3VISEN pin. The sense pins are connected to the inverting inputs of the current-limit comparator directly, while the voltage outputs are connected to the non-inverting inputs via a reference voltage proportional to the voltage on the OCSET pin. This voltage is VOCSET/14.5 in the case of the 5V output and VOCSET/11.5 in the case of the 3.3V output. These values were chosen so that the 3.3V and 5V sense resistors could both be 5m⍀ in PCI applications. ILIMIT = current limit in Amps RSET is resistor from OCSET to GND in ⍀ Due to tolerances in the current tracking FETs, the variations in the internal current limit are quite wide, typically ±20% of the calculated value for the +12V supply and +35/-20% of the calculated value for the –12V supply. CHOICE OF RSET AND RSENSE When the voltage drop across the current-sensing resistor exceeds the reference voltage, the output of the comparator will go high, the fault latch will be set and all four main outputs and the auxiliary output on the channel will be turned off. The other main channel and auxiliary channel will remain on. Using the above equations, RSET is chosen to set the required current limits for the +3.3VAUX, +12V and -12V supplies. Once RSET has been chosen, RSENSE3 and RSENSE5 can be chosen to set the current limits for the 3.3V and 5V outputs. For PCI applications RSET should be 6.04k⍀ and the current sense resistors should both be 5m⍀±1%. This will set the current limits to the maximum values for the PCI specification. For other applications, the following limits should be noted. The reference voltages for the current-limit comparators are set by connecting a resistor between the OCSET pin and GND. An on-chip, 100µA current source generates a voltage across this resistor. The current limit may also be adjusted by the choice of current-sensing resistor. 1. The minimum value of RSET is limited by the minimum voltage the current–limit comparators can reliably sense, which is determined by noise, comparator offset voltage and the overdrive required to switch the comparator. The reference voltage set by RSET should not be less than 33mV for the 5V output, which has the smallest reference voltage. The minimum recommended value for RSET is 6k⍀, which gives a reference voltage of 35mV for the 5V output and 45mV for the 3.3V output. ILIMIT(3.3V) = VOCSET/(11.5 ⫻ RSENSE3) = (RSET ⫻ 10-4)/(11.5 ⫻ RSENSE3) ILIMIT(5V) = 1.25 ⫻ VOCSET = VOCSET/(14.5 ⫻ RSENSE5) = (RSET ⫻ 10-4)/(14.5 ⫻ RSENSE5) Where: ILIMIT = current limit in Amps 2. The maximum value of RSET is limited by the junction temperature. This is determined by the power dissipated in the onchip MOSFETs, (which is dependent upon the current passed RSET is resistor from OCSET to GND in ⍀ RSENSE is current-sense resistor in ⍀ –8– REV. PrN 1/02 ADM1014 by the devices and their on-resistance), the thermal resistance of the package (100oC/W), and the ambient temperature. The maximum on-resistance of the +3.3VAUX MOSFET is 0.65⍀, that of the +12V MOSFET is 0.35⍀ and that of the – 12V MOSFET is 0.9⍀, so the power dissipation will be: PD = (0.65 ⫻ (I+3.3VAUX)2 + 0.35 ⫻ (I+12V)2 + 0.9 ⫻ (I-12V)2) Where: PD is power dissipation in Watts I is current in Amps Under normal operating conditions the maximum recommended value for RSET is 15k⍀. Figure 2. FLTN and 3V5VG Delay TABLE 1. FLT AND 3V5VG DELAY VS. CFLT UNDERVOLTAGE SENSING Undervoltage sensing of the +3.3V, +5V, +12V and +3.3VAUX supplies is carried out by four voltage comparators. The supply voltages being monitoring are applied to the inverting inputs of these comparators, whilst reference voltages of 2.9V, 4.6V, 10.8V and 2.9V (derived from an on-chip zener reference) are applied to their non-inverting inputs. Should any of the output voltages fall below the corresponding reference voltage, the output of the comparator will go high, the fault latch will be set, turning off all the supplies (main and auxiliary) on that channel. CFLT tA t2A OPEN 0.1µs 0.05µs 0.001µF 0.44µs 0.22µs 0.01µF 2.9µs 1.5µs 0.1µF 28µs 14µs POWER CONTROL INPUTS FLTN AND FAUXN OUTPUTS The FLTN and FAUXN outputs are active-low, 3.3V compatible, Open- Drain fault outputs. These outputs are shorted together and then connected to the 3.3VAux supply using a 4.7k⍀ pull-up resistors. Should an overcurrent or undervoltage event occur on one of the supplies, main or auxiliary, then the fault latch will be set, FLTA and FAUXA or FLTB and FAUXB will go low and all outputs on the faulting channel will be turned off. The PWRONA and PWRONB inputs are 3.3V CMOS-compatible logic inputs, which may be used to switch all four main outputs on and off, and is also used to reset the fault latch and turn the outputs back on after an overcurrent or undervoltage shutdown. When PWRON is high, the four main supplies are turned on. With PWRON held low, the supplies are turned off. After an overcurrent or undervoltage shutdown, PWRON should be toggled low then high again to reset the fault latch and turn on the outputs. PAUXONA and PAUXONB are also 3.3V CMOS-compatible logic inputs which perform a similar function for the +3.3V auxiliary supplies. PROGRAMMABLE FAULT LATCH DELAY The delay between an overcurrent or undervoltage fault occurring and the outputs shutting down may be set by connecting a capacitor between a FLTN or FAUXN output and GND. This delays the start of the FLTN/FAUXN output 1 to 0 transition and slows down the fall time of the FLTN/FAUXN output, thus delaying shutdown of the outputs. If the fault latch threshold (~1.6V) is reached on FLTN/FAUXN then the fault latch will be set and the four supply outputs and the auxiliary output will be shut down. If the fault disappears before the latching threshold is reached, the fault latch will not be set and the FLTN/FAUXN output will return to a high state. POWER-ON SEQUENCE AND SOFT START When the device is powered on with PWRON held high, the outputs are inhibited by the power-on reset circuit and will not become active until VCC exceeds 10V. During this time the undervoltage comparators are inhibited and the fault latch is held in a reset condition. Note: the power-on reset circuit monitors 12VINA. After the power-on delay, all five outputs are turned on simultaneously. The undervoltage comparators are enabled when the voltage on the gate of the internal PMOS transistor, 12VG, has fallen below about 400mV. This adjustable delay allows the ADM1014 to ignore overcurrent and undervoltage transients that might otherwise cause an unwanted shutdown. It should be noted that if a fault is asserted on FLTN and FAUXN at the same time, then the delay is halved, as shown in fig. 2 and Table 1. The rise time of the outputs may be controlled by connecting capacitors between the gate and output pins of the +3.3VAUX, +12V and -12V outputs, and from the 3V5VG pin to GND. During output turn-on, these capacitors are charged from a nominal 25µA current source. Limiting the output rise times also limits the charging currents drawn by any supply decoupling capacitors in the circuits being driven. With fast turn-on these currents might be excessive and cause overcurrent faults at power-on. Care must be taken when choosing these capacitors. If the capacitor on AUXG or 3V5VG is more than 25% larger than REV. PrN 1/02 –9– ADM1014 the capacitor on 12VG, the +3.3VAUX, 3.3V and 5V outputs may not have exceeded their undervoltage thresholds by the time the undervoltage comparators are enabled, and a false undervoltage condition may be detected. For this reason it is recommended to use the same value for all three gate capacitors. APPLICATIONS INFORMATION APPLICATION CIRCUIT For PCI applications the minimum recommended value is 0.033µF. Smaller values may cause overcurrent faults at powerup due to excessive charging currents drawn by decoupling capacitors. Figure 3 shows a typical circuit configuration for the ADM1014 in a PCI application, controlling supply voltages of +3.3V at up to 7.6A, +5V at up to 5A, +12V at up to 0.5A and –12V at up to 0.1A. In this circuit, two external MOSFETs are connected in parallel for the 3.3V and 5V outputs to minimise on-resistance. The maximum value of the gate capacitors is determined by the need to discharge them quickly when turning off the outputs under fault conditions. If the capacitors are too large the ADM1014 may be unable to protect the power bus or the external MOSFETs. With 0.033µF capacitors, the turn-off time will be less than 6µs. SLOT 1 12V -12V +3.3Vaux 5V 3.3V AUXINA AUXGA C1 AUXOA 5VISENA M12VINA M12GA R1 C2 5VSA M12VOA Q1 3V5VGA C3 M12VINB M12GB 3V5VGB M12VOB 5VSB Q2 FROM SYSTEM CONTROLLER R3 3VSA 12VINB 12VGB C5 5V BUS -12V BUS 3VISENA ADM1014 12VOA 3.3V BUS C4 +12V BUS +3.3Vaux BUS R2 5VISENB 12VINA 12VGA Q3 12VOB Q4 AUXINB AUXGB 3VSB AUXOB 3VISENB R4 C6 C7 C8 PAUXONA PWRONA PWRONB PAUXONB FAUXA FLTNB FLTNA R11 C9 C10 C11 FAUXB C12 OCSET GND R5 R12 TO SYSTEM CONTROLLER SLOT 2 12V -12V +3.3Vaux 3.3V 5V Figure 3. Typical Application Circuit –10– REV. PrN 1/02 ADM1014 RL1 25 0m A +12V C1 RL2 50m A -12V C2 R L3 37 5m A 3.3Vaux C3 GND RL4 2A 5.0V C4 R L5 3A 3.3V C5 Figure 4. Load Board for Typical Application Circuit Main Board Components Load Board Components Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Item 1 2 3 4 5 6 7 8 Qty 1 1 4 4 4 2 2 2 8 4 3 1 8 2 4 1 1 4 1 4 2 Ref Des U1 SKT1 Q1-4 D1-4 R1-4 R5-6 R7-8 R9-10 C1-8 C9-12 C13-15 S1 T1-8 P1-2 J1 J4-J6 J2 J3 P4-7 PCB R11-12 Load Board REV. PrN 1/02 Description ADM1014 38 Pin Tssop Socket IRF7413 Power Mosfet Green SMD LED 5m⍀ Metal Strip Resistor 470⍀ 0805 chip resistor 1K5⍀ 0805 chip resistor 6K04⍀ 0805 chip resistor CAP,0.033UF CAP,0.47UF Electrolytic capacitor space SPDT Slide Switch Testpoint 20 Pin Edge Conn Skt 4mm 10A PCB Sockets-Red 4mm 10A PCB Sockets-Green 4mm 10A PCB Sockets-Black SMB EVAL-ADM1014 Main Board 4K7⍀ 0805 chip resistor Fully Assembled Load Board –11– Qty 1 3 2 1 1 1 1 1 Ref Des PCB CL1-CL3 CL4-CL5 RL1 RL2 RL3 RL4 RL5 Description EVAL-ADM1014Load Board 100uF 16V Electrolytic Caps 2200uF 16V Electrolytic Caps 47⍀ 6W (W22 Series) Res 240⍀ 2.5W (W21 Series) Res 10⍀ 6W (W22 Series) Res 2.2⍀ 12W (W24 Series) Res 1⍀ 12W (W24 Series) Res ADM1014 LAYOUT CONSIDERATIONS Any circuits supplied by the ADM1014 are outside the control loops of the main system power supplies, which means that any series resistance between the four supply inputs and the outputs will cause a degradation of the supply load regulation. This includes connector contact resistance, PCB trace resistance, onresistance of MOSFETs (both external and on-chip) and current sense resistors. Care must therefore be taken to ensure that: CURRENT SENSE RESISTORS 35 37 34 36 22 24 21 23 VSENSE VSENSE a) PCB traces are as heavy as possible. 34 b)External MOSFETs have low-on resistance. ADM1014 c) Current sense resistors are as small as possible. The current sense resistors have very small values (5m⍀ in the preceding example) to minimise the voltage drop across them. Because of this, PCB trace resistance can be a significant percentage of the sense resistance. It is therefore essential to ensure that the ADM1014 senses the voltage drop directly across the sense resistors and not across any current-carrying trace resistance in series with them. Connections from the ADM1014 to the sense resistors must go directly to the ends of the resistors. Figure 4 shows examples of good and bad practice CORRECT CURRENT SENSE RESISTORS 21 35 37 34 36 ADDITIONAL VOLTAGE DROP VSENSE ADDITIONAL VOLTAGE DROP ADDITIONAL VOLTAGE DROP 22 24 21 23 VSENSE ADDITIONAL VOLTAGE DROP ADM1014 INCORRECT Figure 4. Good and Bad Practice For Sense Resistor Connection OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 38-Pin TSSOP (RU-38) 0.386 (9.80) 0.378 (9.60) 20 38 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 19 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0433 (1.10) MAX 0.0200 (0.50) 0.0106 (0.27) BSC 0.0067 (0.17) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) –12– REV. PrN 1/02