a FEATURES Low Offset Voltage: 250 V Low Noise: 6 nV/√ Hz Low Distortion: 0.0006% High Slew Rate: 22 V/s Wide Bandwidth: 9 MHz Low Supply Current: 5 mA Low Offset Current: 2 nA Unity-Gain Stable SO-8 Package APPLICATIONS High Performance Audio Active Filters Fast Amplifiers Integrators GENERAL DESCRIPTION The OP285 is a precision high-speed amplifier featuring the Butler Amplifier front-end. This new front-end design combines the accuracy and low noise performance of bipolar transistors with the speed of JFETs. This yields an amplifier with high slew rates, low offset and good noise performance at low supply currents. Bias currents are also low compared to bipolar designs. The OP285 offers the slew rate and low power of a JFET amplifier combined with the precision, low noise and low drift of a bipolar amplifier. Input offset voltage is laser-trimmed and guaranteed less than 250 µV. This makes the OP285 useful in dc-coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. Slew rates of 22 V/µs and a bandwidth of 9 MHz make the OP285 one of the most accurate medium speed amplifiers available. Dual 9 MHz Precision Operational Amplifier OP285* PIN CONNECTIONS 8-Lead Narrow-Body SO (S-Suffix) 8 V+ OUT A 1 –IN A 2 7 OUT B OP285 TOP VIEW (Not to Scale) +IN A 3 6 –IN B 5 +IN B V– 4 8-Lead Epoxy DIP (P-Suffix) OUT A 1 –IN A 2 +IN A 3 V– 4 – + + – OP285 8 V+ 7 OUT B 6 –IN B 5 +IN B The combination of low noise, speed and accuracy can be used to build high speed instrumentation systems. Circuits such as instrumentation amplifiers, ramp generators, bi-quad filters and dc-coupled audio systems are all practical with the OP285. For applications that require long term stability, the OP285 has a guaranteed maximum long term drift specification. The OP285 is specified over the XIND—extended industrial— (–40°C to +85°C) temperature range. OP285s are available in 8-pin plastic DIP and SOIC-8 surface mount packages. *Patents pending REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 OP285–SPECIFICATIONS (@ Vs = 15.0 V, TA = 25C, unless otherwise noted.) Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large-Signal Voltage Gain Symbol VOS VOS IB IB IOS IOS VCM CMRR AVO AVO AVO Common-Mode Input Capacitance Differential Input Capacitance Long-Term Offset Voltage ∆VOS Offset Voltage Drift ∆VOS/∆T OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY Power Supply Rejection Ratio Supply Current DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin Settling Time Current Noise Density Headroom –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C Typ Max Unit 35 250 600 350 400 ± 50 ± 100 10.5 µV µV nA nA nA nA V 100 2 2 –10.5 VCM = ± 10.5 V, –40°C ≤ TA ≤ +85°C RL = 2 kΩ RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω 80 250 175 106 1 dB V/mV V/mV V/mV pF pF µV µV/°C 200 7.5 3.7 Note 1 300 RL = 2 kΩ RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω, VS = ± 18 V –13.5 –13 +13.9 +13.5 +13.9 +13 –16/+14 V V V PSRR PSRR VS = ± 4.5 V to ± 18 V VS = ± 4.5 V to ± 18 V, –40°C ≤ TA ≤ +85°C VS = ± 4.5 V to ± 18 V, VO = 0 V, RL = x, –40°C ≤ TA ≤ +85°C VS = ± 22 V, VO, = 0 V, RL = x –40°C ≤ TA ≤ +85°C 85 111 dB ISY VS SR GBP o ts ts Distortion Voltage Noise Density Min VO VO ISY Supply Voltage Range Conditions en en in RL = 2 kΩ 80 4 ± 4.5 15 To 0.1%, 10 V Step To 0.01%, 10 V Step AV = 1, VOUT = 8.5 V p-p, f = 1 kHz, RL = 2 kΩ f = 30 Hz f = 1 kHz f = 1 kHz THD + Noise ≤ 0.01%, RL = 2 kΩ, VS = ± 18 V dB 5 mA 5.5 ± 22 mA V 22 9 62 625 750 V/µs MHz Degrees ns ns –104 7 6 0.9 dB nV/√Hz nV/√Hz pA/√Hz >12.9 dBu NOTE 1 Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3. Specifications subject to change without notice. –2– REV. A OP285 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 7.5 V Output Short-Circuit Duration to Gnd3 . . . . . . . . . Indefinite Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP285G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 Sec) . . . . . . . . 300°C Package Type JA4 JC Unit 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 103 158 43 43 °C/W °C/W NOTES 1 Absolute Maximum Ratings apply to packaged parts, unless otherwise noted. 2 For supply voltages less than ± 7.5 V, the absolute maximum input voltage is equal to the supply voltage. 3 Shorts to either supply may destroy the device. See data sheet for full details. 4 JA is specified for the worst case conditions, i.e., JA is specified for device in socket for cerdip, P-DIP, and LCC packages; JA is specified for device soldered in circuit board for SOIC package. ORDERING GUIDE Model OP285GP* OP285GS OP285GSR Temperature Range Package Description Package Option –40°C to +85°C 8-Pin Plastic DIP N-8 –40°C to +85°C 8-Pin SOIC S0-8 –40°C to +85°C S0-8 Reel, 2500 pcs. *Not for new designs. Obsolete April 2002. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP285 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE OP285 1500 1250 +VOM 10 5 0 –5 –10 –VOM –15 30 VS = 15V VO = 10V 1000 750 –GAIN RL = 2k +GAIN RL = 600 500 5 10 15 20 SUPPLY VOLTAGE – V 0 –50 25 25 0 50 50 75 100 0 CLOSED-LOOP GAIN – dB –SR 40 35 +SR 25 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL INPUT VOLTAGE – V TPC 3. Slew Rate vs. Differential Input Voltage 60 VS = 15V TA = +25C 40 45 SLEW RATE – V/s –SR 10 0 –25 TPC 2. Open-Loop Gain vs. Temperature VS = 15V RL = 2k 30 +SR TEMPERATURE – C TPC 1. Output Voltage Swing vs. Supply Voltage 50 15 5 AVCL = +100 VS = 15V TA = 25C 50 30 20 IMPEDANCE – 0 20 –GAIN RL = 600 250 –20 –25 VS = 15V RL = 2k 25 +GAIN RL = 2k SLEW RATE – V/s 15 OPEN-LOOP GAIN – V/MV OUTPUT VOLTAGE SWING – V 25 TA = 25C 20 RL = 2k AVCL = +10 10 0 AVCL = +1 AVCL = +1 40 AVCL = +10 30 20 AVCL = +100 –10 10 –20 25 50 0 TEMPERATURE – C 75 1k 100k 1M 10M 100M POWER SUPPLY REJECTION – dB 80 60 40 20 1k 10k 100k 1M 10M FREQUENCY – Hz TPC 7. Common-Mode Rejection vs. Frequency 10k 100k 1M 10M TPC 6. Closed-Loop Output Imped ance vs. Frequency 100 120 VS = 15V TA = 25C 100 1k FREQUENCY – Hz TPC 5. Closed-Loop Gain vs. Frequency 120 COMMON MODE REJECTION – dB 10k FREQUENCY – Hz TPC 4. Slew Rate vs. Temperature 0 100 0 100 –30 100 80 100 GAIN +PSRR VS = 15V TA = 25C 80 60 –PSRR 40 20 VS = 15V RL = 2k TA = 25C 0 45 60 0N = 58 40 90 PHASE 20 135 0 180 –20 225 –40 270 PHASE – Degrees –25 OPEN-LOOP GMIN – dB 20 –50 –60 0 10 100 1k 10k 100k FREQUENCY – Hz TPC 8. Power Supply Rejection vs. Frequency –4– 1M 1k 10k 100k 1M 10M 100M FREQUENCY – Hz TPC 9. Open-Loop Gain, Phase vs. Frequency REV. A Typical Performance Characteristics–OP285 65 16 90 øM 9 55 GBW 50 8 A VCL = +1 NEGATIVE EDGE 80 OVERSHOOT – % 10 60 70 60 AVCL= +1 POSITIVE EDGE 50 40 30 VS = 15V RL = 2k VIN = 100mV p-p 20 10 7 –50 0 –25 25 50 40 100 75 0 300 200 400 500 TPC 11. Small-Signal Overshoot vs.| Load Capacitance 30 ABSOLUTE OUTPUT CURRENT – mA SUPPLY CURRENT – mA 20 15 TA = 25C VS = 15V AVCL = +1 RL = 2k 0 10k 100k 1M 4.5 TA = +85C 4.0 TA = +25C TA = –40C 3.5 0 FREQUENCY – Hz 10 15 25 CURRENT NOISE DENSITY – pA/ Hz 250 200 150 100 50 0 25 TA = 25C VS = 15V 2 1k LOAD RESISTANCE – 50 75 TEMPERATURE – C TPC 16. Input Bias Current vs. Temperature 100 10k VS = 15V 110 100 90 SINK 80 70 60 50 40 SOURCE 30 –25 0 25 50 75 100 TEMPERATURE – C TPC 15. Short Circuit Current vs. Temperature 250 5 VS = 15V REV. A 5 TPC 14. Supply Current vs. Supply Voltage 300 –25 4 SUPPLY VOLTAGE – V TPC 13. Maximum Output Swing vs. Frequency 0 –50 +VOM 6 20 –50 3.0 10M –40C TA +85C 402 OP AMPS VS = 15V TA = 25C 4 200 3 150 UNITS 1k 8 120 25 5 10 TPC 12. Maximum Output Voltage vs. Load Resistance 5.0 10 –VOM 12 LOAD CAPACITANCE – pF TPC 10. Gain Bandwidth Product, Phase Margin vs. Temperature MAXIMUM OUTPUT SWING – V 100 14 0 100 0 TEMPERATURE – C INPUT BIAS CURRENT – nA MAXIMUM OUTPUT SWING – Volts 100 PHASE MARGIN – Degrees GAIN BANDWIDTH PRODUCT – MHz 11 2 100 1 50 0 10 100 1k FREQUENCY – Hz 100k TPC 17. Current Noise Density vs. Frequency –5– 0 1 2 3 4 5 6 7 TC VOS – V/ C 8 TPC 18. tC VOS Distribution 9 10 OP285 250 10 TA= 25C 402 OP AMPS 50 200 +0.1% +0.01% STEP SIZE – V 4 UNITS 100 2 0 –2 –4 50 45 SLEW RATE – V/S 6 150 TA = 25C VS = 15V 8 –0.1% –6 –0.01% –SR 40 35 30 +SR 25 –8 0 –250 –200 –150 –100 –50 0 50 100 150 200 250 0 INPUT OFFSET – V TPC 19. Input Offset (VOS) Distribution 20 –10 0 100 200 300 400 500 600 700 800 900 SETTLING TIME – ns 100 100 90 90 90 10 10 10 0% 0% 0% 200nS TPC 22. Negative Slew Rate RL =2 kΩ, VS = ± 15 V, AV = +1 CH A: 80.0 V FS MKR: 6.23 V/ Hz 0 Hz MKR: 1 000 Hz 5V 200nS TPC 23. Positive Slew Rate RL = 2 kΩ, VS = ± 15 V, AV = +1 500 TPC 21. Slew Rate vs. Capacitive Load TPC 20. Settling Time vs. Step Size 100 5V 100 200 300 400 CAPACITIVE LOAD – pF 50mV 100nS TPC 24. Small Signal Response RL =2 kΩ, VS = ± 15 V, AV = +1 10.0 V/DIV 2.5 KHz BW: 15.0 MHz TPC 25. OP285 Voltage Noise Density vs. Frequency VS = ± 15 V, AV = 1000 –6– REV. A OP285 APPLICATIONS Short-Circuit Protection The OP285 has been designed with inherent short-circuit protection to ground. An internal 30 Ω resistor, in series with the output, limits the output current at room temperature to ISC+ = 40 mA and ISC- = –90 mA, typically, with ± 15 V supplies. applications, the fix is a simple one and is illustrated in Figure 3. A 3.92 kΩ resistor in series with the noninverting input of the OP285 cures the problem. RFB* – However, shorts to either supply may destroy the device when excessive voltages or current are applied. If it is possible for a user to short an output to a supply, for safe operation, the output current of the OP285 should be design-limited to ± 30 mA, as shown in Figure 1. + RS 3.92k Figure 3. Output Voltage Phase Reversal Fix FEEDBACK RX 332 A1 + VOUT A1 = 1/2 OP285 Figure 1. Recommended Output Short-Circuit Protection Input Over Current Protection The maximum input differential voltage that can be applied to the OP285 is determined by a pair of internal Zener diodes connected across the inputs. They limit the maximum differential input voltage to ± 7.5 V. This is to prevent emitter-base junction breakdown from occurring in the input stage of the OP285 when very large differential voltages are applied. However, in order to preserve the OP285’s low input noise voltage, internal resistance in series with the inputs were not used to limit the current in the clamp diodes. In small-signal applications, this is not an issue; however, in industrial applications, where large differential voltages can be inadvertently applied to the device, large transient currents can be made to flow through these diodes. The diodes have been designed to carry a current of ± 8 mA; and, in applications where the OP285’s differential voltage were to exceed ± 7.5 V, the resistor values shown in Figure 2 safely limit the diode current to ± 8 mA. 909 – A1 909 + A1 = 1/2 Figure 2. OP285 Input Over Current Protection Output Voltage Phase Reversal Since the OP285’s input stage combines bipolar transistors for low noise and p-channel JFETs for high speed performance, the output voltage of the OP285 may exhibit phase reversal if either of its inputs exceed its negative common-mode input voltage. This might occur in very severe industrial applications where a sensor or system fault might apply very large voltages on the inputs of the OP285. Even though the input voltage range of the OP285 is ± 10.5 V, an input voltage of approximately –13.5 V will cause output voltage phase reversal. In inverting amplifier configurations, the OP285’s internal 7.5 V input clamping diodes will prevent phase reversal; however, they will not prevent this effect from occurring in noninverting applications. For these REV. A RL 2k *RFB IS OPTIONAL RFB – VOUT VIN Overload or Overdrive Recovery Overload or overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output voltage from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. The circuit shown in Figure 4 was used to evaluate the OP285’s overload recovery time. The OP285 takes approximately 1.2 µs to recover to VOUT = +10 V and approximately 1.5 µs to recover to VOUT = –10 V. R1 1k R2 10k 2 3 VIN 4V p-p @100 Hz A1 RS 909 VOUT 1 RL 2.43k A1 = 1/2 OP285 Figure 4. Overload Recovery Time Test Circuit Driving the Analog Input of an A/D Converter Settling characteristics of operational amplifiers also include the amplifier’s ability to recover, i.e., settle, from a transient output current load condition. When driving the input of an A/D converter, especially successive-approximation converters, the amplifier must maintain a constant output voltage under dynamically changing load current conditions. In these types of converters, the comparison point is usually diode clamped, but it may deviate several hundred millivolts resulting in high frequency modulation of the A/D input current. Amplifiers that exhibit high closed-loop output impedances and/or low unity-gain crossover frequencies recover very slowly from output load current transients. This slow recovery leads to linearity errors or missing codes because of errors in the instantaneous input voltage. Therefore, the amplifier chosen for this type of application should exhibit low output impedance and high unity-gain bandwidth so that its output has had a chance to settle to its nominal value before the converter makes its comparison. The circuit in Figure 5 illustrates a settling measurement circuit for evaluating the recovery time of an amplifier from an output load current transient. The amplifier is configured as a follower with a very high speed current generator connected to its output. In this test, a 1 mA transient current was used. As shown in Figure 6, the OP285 exhibits an extremely fast recovery time of 139 ns to 0.01%. Because of its high gain-bandwidth product, high open-loop gain, and low output impedance, the OP285 is ideally suited to drive high speed A/D converters. –7– OP285 Measuring Settling Time +15V 0.1F 3 1/2 1 OP285 2 The design of OP285 combines high slew rate and wide gainbandwidth product to produce a fast-settling (ts < l µs) amplifier for 8- and 12-bit applications. The test circuit designed to measure the settling time of the OP285 is shown in Figure 7. This test method has advantages over false-sum node techniques in that the actual output of the amplifier is measured, instead of an error voltage at the sum node. Common-mode settling effects are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. Of course, a reasonably flat-top pulse is required as the stimulus. 8 + + 7A13 PLUG-IN – 7A13 PLUG-IN 0.1F – 4 * –15V 1k 300pF 15V TTL INPUT |VREF| 1k IOUT 2N3904 1.5k 2N2907 1N4148 The output waveform of the OP285 under test is clamped by Schottky diodes and buffered by the JFET source follower. The signal is amplified by a factor of ten by the OP260 and then Schottky-clamped at the output to prevent overloading the oscilloscope’s input amplifier. The OP41 is configured as a fast integrator which provides overall dc offset nulling. 10F + 1k 1.8k 220 15V 0.47F 0.1F High Speed Operation 0.01F *NOTE DECOUPLE CLOSE TOGETHER ON GROUND PLAN WITH SHORT LEAD LENGTHS. As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Recommended circuit configurations for inverting and noninverting applications are shown in Figures 8 and Figure 9. VREF (–1V) Figure 5. Transient Output Load Current Test Fixture +15V 10F + A1 1,2 V T 138.9NS 0.1F 100 TTL CTRL (5V/ DIV) 90 2 – VOUT (2MV/ DIV) 8 1 1/2 10V VIN 10 OP285 3 + 4 0% 5V 2MV VOUT RL 15k 0.1F 50NS 10F Figure 6. OP285’s Output Load Current Recovery Time –15V Figure 8. Unity Gain Follower 16–20V – + +15V 1k OUTPUT (TO SCOPE) 0.1F V+ DUT V– D3 RL 1k D1 2N4416 1/2 OP260AJ D2 1F 0.1F + D4 – 16–20V RF 2k 10k RG 222 10k IC2 5V 2N2222A 750 1N4148 15k SCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ IC2 IS PMI OP41EJ –15V Figure 7. OP285’s Settling Time Test Fixture –8– REV. A OP285 +15V 10F + R3 2k 0.1F 2 R9 50 1 10pF VIN VO1 3 A2 R11 1k 4.99k R1 2k 4.99k 2 – 8 1/2 VIN 1 OP285 3 + 4 3 VOUT 2 A1 R4 2k VO2 – VO1 = VIN 1 P1 10k 2k R5 2k 2.49k 0.1F R7 2k R2 2k R6 2k 6 7 10F + 5 R12 1k R10 50 A3 VO2 R8 2k –15V A1 = 1/2OP285 A2, A3 = 1/2 OP285 GAIN = SET R2, R4, R5 = R1 AND R, R7, R8 = R2 Figure 9. Unity-Gain Inverter In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance (R S and C S) and the OP285’s input capacitance (CIN), as shown in Figure 10. With RS and RF in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor, CFB, in parallel with RFB eliminates this problem. By setting RS (CS + CIN) = RFBCFB, the effect of the feedback pole is completely removed. CFB RFB VOUT RS CS CIN Figure 11. High-Speed, Low-Noise Differential Line Driver Low Phase Error Amplifier The simple amplifier configuration of Figure 12 uses the OP285 and resistors to reduce phase error substantially over a wide frequency range when compared to conventional amplifier designs. This technique relies on the matched frequency characteristics of the two amplifiers in the OP285. Each amplifier in the circuit has the same feedback network which produces a circuit gain of 10. Since the two amplifiers are set to the same gain and are matched due to the monolithic construction of the OP285, they will exhibit identical frequency response. Recall from feedback theory that a pole of a feedback network becomes a zero in the loop gain response. By using this technique, the dominant pole of the amplifier in the feedback loop compensates for the dominant pole of the main amplifier, R2 4.99k Figure 10. Compensating the Feedback Pole R1 549 2 3 High-Speed, Low-Noise Differential Line Driver The circuit of Figure 11 is a unique line driver widely used in industrial applications. With ± 18 V supplies, the line driver can deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The high slew rate and wide bandwidth of the OP285 combine to yield a full power bandwidth of 130 kHz while the low noise front end produces a referred-to-input noise voltage spectral density of 10 nV/√Hz. The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set to noninverting, inverting, or differential operation. REV. A A1 1 R5 549 6 5 VIN R3 499 7 A2 R4 4.99 VOUT A1, A2 = 1/2 OP285 Figure 12. Cancellation of A2’s Dominant Pole by A1 –9– OP285 thereby reducing phase error dramatically. This is shown in Figure 13 where the 10x composite amplifier’s phase response exhibits less than 1.5° phase shift through 500 kHz. On the other hand, the single gain stage amplifier exhibits 25° of phase shift over the same frequency range. An additional benefit of the low phase error configuration is constant group delay, by virtue of constant phase shift at all frequencies below 500 kHz. Although this technique is valid for minimum circuit gains of 10, actual closed-loop magnitude response must be optimized for the amplifier chosen. LOW PHASE ERROR AMPLIFIER RESPONSE 0 –5 PHASE – Degrees –10 –15 A Low Noise, High Speed Instrumentation Amplifier A high speed, low noise instrumentation amplifier, constructed with a single OP285, is illustrated in Figure 15. The circuit exhibits less than 1.2 µV p-p noise (RTI) in the 0.1 Hz to 10 Hz band and an input noise voltage spectral density of 9 nV/√Hz (1 kHz) at a gain of 1000. The gain of the amplifier is easily set by RG according to the formula: VOUT 9.98 kΩ = +2 VIN RG The advantages of a two op amp instrumentation amplifier based on a dual op amp is that the errors in the individual amplifiers tend to cancel one another. For example, the circuit’s input offset voltage is determined by the input offset voltage matching of the OP285, which is typically less than 250 µV. + VIN – SINGLE STAGE AMPLIFIER RESPONSE –20 5 3 2 A1 –25 1 C1 5pF–40pF –35 –40 DC CMRR TRIM –45 10k 100k START 10,000.000Hz 1M 10M STOP 10,000,000.000Hz R1 4.99k VIN1 R1 2k VIN2 3 A1 R5 50 R4 2k 1 5 7 A2 RG A1, A2 = 1/2 OP285 GAIN = 9.98k +2 GAIN 2 10 100 1000 RG() OPEN 1.24k 102 10 Figure 15. A High-Speed Instrumentation Amplifier Common-mode rejection of the circuit is limited by the matching of resistors R1 to R4. For good common-mode rejection, these resistors ought to be matched to better than 1%. The circuit was constructed with 1% resistors and included potentiometer P1 for trimming the CMRR and a capacitor C1 for trimming the CMRR. With these two trims, the circuit’s common-mode rejection was better than 95 dB at 60 Hz and better than 65 dB at 10 kHz. For the best common-mode rejection performance, use a matched (better than 0.1%) thin-film resistor network for R1 through R4 and use the variable capacitor to optimize the circuit’s CMR. The instrumentation amplifier exhibits very wide small- and large-signal bandwidths regardless of the gain setting, as shown in the table. Because of its low noise, wide gain-bandwidth product, and high slew rate, the OP285 is ideally suited for high speed signal conditioning applications. R2 2k 2 R3 2k VOUT RQ P1 500 For a more detailed treatment on the design of low phase error amplifiers, see Application Note AN-107. A fast, 30 mA current source, illustrated in Figure 14, takes advantage of the OP285’s speed and high output current drive. This is a variation of the Howland current source where a second amplifier, A2, is used to increase load current accuracy and output voltage compliance. With supply voltages of ± 15 V, the output voltage compliance of the current pump is ± 8 V. To keep the output resistance in the MΩ range requires that 0.1% or better resistors be used in the circuit. The gain of the current pump can be easily changed according to the equations shown in the diagram. 7 R4 4.99k R2 4.99 Figure 13. Phase Error Comparison Fast Current Pump A2 R3 4.99k AC CMRR TRIM –30 6 6 – V IN1 VIN V IOUT = IN2 = R5 R5 IOUT = (MAX) = 30mA A1, A2 = 1/2 OP285 GAIN = R2 , R4 = R2, R3 = R1 R1 Figure 14. A Fast Current Pump Circuit Gain 2 10 100 1000 –10– RG () Open 1.24 k 102 10 Circuit Bandwidth VOUT = 100 mV p-p VOUT = 20 V p-p 5 MHz 1 MHz 90 kHz 10 kHz 780 kHz 460 kHz 85 kHz 10 kHz REV. A OP285 R1 95.3k 2 VIN 3 1 A1 C1 2200pF R6 4.12k R2 787 C2 2200pF 5 C4 2200pF 5 6 7 A3 R3 1.82k 1 R9 1k 2 A2 3 6 R7 100k 7 A4 VOUT R8 1k C3 2200pF R4 1.87k A1, A4 = 1/2 OP285 A2, A3 = 1/2 OP285 R5 1.82k Figure 16. A 3-Pole, 40 kHz Low-Pass Filter A 3-Pole, 40 kHz Low-Pass Filter Driving Capacitive Loads The OP285 was designed to drive both resistive loads to 600 Ω and capacitive loads of over 1000 pF and maintain stability. While there is a degradation in bandwidth when driving capacitive loads, the designer need not worry about device stability. The graph in Figure 18 shows the 0 dB bandwidth of the OP285 with capacitive loads from 10 pF to 1000 pF. 10 9 8 BANDWIDTH – MHz The closely matched and uniform ac characteristics of the OP285 make it ideal for use in GIC (Generalized Impedance Converter) and FDNR (Frequency Dependent Negative Resistor) filter applications. The circuit in Figure 16 illustrates a linear-phase, 3-pole, 40 kHz low-pass filter using an OP285 as an inductance simulator (gyrator). The circuit uses one OP285 (A2 and A3) for the FDNR and one OP285 (Al and A4) as an input buffer and bias current source for A3. Amplifier A4 is configured in a gain of 2 to set the pass band magnitude response to 0 dB. The benefits of this filter topology over classical approaches are that the op amp used in the FDNR is not in the signal path and that the filter’s performance is relatively insensitive to component variations. Also, the configuration is such that large signal levels can be handled without overloading any of the filter’s internal nodes. As shown in Figure 17, the OP285’s symmetric slew rate and low distortion produce a clean, well-behaved transient response. 7 6 5 4 3 2 1 100 90 0 VOUT 10V p-p 10kHz 200 400 600 CLOAD – pF 800 Figure 18. Bandwidth vs. CLOAD 10 0% SCALE: VERTICAL – 2V/ DIV HORIZONTAL – 10S/ DIV Figure 17. Low-Pass Filter Transient Response REV. A 0 –11– 1000 OP285 OP285 SPICE Model * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * * .SUBCKT OP285 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHZ * R3 5 51 2.188 R4 6 51 2.188 CIN 1 2 1.5E-12 C2 56 364E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) 26 28 35E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 74 1.672 R6 84 1.672 D1 2 36 DZ D2 1 36 DZ EN 31 100 1 GN1 0 2 13 0 1 GN20 1 16 0 1 * EREF 98 0 28 0 1 EP 97 0 99 0 l EM 510 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 CN1 13 0 7.53E-3 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC2 CN2 16 0 7.53E-3 * * GAIN STAGE & DOMINANT POLE AT 32 HZ * R7 18 98 1.09E6 C3 18 98 4.55E-9 G1 98 18 5 6 4.57E-1 V2 97 19 1.4 V3 20 51 1.4 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHz/2.7MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100 MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHZ * R11 24 98 l C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ * R12 25 26 1E6 C7 25 26 1.59E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506 * * POLE AT 100 MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * Rl5 28 99 100E3 R16 28 50 100E3 C9 28 50 1 E-6 ISY 99 50 1.85E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF = 5E5) .MODEL DX D(IS = lE-12) .MODEL DY D(IS = lE-15 BV = 50) .MODEL DZ D(IS = lE-15 BV = 7.0) .MODEL DEN D(IS = lE-12 RS = 4.35K KF = 1.95E-15 AF = l) .MODEL DIN D(IS = lE-12 RS = 77.3E-6 KF = 3.38E-15 AF = 1) .ENDS OP-285 –12– REV. A OP285 97 EP I1 4 –IN R5 R6 7 8 9 2 Q1 CIN VN1 D1 IOS EN 1 12 3 EOS VN3 DN1 36 D2 +IN 35 15 Q2 10 13 DN2 DN4 VN2 DN5 16 CN1 CN2 DN6 VN4 VN6 11 5 VN5 DN3 14 17 6 C2 R3 R4 EM Figure 19a. Spice Diagram 97 V2 C7 19 D3 21 24 23 25 R12 26 R9 G1 R7 C3 G2 G3 R8 R10 C5 G4 C6 R11 E2 R13 C4 D4 20 V3 51 Figure 19b. Spice Diagram 99 D8 D7 R15 G8 D5 28 V4 30 F1 27 D6 G5 R14 C8 L2 29 F2 32 R16 C9 33 D9 G7 50 Figure 19c. Spice Diagram –13– G3 D10 G6 34 OUTPUT V5 31 98 REV. A R17 ISY R18 OP285 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead PDIP Package (N-8) 8 5 0.280 (7.11) 0.240 (6.10) 4 1 0.070 (1.77) 0.045 (1.15) 0.430 (10.92) 0.348 (8.84) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.150 (3.81) MIN 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0 - 15 8-Lead SOIC Package (R-8) 5 8 0.1574 (4.00) 0.1497 (3.80) PIN 1 4 1 0-8 0.2440 (6.20) 0.2284 (5.80) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25) × 45 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) SEE DETAIL ABOVE SEATING PLANE –14– REV. A OP285 Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 REV. A –15– –16– PRINTED IN U.S.A. C00306–0–1/02(A)