Philips Semiconductors Objective specification PowerMOS transistor Isolated version of PHP4N50E GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a full pack, plastic envelope featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT186A PIN PHX4N50E QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance PIN CONFIGURATION MAX. UNIT 500 2.9 30 1.5 V A W Ω SYMBOL DESCRIPTION d case 1 gate 2 drain 3 source g case isolated 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR ±VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) RGS = 20 kΩ IDM Drain current (pulse peak value) Source-drain diode current (DC) Source-drain diode current (pulse peak value) Total power dissipation Storage temperature Junction temperature IDR IDRM Ptot Tstg Tj MIN. MAX. UNIT Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C - 500 500 30 2.9 1.8 11.6 V V V A A A Ths = 25 ˚C - 2.9 A Ths = 25 ˚C - 11.6 A Ths = 25 ˚C -55 - 30 150 150 W ˚C ˚C MIN. MAX. UNIT - 280 44 7.4 mJ mJ mJ AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS WDSR1 CONDITIONS Drain-source non-repetitive ID = 5.3 A; VDD ≤ 50 V; VGS = 10 V; unclamped inductive turn-off RGS = 50 Ω energy Tj = 25˚C prior to surge Tj = 100˚C prior to surge Drain-source repetitive ID = 5.3 A; VDD ≤ 50 V; VGS = 10 V; unclamped inductive turn-off RGS = 50 Ω; Tj ≤ 150 ˚C energy Pulse width and frequency limited by Tj(max) November 1996 1 Rev 1.000 Philips Semiconductors Objective specification PowerMOS transistor PHX4N50E ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65% ; clean and dustfree Cisol Capacitance from T2 to external f = 1 MHz heatsink MIN. TYP. - MAX. UNIT 2500 V - 10 - pF MIN. TYP. MAX. UNIT - - 4.1 K/W - 55 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Thermal resistance junction to ambient with heatsink compound Rth j-a STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Drain-source leakage current VGS = 0 V; ID = 0.25 mA 500 - - V VDS = VGS; ID = 0.25 mA VDS = 500 V; VGS = 0 V; Tj = 25 ˚C VDS = 400 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V VGS = 10 V; ID = 2.65 A 2.0 - 3.0 10 0.1 10 1.3 4.0 100 1.0 100 1.5 V µA mA nA Ω - 1.1 1.4 V VGS(TO) IDSS IGSS RDS(ON) VSD Gate-source leakage current Drain-source on-state resistance Source-drain diode forward voltage November 1996 IF = 5.3 A ;VGS = 0 V 2 Rev 1.000 Philips Semiconductors Objective specification PowerMOS transistor PHX4N50E DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gfs Forward transconductance VDS = 15 V; ID = 2.65 A 1.5 2.5 - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 750 90 40 1000 140 70 pF pF pF Qg(tot) Qgs Qgd Total gate charge Gate to source charge Gate to drain (Miller) charge VGS = 10 V; ID = 5.3 A; VDS = 400 V - 35 4 16 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 2.6 A; VGS = 10 V; RGS = 50 Ω; RGEN = 50 Ω - 10 45 100 40 45 60 140 65 ns ns ns ns trr Source-drain diode reverse recovery time Source-drain diode reverse recovery charge IF = 5.3 A; -dIF/dt = 100 A/µs; - 1200 - ns VGS = 0 V; VR = 100 V - 6 - µC Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH Qrr November 1996 3 Rev 1.000 Philips Semiconductors Objective specification PowerMOS transistor PHX4N50E MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 19 max. max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.1. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 1996 4 Rev 1.000 Philips Semiconductors Objective specification PowerMOS transistor PHX4N50E DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1996 5 Rev 1.000