MOTOROLA Order this document by MJE13007/D SEMICONDUCTOR TECHNICAL DATA MJE13007 MJF13007 SWITCHMODE NPN Bipolar Power Transistor For Switching Power Supply Applications The MJE/MJF13007 is designed for high–voltage, high–speed power switching inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V switchmode applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits. • • • • • • POWER TRANSISTOR 8.0 AMPERES 400 VOLTS 80/40 WATTS VCEO(sus) 400 V Reverse Bias SOA with Inductive Loads @ TC = 100°C 700 V Blocking Capability SOA and Switching Applications Information Two Package Choices: Standard TO–220 or Isolated TO–220 MJF13007 is UL Recognized to 3500 VRMS, File #E69369 MAXIMUM RATINGS Rating Symbol MJE13007 MJF13007 Unit Collector–Emitter Sustaining Voltage VCEO 400 Vdc Collector–Emitter Breakdown Voltage VCES 700 Vdc Emitter–Base Voltage VEBO 9.0 Vdc Collector Current — Continuous Collector Current — Peak (1) IC ICM 8.0 16 Adc Base Current — Continuous Base Current — Peak (1) IB IBM 4.0 8.0 Adc Emitter Current — Continuous Emitter Current — Peak (1) IE IEM 12 24 Adc RMS Isolation Voltage (for 1 sec, R.H. < 30%, TA = 25°C) Test No. 1 Per Fig. 15 Test No. 2 Per Fig. 16 Test No. 3 Per Fig. 17 Proper strike and creepage distance must be provided Total Device Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature VISOL V PD TJ, Tstg — — — 4500 3500 1500 80 0.64 40* 0.32 – 65 to 150 CASE 221A–06 TO–220AB MJE13007 Watts W/°C °C THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case — Junction to Ambient Maximum Lead Temperature for Soldering Purposes: 1/8″ from Case for 5 Seconds RθJC RθJA °1.56° °62.5° TL °3.12° °62.5° 260 °C/W °C CASE 221D–02 ISOLATED TO–220 TYPE UL RECOGNIZED MJF13007 (1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle ≤ 10%. *Measurement made with thermocouple contacting the bottom insulated mountign surface of the *package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied *at a mounting torque of 6 to 8•lbs. Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Designer’s and SWITCHMODE are trademarks of Motorola, Inc. Motorola, Inc. 1995 Motorola Bipolar Power Transistor Device Data 1 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit VCEO(sus) 400 — — Vdc — — — — 0.1 1.0 — — 100 *OFF CHARACTERISTICS Collector–Emitter Sustaining Voltage (IC = 10 mA, IB = 0) Collector Cutoff Current (VCES = 700 Vdc) (VCES = 700 Vdc, TC = 125°C) ICES Emitter Cutoff Current (VEB = 9.0 Vdc, IC = 0) IEBO mAdc µAdc SECOND BREAKDOWN Second Breakdown Collector Current with Base Forward Biased Clamped Inductive SOA with Base Reverse Biased IS/b See Figure 6 — See Figure 7 *ON CHARACTERISTICS DC Current Gain (IC = 2.0 Adc, VCE = 5.0 Vdc) (IC = 5.0 Adc, VCE = 5.0 Vdc) hFE — 8.0 5.0 — — 40 30 — — — — — — — — 1.0 2.0 3.0 3.0 — — — — — — 1.2 1.6 1.5 fT 4.0 14 — MHz Cob — 80 — pF Cc–hs — 3.0 — pF td — 0.025 0.1 µs tr — 0.5 1.5 ts — 1.8 3.0 tf — 0.23 0.7 Collector–Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 8.0 Adc, IB = 2.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) VCE(sat) Base–Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) VBE(sat) Vdc Vdc DYNAMIC CHARACTERISTICS Current–Gain — Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, f = 1.0 MHz) Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz) Collector to Heatsink Capacitance, MJF13007 SWITCHING CHARACTERISTICS Resistive Load (Table 1) Delay Time Rise Time Storage Time (VCC = 125 Vdc, IC = 5.0 A, IB1 = IB2 = 1.0 A, tp = 25 µs, Duty Cycle ≤ 1.0%) Fall Time Inductive Load, Clamped (Table 1) Voltage Storage Time VCC = 15 Vdc, IC = 5.0 A Vclamp = 300 Vdc TC = 25°C TC = 100°C tsv — — 1.2 1.6 2.0 3.0 µs Crossover Time IB(on) = 1.0 A, IB(off) = 2.5 A LC = 200 µH TC = 25°C TC = 100°C tc — — 0.15 0.21 0.30 0.50 µs TC = 25°C TC = 100°C tfi — — 0.04 0.10 0.12 0.20 µs Fall Time * Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. 2 Motorola Bipolar Power Transistor Device Data VCE(sat), COLLECTOR–EMITTER SATURATION VOLTAGE (VOLTS) VBE(sat), BASE–EMITTER SATURATION VOLTAGE (VOLTS) 1.4 IC/IB = 5 1.2 1 0.8 TC = – 40°C 25°C 0.6 100°C 0.4 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10 5 IC/IB = 5 2 1 0.5 0.2 TC = – 40°C 0.1 25°C 0.05 0.02 0.01 0.01 0.02 100°C 0.05 0.1 0.2 0.5 1 2 5 10 IC, COLLECTOR CURRENT (AMPS) Figure 1. Base–Emitter Saturation Voltage Figure 2. Collector–Emitter Saturation Voltage VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (AMPS) 3 TJ = 25°C 2.5 2 1.5 IC = 8 A IC = 5 A 1 IC = 3 A IC = 1 A 0.5 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 5 10 IB, BASE CURRENT (AMPS) Figure 3. Collector Saturation Region 100 10000 C, CAPACITANCE (pF) hFE , DC CURRENT GAIN 25°C 10 40°C VCE = 5 V 1 0.01 TJ = 25°C Cib TJ = 100°C 0.1 1 10 1000 Cob 100 10 0.1 1 10 100 IC, COLLECTOR CURRENT (AMPS) VR, REVERSE VOLTAGE (VOLTS) Figure 4. DC Current Gain Figure 5. Capacitance Motorola Bipolar Power Transistor Device Data 1000 3 10 Extended SOA @ 1 µs, 10 µs 20 10 5 1 µs 10 µs TC = 25°C 2 1 0.5 DC 1 ms 5 ms 0.2 0.1 0.05 0.02 0.01 IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 100 50 BONDING WIRE LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT CURVES APPLY BELOW RATED VCEO 10 8 4 1000 SECOND BREAKDOWN DERATING POWER DERATING FACTOR 0.6 THERMAL DERATING 0.2 40 60 80 100 120 140 160 TC, CASE TEMPERATURE (°C) Figure 8. Forward Bias Power Derating r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0V –2 V 100 200 300 400 500 600 700 800 VCEV, COLLECTOR–EMITTER CLAMP VOLTAGE (VOLTS) 0 Figure 7. Maximum Reverse Bias Switching Safe Operating Area 1 0 20 –5 V 2 Figure 6. Maximum Forward Bias Safe Operating Area 0.4 VBE(off) 0 20 30 50 70 100 200 300 500 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) 0.8 TC ≤ 100°C GAIN ≥ 4 LC = 500 µH 6 There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC — VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 6 is based on TC = 25°C; TJ(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when T C ≥ 25°C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 6 may be found at any case temperature by using the appropriate curve on Figure 8. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 7) is discussed in the applications information section. 1 0.7 0.5 D = 0.5 D = 0.2 0.2 D = 0.1 0.1 0.07 0.05 0.02 D = 0.05 t1 D = 0.02 t2 DUTY CYCLE, D = t1/t2 D = 0.01 0.01 0.01 SINGLE PULSE 0.02 RθJC(t) = r(t) RθJC RθJC = 1.56°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) P(pk) 0.05 0.1 0.2 0.5 1 2 5 t, TIME (msec) 10 20 50 100 200 500 Figure 9. Typical Thermal Response for MJE13007 4 Motorola Bipolar Power Transistor Device Data 10 k r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 0.5 0.3 D = 0.5 D = 0.2 0.2 D = 0.1 0.1 0.05 0.03 P(pk) t1 D = 0.05 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.02 0.01 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 t, TIME (msec) RθJC(t) = r(t) RθJC RθJC = 3.12°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1K 2K 3K 5K 10K 20K 30K 50K 100K Figure 10. Typical Thermal Response for MJF13007 SPECIFICATION INFORMATION FOR SWITCHMODE APPLICATIONS INTRODUCTION The primary considerations when selecting a power transistor for SWITCHMODE applications are voltage and current ratings, switching speed, and energy handling capability. In this section, these specifications will be discussed and related to the circuit examples illustrated in Table 2.(1) VOLTAGE REQUIREMENTS Both blocking voltage and sustaining voltage are important in SWITCHMODE applications. Circuits B and C in Table 2 illustrate applications that require high blocking voltage capability. In both circuits the switching transistor is subjected to voltages substantially higher than VCC after the device is completely off (see load line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking capability at this point depends on the base to emitter conditions and the device junction temperature. Since the highest device capability occurs when the base to emitter junction is reverse biased (VCEV), this is the recommended and specified use condition. Maximum ICEV at rated VCEV is specified at a relatively low reverse bias (1.5 Volts) both at Motorola Bipolar Power Transistor Device Data 25°C and 100°C. Increasing the reverse bias will give some improvement in device blocking capability. The sustaining or active region voltage requirements in switching applications occur during turn–on and turn–off. If the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn–on and the pulsed forward bias SOA curves (Figure 6) are the proper design limits. For inductive loads, high voltage and current must be sustained simultaneously during turn–off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as a Reverse Bias Safe Operating Area (Figure 7) which represents voltage–current conditions that can be sustained during reverse biased turn–off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. (1) For detailed information on specific switching applications, see (1) Motorola Application Note AN719, AN873, AN875, AN951. 5 Table 1. Test Conditions For Dynamic Performance RESISTIVE SWITCHING REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING VCC TEST CIRCUITS +15 V 150 Ω 3W 1 µF 100 Ω 3W MTP8P10 MTP8P10 100 µF MUR105 +10 V RC RB1 IC MJE210 A RB2 50 Ω IB TUT RB SCOPE 5.1 k D1 VCE TUT 51 MTP12N10 –4V Voff 1 µF CIRCUIT VALUES V(BR)CEO(sus) TEST WAVEFORMS Vclamp = 300 Vdc IB 150 Ω 3W 500 µF +125 V MUR8100E MPF930 MPF930 COMMON L = 10 mH RB2 = 8 VCC = 20 Volts IC(pk) = 100 mA tf CLAMPED IC Inductive Switching RBSOA L = 200 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1 L = 500 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1 tf UNCLAMPED ≈ t2 ICM t1 tf t2 ≈ VCE VCEM Vclamp t t2 VCC = 125 V RC = 25 Ω D1 = 1N5820 OR EQUIV. TYPICAL WAVEFORMS t1 ADJUSTED TO OBTAIN IC Lcoil (ICM) t1 ≈ VCC IB1 TEST EQUIPMENT SCOPE — TEKTRONIX 475 OR EQUIVALENT In the four application examples (Table 2) load lines are shown in relation to the pulsed forward and reverse biased SOA curves. In circuits A and D, inductive reactance is clamped by the diodes shown. In circuits B and C the voltage is clamped by the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. A snubber network or an additional clamp may be required to keep the turn–off load line within the Reverse Bias SOA curve. Load lines that fall within the pulsed forward biased SOA curve during turn–on and within the reverse bias SOA curve during turn–off are considered safe, with the following assumptions: (1) The device thermal limitations are not exceeded. (2) The turn–on time does not exceed 10 µs (see standard pulsed forward SOA curves in Figure 6). (3) The base drive conditions are within the specified limits shown on the Reverse Bias SOA curve (Figure 7). CURRENT REQUIREMENTS An efficient switching transistor must operate at the required current level with good fall time, high energy handling 0 VCE Lcoil (ICM) Vclamp VOLTAGE REQUIREMENTS (continued) 25 µs +11 V VCE PEAK t TIME 6 L IB IB2 9V tr, tf < 10 ns DUTY CYCLE = 1.0% RB AND RC ADJUSTED FOR DESIRED IB AND IC capability and low saturation voltage. On this data sheet, these parameters have been specified at 5.0 amperes which represents typical design conditions for these devices. The current drive requirements are usually dictated by the VCE(sat) specification because the maximum saturation voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage. SWITCHING REQUIREMENTS In many switching applications, a major portion of the transistor power dissipation occurs during the fall time (tfi). For this reason considerable effort is usually devoted to reducing the fall time. The recommended way to accomplish this is to reverse bias the base–emitter junction during turn– off. The reverse biased switching characteristics for inductive loads are shown in Figures 13 and 14 and resistive loads in Figures 11 and 12. Usually the inductive load components will be the dominant factor in SWITCHMODE applications and the inductive switching data will more closely represent the device performance in actual application. The inductive switching characteristics are derived from the same circuit used to specify the reverse biased SOA curves, (see Table 1) providing correlation between test procedures and actual use conditions. Motorola Bipolar Power Transistor Device Data SWITCHING TIME NOTES In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and any coil driver, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp trv = Voltage Rise Time, 10–90% Vclamp tfi = Current Fall Time, 90–10% IC tti = Current Tail, 10–2% IC tc = Crossover Time, 10% Vclamp to 10% IC An enlarged portion of the turn–off waveforms is shown in Figure 13 to aid in the visual identity of these terms. For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN222A: PSWT = 1/2 VCCIC(tc) f Typical inductive switching times are shown in Figure 14. In general, trv + tfi ≅ tc. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at 25°C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a “SWITCHMODE” transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100°C. SWITCHING PERFORMANCE 10000 7000 5000 VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25°C PW = 25 µs 1000 tr VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25°C PW = 25 µs ts 2000 t, TIME (ns) t, TIME (ns) 10000 1000 700 500 100 tf 200 td 10 100 1 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) 7 8 9 10 1 Figure 11. Turn–On Time (Resistive Load) 7 8 9 10 Figure 12. Turn–Off Time (Resistive Load) 10000 IC 90% Vclamp tsv 90% IC tfi trv Vclamp 2000 10% Vclamp 90% IB1 10% IC t, TIME (ns) Vclamp 5000 tti tc IB 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) 2% IC 1000 500 IC/IB = 5 IB(off) = IC/2 Vclamp = 300 V LC = 200 µH VCC = 15 V TJ = 25°C tsv tc 200 100 tfi 50 20 TIME 10 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 IC, COLLECTOR CURRENT (AMP) Figure 13. Inductive Switching Measurements Motorola Bipolar Power Transistor Device Data Figure 14. Typical Inductive Switching Times 7 Table 2. Applications Examples of Switching Circuits CIRCUIT LOAD LINE DIAGRAMS SERIES SWITCHING REGULATOR TURN–ON (FORWARD BIAS) SOA ton ≤ 10 µs DUTY CYCLE ≤ 10% VO VCC COLLECTOR CURRENT 16 A A TIME DIAGRAMS TC = 100°C PD = 3200 W 2 300 V IC ton TURN–OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V DUTY CYCLE ≤ 10% 8A TURN–ON VCE 400 V 1 VCC 700 V 1 VCC COLLECTOR VOLTAGE Notes: FLYBACK INVERTER VO N COLLECTOR CURRENT VCC B TURN–ON (FORWARD BIAS) SOA ton ≤ 10 µs DUTY CYCLE ≤ 10% 16 A 300 V TURN–ON VCC + N (Vo) + LEAKAGE SPIKE VCE VCC + N (Vo) VCC 400 V 1 700 V 1 COLLECTOR VOLTAGE VCC + N (Vo) t 16 A TURN–ON (FORWARD BIAS) SOA ton ≤ 10 µs TC = 100°C PD = 3200 W 2 IC COLLECTOR CURRENT DUTY CYCLE ≤ 10% VO t LEAKAGE SPIKE See AN569 for Pulse Power Derating Procedure. 1 VCC DUTY CYCLE ≤ 10% TURN–OFF Notes: C toff ton TURN–OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V 8A + VCC PUSH–PULL INVERTER/CONVERTER IC PD = 3200 W 2 TC = 100°C t TIME See AN569 for Pulse Power Derating Procedure. 1 t TIME TURN–OFF + toff toff ton t TURN–OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V 300 V 8A VCE DUTY CYCLE ≤ 10% TURN–ON 2 VCC VCC + 2 VCC TURN–OFF VCC 400 V 1 COLLECTOR VOLTAGE 700 V 1 t Notes: 1 VCC D SOLENOID 16 A TURN–ON (FORWARD BIAS) SOA ton ≤ 10 µs DUTY CYCLE ≤ 10% TC = 100°C PD = 3200 W 2 COLLECTOR CURRENT SOLENOID DRIVER See AN569 for Pulse Power Derating Procedure. 300 V 8A IC toff TURN–OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V DUTY CYCLE ≤ 10% ton t VCE TURN–OFF VCC TURN–ON + VCC 400 V 1 700 V 1 COLLECTOR VOLTAGE Notes: 1 8 See AN569 for Pulse Power Derating Procedure. Motorola Bipolar Power Transistor Device Data t TEST CONDITIONS FOR ISOLATION TESTS* CLIP MOUNTED FULLY ISOLATED PACKAGE CLIP LEADS HEATSINK MOUNTED FULLY ISOLATED PACKAGE 0.107” MIN MOUNTED FULLY ISOLATED PACKAGE LEADS LEADS HEATSINK HEATSINK 0.107” MIN 0.110” MIN Figure 15. Screw or Clip Mounting Position for Isolation Test Number 1 Figure 16. Clip Mounting Position for Isolation Test Number 2 Figure 17. Screw Mounting Position for Isolation Test Number 3 * Measurement made between leads and heatsink with all leads shorted together MOUNTING INFORMATION 4–40 SCREW CLIP PLAIN WASHER HEATSINK COMPRESSION WASHER HEATSINK NUT Figure 18. Typical Mounting Techniques for Isolated Package Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw torque of 6 to 8 in . lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a constant pressure on the package over time and during large temperature excursions. Destructive laboratory tests show that using a hex head 4–40 screw, without washers, and applying a torque in excess of 20 in . lbs will cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability. Additional tests on slotted 4–40 screws indicate that the screw slot fails between 15 to 20 in . lbs without adversely affecting the package. However, in order to positively ensure the package integrity of the fully isolated device, Motorola does not recommend exceeding 10 in . lbs of mounting torque under any mounting conditions. ** For more information about mounting power semiconductors see Application Note AN1040. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola Bipolar Power Transistor Device Data 9 PACKAGE DIMENSIONS B –T– F SEATING PLANE C T 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. S A Q 1 2 3 H DIM A B C D F G H J K L N Q R S T U V Z U K Z L R V J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 STYLE 1: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 BASE COLLECTOR EMITTER COLLECTOR CASE 221A–06 TO–220AB ISSUE Y –T– –B– F SEATING PLANE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. S Q U DIM A B C D F G H J K L N Q R S U A 1 2 3 H –Y– K G N L D J R 3 PL 0.25 (0.010) M B M Y INCHES MIN MAX 0.621 0.629 0.394 0.402 0.181 0.189 0.026 0.034 0.121 0.129 0.100 BSC 0.123 0.129 0.018 0.025 0.500 0.562 0.045 0.060 0.200 BSC 0.126 0.134 0.107 0.111 0.096 0.104 0.259 0.267 MILLIMETERS MIN MAX 15.78 15.97 10.01 10.21 4.60 4.80 0.67 0.86 3.08 3.27 2.54 BSC 3.13 3.27 0.46 0.64 12.70 14.27 1.14 1.52 5.08 BSC 3.21 3.40 2.72 2.81 2.44 2.64 6.58 6.78 STYLE 2: PIN 1. BASE 2. COLLECTOR 3. EMITTER CASE 221D–02 ISOLATED TO–220 TYPE ISSUE D How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 10 ◊ Motorola Bipolar Power Transistor Device Data *MJE13007/D* MJE13007/D