4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication ADV3002 FEATURES FUNCTIONAL BLOCK DIAGRAM SEL[1:0] TX_EN SERIAL I2C_SDA I2C_SCL I2C_ADDR[1:0] AVCC 2 RESETB CONFIG INTERFACE AVCC AVEE CONTROL LOGIC AVCC LOS IN_x_CLK+ IN_x_CLK– IN_x_DATA2+ IN_x_DATA2– IN_x_DATA1+ IN_x_DATA1– IN_x_DATA0+ IN_x_DATA0– + – + – + – + – + – + – + – + – 4 4 4 4 4 4 4 EQ SWITCH CORE OUT_CLK+ OUT_CLK– OUT_DATA2+ OUT_DATA2– OUT_DATA1+ OUT_DATA1– OUT_DATA0+ OUT_DATA0– TMDS AVCC DDC_xxx_A DDC_xxx_B DDC_xxx_C DDC_xxx_D 2 2 2 2 AVCC 2 SWITCH CORE 3.3V DDC_SCL_COM, DDC_SDA_COM 3.3V CEC_OUT CEC_IN DDC/CEC BIDIRECTIONAL REPLICATOR CONTROL EDID P5V_A P5V_B P5V_C P5V_D 5V COMBINER EDID_ENABLE 2 EDID_SCL, EDID_SDA AMUXVCC EDID EEPROM INTERFACE HPD_A HPD_B HPD_C HPD_D APPLICATIONS Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes HPD CONTROL HOT PLUG DETECT Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADV3002 is a complete HDMI™/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports. 1. The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount Pb-free plastic package and is specified to operate over the 0°C to 85°C temperature range. ADV3002 PARALLEL 07905-001 4 inputs, 1 output HDMI/DVI links ±8 kV ESD protection on input pins HDMI 1.3a receive and transmit compliant Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to 225 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Switchable 50 Ω on-chip input terminations with manual or automatic control on channel switch Equalized inputs with low added jitter compensate for more than 20 meters of HDMI cable at 2.25 Gbps Loss of signal (LOS) detect circuit on TMDS clock Output disable feature for reduced power dissipation Bidirectional DDC buffers (SDA and SCL) EDID replication reduces component count, while enabling simultaneous access to all HDMI sources 5 V combiner provides power to EDID replicator and CEC buffer when local system power is off Bidirectional buffered CEC line with integrated pull-up resistors (26 kΩ) Hot plug detect pulse low on channel switch with programmable pulse width or direct manual control Standards compatible: HDMI, DVI, HDCP, I2C 80-lead, 14 mm × 14 mm LQFP RoHS-compliant package 2. 3. 4. 5. Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than 20 m at data rates up to 2.25 Gbps. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. EDID replication eliminates the need for multiple EDID EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller. 5 V power combiner powers the EDID replicator and CEC buffer when local system power is off. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADV3002 TABLE OF CONTENTS Features .............................................................................................. 1 DDC Buffers................................................................................ 13 Applications ....................................................................................... 1 EDID Replication ....................................................................... 13 General Description ......................................................................... 1 5 V Combiner ............................................................................. 15 Functional Block Diagram .............................................................. 1 CEC Buffer .................................................................................. 15 Product Highlights ........................................................................... 1 Hot Plug Detect Control ........................................................... 15 Revision History ............................................................................... 2 Loss of Signal Detect .................................................................. 16 Specifications..................................................................................... 3 Serial Control Interface ................................................................. 17 TMDS Performance Specifications ............................................ 3 Reset ............................................................................................. 17 Auxiliary Channel Performance Specifications........................ 3 Write Procedure.......................................................................... 17 Power Supply and Control Logic Specifications ...................... 4 Read Procedure........................................................................... 18 Absolute Maximum Ratings............................................................ 5 ADV3002 Register Map ................................................................. 19 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 21 ESD Caution .................................................................................. 5 HDMI Multiplexer for Advanced TV ..................................... 21 Pin Configurations and Function Descriptions ........................... 6 Cable Lengths and Equalization ............................................... 24 Typical Performance Characteristics ............................................. 9 PCB Layout Guidelines.............................................................. 24 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 27 TMDS Input Channels............................................................... 12 Ordering Guide .......................................................................... 27 TMDS Output Channels ........................................................... 12 REVISION HISTORY 12/08—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADV3002 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, data rate = 2.25 Gbps, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. TMDS PERFORMANCE SPECIFICATIONS Table 1. Parameter DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Maximum Clock Rate Bit Error Rate (BER) Added Data Jitter Added Clock Jitter Differential Intrapair Skew Differential Interpair Skew EQUALIZATION PERFORMANCE High Frequency Gain INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/fall time (20% to 80%) TERMINATION Input Termination Resistance Output Termination Resistance LOSS OF SIGNAL (LOS) DETECT Frequency Cutoff Amplitude Threshold Test Conditions/Comments Min NRZ 2.25 225 Typ Max Unit Gbps MHz PRBS 223 − 1 DR ≤ 2.25 Gbps, PRBS 27 − 1 10−9 At output At output 40 1 1 35 ps p-p ps rms ps ps Boost frequency = 1.125 GHz 18 dB Differential 150 AVCC − 800 1200 AVCC mV mV Single-ended high speed channel Single-ended high speed channel DR = 2.25 Gbps AVCC − 200 AVCC − 600 75 AVCC + 10 AVCC − 400 190 mV mV ps Single-ended Single-ended LOS_FC (see Figure 27) Clock rate = 225 MHz, LOS_THR = 00 (see Figure 27) 50 50 Ω Ω 35 MHz mV 5 AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS Table 2. Parameter DDC CHANNELS Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Rise Time Fall Time Leakage CEC CHANNEL Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Output High Voltage, VOH Test Conditions/Comments Min Typ Max Unit 5 15 0.5 IOL = 5 mA 10% to 90%, CLOAD = 50 pF, RPULL-UP = 2 kΩ 90% to 10%, CLOAD = 50 pF, RPULL-UP = 2 kΩ VIN = 5.0 V 0.25 1.45 20 0.4 pF V V V µs ns µA DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 5 15 0.8 0.1 0.6 DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 0.7 × AMUXVCC 250 10 2.0 IOL = 3 mA 2.5 Rev. 0 | Page 3 of 28 pF V V V V ADV3002 Parameter Rise Time Fall Time Pull-Up Resistance Leakage HOT PLUG DETECT Output Low Voltage, VOL 1 Test Conditions/Comments 10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF, RPULL-UP = 3 kΩ 90% to 10%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF, RPULL-UP = 3 kΩ Min Typ 75 Max 250 Unit µs 0.2 50 µs 1.8 kΩ µA 0.4 V 26 Off-leakage test conditions 1 RPU = 800 Ω 0.25 Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to 3.63 V via 26 kΩ ± 5 % resistor with an ammeter in series and with the power mains disabled. POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS Table 3. Parameter POWER SUPPLY AVCC P5V_x AMUXVCC QUIESCENT CURRENT AVCC P5V_x AMUXVCC Test Conditions/Comments Min Typ Max Unit Operating range (3.3 V ± 10%) 3.0 4.7 4.0 3.3 5 5 3.6 5.5 5.5 V V V Outputs disabled Outputs enabled Main power on Main power off Main power on Main power off 40 170 0.5 20 20 0.5 60 150 10 30 30 10 mA mA mA mA mA mA Outputs disabled Outputs enabled 232 661 381 885 mW mW 1.0 V V 0.4 V V Output voltage, total load1 = 50 mA POWER DISSIPATION I2C® AND LOGIC INPUTS2 Input High Voltage, VIH Input Low Voltage, VIL 2 I C AND LOGIC OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL 1 2 2.4 IOH = −2 mA IOL = +2 mA AVCC The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply. The ADV3002 I2C control and logic input pins are listed as control in the Type column in Table 6. I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification. Rev. 0 | Page 4 of 28 ADV3002 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVCC to AVEE P5V_x AMUXVCC Internal Power Dissipation TMDS Single-Ended Input Voltage TMDS Differential Input Voltage Voltage at TMDS Output DDC Input Voltage CEC Input Voltage I2C Logic Input Voltage (EDID_SCL, EDID_SDA, I2C_SCL, I2C_SDA) Parallel Input Voltage (I2C_ADDR[1:0], RESETB) Parallel Input Voltage (SEL[1:0], TX_EN) Storage Temperature Range Operating Temperature Range Junction Temperature ESD Protection (HBM) on HDMI Input Pins ESD Protection (HBM) on All Other Pins Rating 3.7 V 5.8 V AVCC − 0.3 V < AMUXVCC < 5.8 V 1.2 W AVCC − 1.4 V < VIN < AVCC + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE 2.0 V VOUT < 3.7 V AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V AVEE − 0.3 V < VIN < 4.0 V AVEE − 0.3 V < VIN < 4.0 V θJA is specified for the worst-case conditions: a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. θJC is specified for the exposed pad soldered to the circuit board with no airflow. Table 5. Thermal Resistance AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V Package Type 80-Lead LQFP (ST-80-2) AVEE − 0.3V < VIN < AVCC + 0.3 V ESD CAUTION −65°C to +125°C 0°C to +85°C 150°C ±8 kV ±2.5 kV Rev. 0 | Page 5 of 28 θJA 51.3 θJC 15.3 Unit °C/W ADV3002 EDID_SCL EDID_SDA EDID_ENABLE AMUXVCC CEC_OUT CEC_IN DDC_SCL_COM DDC_SDA_COM DDC_SCL_D DDC_SDA_D DDC_SCL_C DDC_SDA_C DDC_SCL_B DDC_SDA_B DDC_SCL_A DDC_SDA_A P5V_D P5V_B P5V_C P5V_A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 PIN 1 60 IN_C_DATA2+ 59 IN_C_DATA2– HPD_B 3 58 HPD_C IN_B_DATA0– 4 57 IN_C_DATA1+ IN_B_DATA0+ 5 56 IN_C_DATA1– HPD_A 6 55 HPD_D IN_B_DATA1– 7 54 IN_C_DATA0+ IN_B_DATA1+ 8 53 IN_C_DATA0– AVCC 9 52 AVCC IN_B_DATA2– 10 51 IN_C_CLK+ IN_B_DATA2+ 11 50 IN_C_CLK– SEL0 12 49 I2C_ADDR0 ADV3002 TOP VIEW (Not to Scale) IN_A_CLK– 13 48 IN_D_DATA2+ IN_A_CLK+ 14 47 IN_D_DATA2– SEL1 15 46 AVEE IN_A_DATA0– 16 45 IN_D_DATA1+ IN_A_DATA0+ 17 44 IN_D_DATA1– AVCC 18 43 AVCC IN_A_DATA1– 19 42 IN_D_DATA0+ IN_A_DATA1+ 20 41 IN_D_DATA0– Figure 2. Pin Configuration Rev. 0 | Page 6 of 28 I2C_SDA I2C_ADDR1 IN_D_CLK+ IN_D_CLK– RESETB OUT_CLK– OUT_CLK+ AVCC OUT_DATA0– OUT_DATA0+ AVEE OUT_DATA1– OUT_DATA1+ I2C_SCL OUT_DATA2– TX_EN OUT_DATA2+ IN_A_DATA2+ AVEE IN_A_DATA2– 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 07905-002 IN_B_CLK– IN_B_CLK+ ADV3002 Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9, 18, 33, 43, 52 10 11 12 13 14 15 16 17 19 20 21, 30, 46 22 23 24 25 26 27 28 29 31 32 34 35 36 37 38 39 40 41 42 44 45 47 48 49 50 51 53 54 55 56 57 58 Mnemonic IN_B_CLK− IN_B_CLK+ HPD_B IN_B_DATA0− IN_B_DATA0+ HPD_A IN_B_DATA1− IN_B_DATA1+ AVCC IN_B_DATA2− IN_B_DATA2+ SEL0 IN_A_CLK− IN_A_CLK+ SEL1 IN_A_DATA0− IN_A_DATA0+ IN_A_DATA1− IN_A_DATA1+ AVEE IN_A_DATA2− IN_A_DATA2+ TX_EN OUT_DATA2+ OUT_DATA2− I2C_SCL OUT_DATA1+ OUT_DATA1− OUT_DATA0+ OUT_DATA0− OUT_CLK+ OUT_CLK− RESETB IN_D_CLK− IN_D_CLK+ I2C_ADDR1 I2C_SDA IN_D_DATA0− IN_D_DATA0+ IN_D_DATA1− IN_D_DATA1+ IN_D_DATA2− IN_D_DATA2+ I2C_ADDR0 IN_C_CLK− IN_C_CLK+ IN_C_DATA0− IN_C_DATA0+ HPD_D IN_C_DATA1− IN_C_DATA1+ HPD_C Type TMDS TMDS HPD TMDS TMDS HPD TMDS TMDS Power TMDS TMDS Control TMDS TMDS Control TMDS TMDS TMDS TMDS Power TMDS TMDS Control TMDS TMDS Control TMDS TMDS TMDS TMDS TMDS TMDS Control TMDS TMDS Control Control TMDS TMDS TMDS TMDS TMDS TMDS Control TMDS TMDS TMDS TMDS HPD TMDS TMDS HPD Description High Speed TMDS Input B Clock Complement. High Speed TMDS Input B Clock. Hot Plug Detect Output B. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Hot Plug Detect Output A. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Positive Analog Supply 3.3 V. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Channel Select Parallel Control LSB. High Speed TMDS Input A Clock Complement. High Speed TMDS Input A Clock. Channel Select Parallel Control MSB. High Speed TMDS Input A Complement. High Speed TMDS Input A Data. High Speed TMDS Input A Data Complement. High Speed TMDS Input A Data. Negative Analog Supply 0.0 V. High Speed TMDS Input A Data Complement. High Speed TMDS Input A Data. TMDS Output Enable Parallel Control. High Speed TMDS Output. High Speed TMDS Output Complement. Serial Control Clock Input. High Speed TMDS Output. High Speed TMDS Output Complement. High Speed TMDS Output. High Speed TMDS Output Complement. High Speed TMDS Output Clock. High Speed TMDS Output Clock Complement. Configuration Registers Reset. Active low. High Speed TMDS Input D Clock Complement. High Speed TMDS Input D Clock. Serial Control External Address MSB. Serial Control Data Input/Output. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. Serial Control External Address LSB. High Speed TMDS Input C Clock Complement. High Speed TMDS Input C Clock. High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. Hot Plug Detect Output D. High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. Hot Plug Detect Output C. Rev. 0 | Page 7 of 28 ADV3002 Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Mnemonic IN_C_DATA2− IN_C_DATA2+ EDID_SCL EDID_SDA EDID_ENABLE AMUXVCC CEC_OUT CEC_IN DDC_SCL_COM DDC_SDA_COM DDC_SCL_D DDC_SDA_D DDC_SCL_C DDC_SDA_C DDC_SCL_B DDC_SDA_B DDC_SCL_A DDC_SDA_A P5V_D P5V_C P5V_B P5V_A Type TMDS TMDS Control Control Control Power CEC CEC DDC DDC DDC DDC DDC DDC DDC DDC DDC DDC Power Power Power Power Description High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. External EDID EEPROM Serial Interface Clock. External EDID EEPROM Serial Interface Data. EDID Replication Enable. Positive Power Supply 5.0 V. Consumer Electronics Control Output. Consumer Electronics Control Input. Display Data Channel Serial Clock Common Input/Output. Display Data Channel Serial Data Common Input/Output. Display Data Channel Serial Clock Input/Output D. Display Data Channel Serial Data Input/Output D. Display Data Channel Serial Clock Input/Output C. Display Data Channel Serial Data Input/Output C. Display Data Channel Serial Clock Input/Output B. Display Data Channel Serial Data Input/Output B. Display Data Channel Serial Clock Input/Output B. Display Data Channel Serial Data Input/Output A. 5 V HDMI Supply from Source D. 5 V HDMI Supply from Source C. 5 V HDMI Supply from Source B. 5 V HDMI Supply from Source A. Rev. 0 | Page 8 of 28 ADV3002 TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE ADV3002 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07905-021 SMA COAX CABLE 07905-022 07905-024 250mV/DIV 250mV/DIV Figure 3. Test Circuit for Eye Diagrams 0.167UI/DIV AT 2.25Gbps Figure 6. Eye Diagram at TP3 for 2 m Cable 07905-025 07905-023 250mV/DIV 250mV/DIV 0.167UI/DIV AT 2.25Gbps Figure 4. Eye Diagram at TP2 for 2 m Cable 0.167UI/DIV AT 2.25Gbps 0.167UI/DIV AT 2.25Gbps Figure 5. Eye Diagram at TP2 for 20 m 24 AWG Cable Figure 7. Eye Diagram at TP3 for 20 m 24 AWG Cable Rev. 0 | Page 9 of 28 ADV3002 1.0 100 0.9 90 0.8 80 0.7 70 1080p, 12-BIT 1080p, 10-BIT 1080p, 8-BIT 720p 0.6 0.5 JITTER (ps) DETERMINISTIC JITTER (UI) ALL CABLES = 24 AWG 0.4 60 50 DETERMINISTIC JITTER 40 0.3 30 0.2 20 0.1 10 0 0 10 20 INPUT CABLE LENGTH (m) 30 0 10 20 Figure 8. Deterministic Jitter vs. Input Cable Length 30 40 50 60 TEMPERATURE (°C) 70 07905-029 0 07905-026 RANDOM JITTER 80 Figure 11. Jitter vs. Temperature 1000 100 90 800 80 EYE HEIGHT (mV) JITTER (ps) 70 60 50 DETERMINISTIC JITTER 40 600 400 30 200 20 10 0.5 1.0 1.5 2.0 DATA RATE (Gbps) 2.5 3.0 3.5 0 07905-027 0 0 0.5 Figure 9. Jitter vs. Data Rate 1.0 1.5 2.0 DATA RATE (Gbps) 2.5 3.0 3.5 07905-030 RANDOM JITTER 0 Figure 12. Eye Height vs. Data Rate 100 1000 90 80 800 EYE HEIGHT (mV) 60 50 DETERMINISTIC JITTER 40 600 400 30 20 200 10 RANDOM JITTER 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 3.4 3.6 0 2.0 Figure 10. Jitter vs. Supply Voltage 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 Figure 13. Eye Height vs. Supply Voltage Rev. 0 | Page 10 of 28 3.4 3.6 07905-031 0 2.0 07905-028 JITTER (ps) 70 ADV3002 100 90 90 80 80 70 70 60 JITTER (ps) DETERMINISTIC JITTER (ps) 100 EQ = 18dB 50 40 60 50 DETERMINISTIC JITTER 40 30 30 20 20 10 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL INPUT SWING (V) 1.8 2.0 07905-032 0 0 2.0 Figure 14. Deterministic Jitter vs. Input Swing 3.4 3.6 0.6 150 100 DATA RISE TIME @ 2.25Gbps DATA FALL TIME @ 2.25Gbps CLOCK RISE TIME @ 225MHz CLOCK FALL TIME @ 225MHz 0 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 80 70 60 50 40 30 20 0 30 40 50 60 TEMPERATURE (°C) 70 80 07905-034 10 20 DDC CEC HPD 0.2 0.1 2 4 6 LOAD CURRENT (mA) 8 10 Figure 18. DDC, CEC, HPD Output Logic Low Voltage vs. Load Current 100 10 0.3 0 Figure 15. Rise and Fall Time vs. Temperature 0 0.4 0 07905-033 50 0.5 07905-036 OUTPUT LOGIC LOW VOLTAGE (V) 200 RISE/FALL TIME (ps) 2.4 2.6 2.8 3.0 3.2 INPUT COMMON-MODE VOLTAGE (V) Figure 17. Jitter vs. Input Common-Mode Voltage 250 TERMINATION RESISTANCE (Ω) 2.2 07905-035 RANDOM JITTER 0 Figure 16. Termination Resistance vs. Temperature Rev. 0 | Page 11 of 28 ADV3002 The primary function of the ADV3002 is to switch up to four HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. The four low speed control signals are the display data channel (DDC) bus (SDA and SCL), the consumer electronics control (CEC) line, and the hot plug detect (HPD) signal. The input equalizer can be manually configured to provide two different levels of high frequency boost: 6 dB or 18 dB. The equalizer (EQ) level defaults to 18 dB after reset. No specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the ADV3002 can be set to 18 dB without degrading the signal integrity, even for short input cables. AVCC 50Ω IN+ 2 Figure 21. High Speed Input Simplified Schematic TMDS OUTPUT CHANNELS 5V HDMI B EDID A DDC Each high speed output differential pair is terminated to the 3.3 V power supply through a pair of 50 Ω on-chip resistors, as shown in Figure 22. This termination is user-selectable; it can be turned on or off by programming the TX_OTO bit of the TMDS output control register, as shown in Table 10. 2 5V EDID B HDMI C AVEE NOTES 1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS. 2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS. DDC 2 4:1 HDMI MUX 2 DDC HDMI Rx 5V AVCC 2 07905-003 HDMI D EDID C DDC 5V EDID D 50Ω OUT+ 5V DDC DISABLE 2 2 5V ADV3002 DDC ESD PROT. DDC Figure 22. High Speed Output Simplified Schematic 2 The output termination resistors of the ADV3002 back terminate the output TMDS transmission lines. These back terminations, as recommended in the HDMI 1.3a specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the ADV3002 TMDS outputs on multiple layers of the printed circuit board (PCB) without severely degrading the quality of the output signal. 2 2 5V AMUXVCC IOUT AVEE NOTES 1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS. 2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS. HDMI Rx 5V DDC OUT– 2 EDID DDC EXTERNAL EDID EEPROM OR SYSTEM MICROCONTROLLER 07905-004 HDMI D HDMI C HDMI B HDMI A Figure 19. Typical HDMI Multiplexer Implementation DDC 50Ω 07905-006 HDMI A DDC CABLE EQ IN– The ADV3002 also includes an integrated EDID SRAM, eliminating the need for an external EDID EEPROM for each HDMI connector. A typical HDMI multiplexer is shown in Figure 19. The simplified implementation using the ADV3002 is shown in Figure 20. 50Ω 07905-005 THEORY OF OPERATION Figure 20. Simplified Implementation Using the ADV3002 TMDS INPUT CHANNELS Each high speed input differential pair terminates to the 3.3 V power supply through a pair of 50 Ω on-chip resistors, as shown in Figure 21. The state of the input terminations can be configured automatically or programmed manually by setting the appropriate bits in the TMDS input termination control register, as shown in Table 10. The output has a disable feature that places the outputs in tristate mode. Bigger wire-OR’ed arrays can be constructed using the ADV3002 in this mode. The ADV3002 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the ADV3002 are enabled by default after reset. External terminations can be provided either by on-board resistors or by the input termination resistors of an Rev. 0 | Page 12 of 28 ADV3002 EDID REPLICATION HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level to 20 mA by programming the TX_OCL bit of the TMDS output control register, as shown in Table 10 (20 mA is the default upon reset). If only external terminations are provided (if the internal terminations are disabled), set the output current level to 10 mA by programming the TX_OCL bit of the TMDS output control register. The high speed outputs must be disabled if there are no output termination resistors present in the system. The ADV3002 EDID replication feature reduces the total system cost by eliminating the need for an EDID EEPROM for each HDMI port. With the ADV3002, only a single external EDID is necessary. The ADV3002 stores the EDID information in an on-chip SRAM. This enables the EDID information to be simultaneously accessible to all four HDMI ports. The ADV3002 combines the 5 V power from the four HDMI sources such that the EDID information can be available even when the system power is off. A block diagram of the ADV3002 DDC buffering and EDID replication scheme is shown in Figure 23. DDC BUFFERS The DDC buffers are 5 V tolerant bidirectional lines that carry extended display identification data (EDID) and high bandwidth digital content protection (HDCP) encryption. The ADV3002 provides switching and buffering for the DDC buses. The DDC buffers are bidirectional, and fully support arbitration, clock synchronization, and other relevant features of a standard mode I2C bus. SRAM I2C MASTER 2 EDID_[SCL/SDA] 2 I2C_[SCL/SDA] EDID CONTROL I2C READ/ WRITE SLAVE I2 C EXTERNAL EDID EEPROM v1.3 MCU READ/ WRITE SLAVE HDMI PORT A 2 2 I2C READ SLAVE HDMI PORT B 2 2 I2C READ SLAVE HDMI PORT C 2 DDC MUX 2 2 HDMI Rx 2 I2C READ SLAVE 2 2 07905-007 HDMI PORT D Figure 23. EDID Replication Block Diagram Rev. 0 | Page 13 of 28 ADV3002 Source Physical Address Assignment CEC enabled devices have a source physical address (SPA) that allows the CEC controller to address the specific physical devices and control switches. The SPA is comprised of four fields or nibbles. Each field is a 4-bit number; therefore, each field can be any one of 16 possible values (0x0 through 0xF). Each HDMI input port is assigned a unique SPA as shown in Figure 24. In any CEC enabled device, only one of the four fields is unique per port. In HDMI sink applications, where the sink is the root device, only the W field is unique per port, whereas the X, Y, and Z fields are always set to zero. SPA = W. X. Y. Z HDMI PORT B SPA = WB. XB. YB. ZB ADV3002 HDMI PORT C SPA = WC. XC. YC. ZC HDMI PORT D SPA = WD. XD. YD. ZD 07905-008 In HDTV applications where the CEC function is available, the EDID contains the source physical address (SPA); a unique value for each HDMI port. Because the memory in the ADV3002 is volatile, the SPA must be stored in the external EDID EEPROM. Rather than require a larger external EEPROM to store the SPA, because all 256 bytes of memory are needed for typical EDID information, the ADV3002 takes advantage of EDID information that is always a fixed value, such as the 24-bit IEEE registration identifier (0x000C03). The 24 bits of the IEEE registration identifier are replaced with the desired SPA values. When a source requests the IEEE registration identifier, the ADV3002 responds with the fixed value (0x000C03). The ADV3002 then automatically calculates the correct checksum for each port based on the SPA stored for that port in the vendor specific data block (VSDB). HDMI PORT A SPA = WA. XA. YA. ZA Figure 24. SPA Assignments Table 7. Typical Vendor Specific Data Block (VSDB) Byte No. 0 1 2 3 4 5 6 to N 7 6 5 4 3 2 1 Vendor specific tag code Length (= N) (= 3) 24-bit IEEE registration identifier (0x000C03) (least significant byte first) 0 SPA Field W SPA Field X SPA Field Y SPA Field Z Remainder or VSDB is stored in Byte 6 through Byte N Table 8. Vendor Specific Data Block with ADV3002 A typical vendor specific data block (VSDB) is shown in Table 7. When using the ADV3002 EDID replicator, the VSDB should be replaced with the one shown in Table 8, whereby the port specific field can be assigned to any of the four fields (W, X, Y, or Z) depending on the value set in the override select bits as shown in Table 9. When calculating the checksum for Block 1 of the EDID, the custom values entered in place of the IEEE registration identifier should not be used in the calculation; instead, the IEEE registration identifier values should be used (0x000C03). The values in Byte 4 and Byte 5 of the VSDB should be included in the calculation. Byte No. 0 1 2 3 4 5 6 to N 7 6 5 4 3 2 1 0 Length (= N) Vendor specific tag code (= 3) Port A SPA override field Port B SPA override field Port C SPA override field Port D SPA override field Not used Override select (see Table 9) Default W field Default X field Default Y field Default Z field Remainder or VSDB is stored in Byte 6 through Byte N Table 9. Override Select Assignment Bit 3 1 0 0 0 Rev. 0 | Page 14 of 28 Override Select Bit 2 Bit 1 0 0 1 0 0 1 0 0 Bit 0 0 0 0 1 Field Replaced by Port Specific SPA W X Y Z ADV3002 EDID Replication with External EEPROM Reset The ADV3002 has dedicated pins to interface to an external EDID EEPROM: EDID_SDA and EDID_SCL. In the default configuration, after the first hot plug event or system power-up, the internal I2C master in the ADV3002 copies the contents of the external EDID EEPROM into the on-chip SRAM. While the EDID is being copied, the HPD signals for all four ports are held low by the ADV3002. A flowchart of the start-up procedure is shown in Figure 25. The entire start-up procedure takes less than 10 ms. The EDID replication feature can be disabled using the EDID_ENABLE pin. Pullling the RESETB pin low initiates a restart of the EDID replication procedure shown in Figure 25 when the local system supply is on. If the local system supply is off, the RESETB pin has no effect. POWER-UP, RESET, OR FIRST HOT PLUG <100µs WAIT FOR EDID POWER-UP COPY EDID INFORMATION TO ADV3002 SRAM HPD ALL PORTS = LOW 5 V COMBINER The 5 V combiner circuit combines the four 5 V supplies from the four HDMI sources and provides the necessary power to the ADV3002 EDID replication circuit, the CEC buffer, as well as the external EDID EEPROM, if applicable. The combiner circuit is designed such that the current limits on each of the 5 V supplies are not exceeded when the local system power is either on or off. A simplified circuit diagram of the 5 V combiner is shown in Figure 26. The combiner detects the presence of the voltage on the 5 V pin (P5V_x) from the HDMI connectors and closes the respective internal switch to connect the 5 V to AMUXVCC. If the local system 3.3 V and 5 V supplies are available, then the combiner opens all the switches. <10ms DETECT DETERMINE SPA AND CHECKSUM P5V_A DETECT WAIT FOR EDID REQUEST P5V_B HPD ALL PORTS = HIGH AMUXVCC 07905-009 DETECT P5V_C Figure 25. EDID Replication Start-Up Flowchart with External EEPROM Writing to the EDID EEPROM DETECT The EDID data can be written to the external EEPROM by writing data via the I2C control interface or via the HDMI A DDC inputs. In both cases, the EDID write procedure is as follows: 1. 2. 3. Write Value 0x96 to the EDID EEPROM write protect password register, 0x0F. The ADV3002 fixed part address is required to write to this register. Write the EDID data to the EEPROM fixed part address (0xA0). Data must be written one byte at a time. Write Value 0x00 to the EDID EEPROM write protect password register, 0x0F. EDID Replication with External Microcontroller The on-chip SRAM can be preloaded using an external microcontroller. Prior to loading the SRAM, disable the I2C master by writing 0x01 to the EDID replication mode register. The microcontroller can then write EDID information into the SRAM via the ADV3002 I2C control interface. The writes to the SRAM should be to the fixed part address of 0xA0. When the EDID copy process is complete, enable the EDID replication function by writing 0x00 to the EDID replication mode register. The EDID_SDA and EDID_SCL pins are unused when an external microcontroller is used to program the SRAM. These pins can be tied either high or low through a resistor, but should not be left floating. P5V_D 07905-010 RESPOND TO EDID REQUEST Figure 26. 5 V Combiner Simplified Circuit Diagram CEC BUFFER The CEC buffer is bidirectional and includes integrated on-chip pull-up resistors. The CEC buffer isolates capacitance from the PCB and local system microcontroller, which is particularly advantageous in systems where the microcontroller is not placed near the HDMI connectors. The integrated on-chip pull-up resistors are connected to an internal 3.3 V supply that is generated from the AMUXVCC supply; thus, the CEC buffer is fully compliant with the CEC line degradation specifications, when the local system power supply is either on or off. HOT PLUG DETECT CONTROL The HPD lines going into the ADV3002 are normally high impedance but are pulled low for greater than 100 ms when a channel switch occurs. This pull-down pulse width can be changed by modifying the value in the hot plug detect pulse width control register (0x05), as shown in Table 10. Also, the HPD pulse can be manually controlled using the hot plug detect manual override control register (0x06), as shown in Table 10. Rev. 0 | Page 15 of 28 ADV3002 LOSS OF SIGNAL DETECT FD • • • The TMDS input termination resistors must be enabled. By default, the ADV3002 TMDS input termination resistors are enabled only on the selected input. The TMDS clock frequency exceeds the frequency cutoff (LOS_FC). Refer to Table 1 for the value of the LOS frequency cutoff. TMDS clock differential amplitude exceeds the LOS threshold set in the LOS detect control register. Refer to Table 1 for the value of the LOS amplitude threshold. 0 LOS_FC FREQUENCY DETECTOR TMDS CLOCK INPUT[x] LOS_STATUS[3:0] FREQUENCY DETECTOR AD 1 0 LOS_THR 07905-011 The TMDS clock line of each HDMI input has a loss of signal (LOS) monitor attached to it. The purpose of the LOS monitor is to determine if there is activity in the HDMI link. A simplified circuit diagram of the LOS detector is shown in Figure 27. The LOS monitors are disabled by default. The LOS monitors can be enabled by programming the LOS_EN bit of the LOS detect control register. When enabled, the status of each HDMI input can be read in the LOS detect status register. A logic high LOS_STATUS bit of a given HDMI input indicates an inactive input; a logic low LOS_STATUS bit indicates an active input. Three conditions need to be fulfilled for an HDMI input to be considered active: 1 Figure 27. Loss of Signal Detect Simplified Circuit Diagram LOS Autosquelch The LOS detect circuit can be used to automatically disable the TMDS signal path. Setting the LOS_RX_EN bit in the LOS control register causes the selected TMDS input to be disabled when an LOS event occurs on that input. In this case, the TMDS signal path is enabled when the active signal conditions listed previously are met. Rev. 0 | Page 16 of 28 ADV3002 SERIAL CONTROL INTERFACE RESET On initial power-up, or at any point in operation, the ADV3002 register set can be restored to the default values by pulling the RESETB pin low according to the specification in Table 3. During normal operation, however, the RESETB pin must be pulled up to 3.3 V. 6. 7. 8. 9. WRITE PROCEDURE To write data to the ADV3002 register set, an I2C master (such as a microcontroller) needs to send the appropriate control signals to the ADV3002 slave device. The signals are controlled by the I2C master unless otherwise specified. For a diagram of the procedure, see Figure 28. The steps for a write procedure are as follows: 2. 3. 4. 5. Send a start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low). Send the ADV3002 part address (seven bits). The upper five bits of the ADV3002 part address are the static value [10010] and the two LSBs are set by Input Pins I2C_ADDR[1:0]. This transfer should be MSB first. Send the write indicator bit (0). Wait for the ADV3002 to acknowledge the request. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first. * I2C_SCL R/W GENERAL CASE I2C_SDA START FIXED ADDR PART REGISTER ADDR ADDR ACK DATA ACK STOP ACK EXAMPLE I2C_SDA 1 2 3 4 5 *THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8. Figure 28. I2C Write Procedure Rev. 0 | Page 17 of 28 6 7 8 9 07905-012 1. Wait for the ADV3002 to acknowledge the request. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. Wait for the ADV3002 to acknowledge the request. Do one of the following: a. Send a stop condition (while holding the I2C_SCL line high, pull the I2C_SDA line high) and release control of the bus to end the transaction (shown in Figure 28). b. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 2 in this procedure to perform another write. c. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 2 of the read procedure (in the Read Procedure section) to perform a read from another address. d. Send a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 8 of the read procedure (in the Read Procedure section) to perform a read from the same address set in Step 5 of the write procedure. ADV3002 I2C_SCL R/W START FIXED PART ADDR R/W ADDR REGISTER ADDR SR FIXED PART ADDR ACK ACK ADDR DATA STOP ACK NACK 9 10 11 12 EXAMPLE I2C_SDA 1 2 3 4 5 6 7 8 13 07905-013 GENERAL CASE I2C_SDA 2 Figure 29. I C Read Procedure READ PROCEDURE To read data from the ADV3002 register set, an I C master (such as a microcontroller) needs to send the appropriate control signals to the ADV3002 slave device. The signals are controlled by the I2C master unless otherwise specified. For a diagram of the procedure, see Figure 29. The steps for a read procedure are as follows: 2 1. Send a start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low). 2. Send the ADV3002 part address (seven bits). The upper five bits of the ADV3002 part address are the static value [10010] and the two LSBs are set by Input Pins I2C_ADDR[1:0]. This transfer should be MSB first. 3. Send the write indicator bit (0). 4. Wait for the ADV3002 to acknowledge the request. 5. Send the register address (eight bits) from which data is to be read. This transfer should be MSB first. 6. Wait for the ADV3002 to acknowledge the request. 7. Send a repeated start condition (Sr) by holding the I2C_SCL line high and pulling the I2C_SDA line low. 8. Resend the ADV3002 part address (seven bits) from Step 2. The upper five bits of the ADV3002 part address compose the static value [10010]. The two LSBs are set by Input Pins I2C_ ADDR[1:0]. This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the ADV3002 to acknowledge the request. 11. Read the data from the ADV3002. The ADV3002 serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Do one of the following: a. Send a no acknowledge (NACK) followed by a stop condition (while holding the I2C_SCL line high, pull the SDA line high) and release control of the bus to end the transaction (shown in Figure 29). b. Send a no acknowledge (NACK) followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 2 of the write procedure (see the previous Write Procedure section) to perform a write. c. Send a no acknowledge (NACK) followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 2 of this procedure to perform a read from another address. d. Send a no acknowledge (NACK) followed by a repeated start condition (while holding the I2C_SCL line high, pull the I2C_SDA line low) and continue from Step 8 of this procedure to perform a read from the next byte. e. Send an acknowledge (ACK) and read the next byte of data. Continue from Step 11. 13. Send a stop condition (while holding the I2C_SCL line high, pull the I2C_SDA line high). Rev. 0 | Page 18 of 28 ADV3002 REGISTER MAP Table 10. Register Map Address 0x00 0x01 0x02 0x03 0x04 Default 0x00 0x07 0x02 0x0F 0x07 0x05 0x05 0x06 0x00 Register Name Channel select control Bit 7:3 2 Bit Name Unused CH_SRC 1:0 CH[1:0] channel select 7:4 3 Unused TX_EN_SRC 2 TX_EN 1 TX_OCL 0 TX_OTO 7:2 1 Unused EQ_SEL 0 ISIGN TMDS input termination control 7:4 ITO_SRC[3:0] 3:0 ITO_CTL[3:0] Auxiliary buffer enables 7:3 2 1 Unused Reserved DDC_EN 0 CEC_EN 7:0 HPD_PW[7:0] 7:5 4 Unused HPD_SRC 3:0 HPD_CTL[3:0] TMDS output control TMDS input control Hot plug detect pulse width control Hot plug detect manual override control Description Unused 0: input selected by SEL[1:0] parallel pins 1: input selected by channel select control register, CH[1:0] channel select 00: Input A selected if CH_SRC = 1 01: Input B selected if CH_SRC = 1 10: Input C selected if CH_SRC = 1 11: Input D selected if CH_SRC = 1 Unused 0: TMDS output enable controlled by the TX_EN parallel pin 1: TMDS output enable controlled by the TX_EN bit 0: TMDS output disabled if TX_EN_SRC = 1 1: TMDS output enabled if TX_EN_SRC = 1 0: TMDS output current = 10 mA 1: TMDS output current = 20 mA 0: TMDS output termination = off 1: TMDS output termination = on Unused 0: TMDS equalizer boost = 6 dB 1: TMDS equalizer boost = 18 dB 0: TMDS input polarity = standard 1: TMDS input polarity = inverse 0000: input termination control is automatic 1111: input termination control is manual 0000: all input terminations off if input termination control is manual 0001: Input A termination on if input termination control is manual 0010: Input B termination on if input termination control is manual 0100: Input C termination on if input termination control is manual 1000: Input D termination on if input termination control is manual 1111: all input terminations on if input termination control is manual Unused Reserved; set to 1 0: DDC buffer disabled 1: DDC buffer enabled 0: CEC buffer disabled 1: CEC buffer enabled Pulse width = decimal (HPD_PW) × step size (24 ms typical) Unused 0: hot plug detect control is automatic; pulse width set by hot plug detect pulse width control register 1: hot plug detect control is manual; hot plug detect state is set by HPD_CTL[3:0] 0000: HPD outputs are high impedance (pulled up to 5 V via external resistor) 0001: HPD_A = low if HPD_SRC = 1 0010: HPD_B = low if HPD_SRC = 1 0100: HPD_C = low if HPD_SRC = 1 1000: HPD_D = low if HPD_SRC = 1 1111: all HPD outputs = low if HPD_SRC = 1 Rev. 0 | Page 19 of 28 ADV3002 Address 0x07 Default 0x00 Register Name Loss of signal detect control Bit 7:6 5:4 Bit Name Unused LOS_THR[1:0] 3 2 Unused LOS_RX_EN 1 0 Reserved LOS_EN Description Unused 00: LOS Threshold 0 01: LOS Threshold 1 10: LOS Threshold 2 11: LOS Threshold 3 Unused 0: TMDS autosquelch disabled 1: TMDS autosquelch enabled Reserved; set to 0 0: LOS detect disabled 1: LOS detect enabled Unused 0: EDID replicator enabled; for use with an external EEPROM 1: EDID replicator disabled; external microcontroller can write the SRAM; write only 0x00: write protect enabled; EDID EEPROM writes not allowed 0x96: write protect disabled; EDID EEPROM writes from Port A or I2C control are allowed; write only 0x0E 0x00 EDID replication mode (write only) 7:1 0 Unused EDID_REPL_EN (write only) 0x0F 0x00 7:0 PASSWD[7:0] (write only) 0x10 0x00 EDID EEPROM write protect password (write only) Loss of signal detect status 7:4 3:0 Unused LOS_STATUS[3:0] (read only) 0xFE 0x03 Revision 7:0 0xFF 0xC2 Device ID 7:0 REV[7:0] (read only) ID[7:0] (read only) Unused 0000: TMDS active on all inputs 0001: loss of signal detected on Input A 0010: loss of signal detected on Input B 0100: loss of signal detected on Input C 1000: loss of signal detected on Input D 1111: loss of signal detected on all inputs 0x03: read only 0xC2: read only Rev. 0 | Page 20 of 28 ADV3002 APPLICATIONS INFORMATION The ADV3002 is a complete HDMI/DVI link switch featuring equalized TMDS inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports. Alternatively, a system standby microcontroller can be used instead of a dedicated EDID EEPROM to load the ADV3002 SRAM. Simplified application schematics are shown in Figure 33 and Figure 34 illustrating these two options. available when the system power is off, a Thevenin equivalent 2 kΩ pull-up resistor to 3.3 V is shown in Figure 31. 5V_COMBINED AMUXVCC ADV3002 3kΩ CEC_OUT MCU CEC_IN 6kΩ 07905-015 HDMI MULTIPLEXER FOR ADVANCED TV Figure 31. CEC Circuit 5 V Power HDTV SET The individual 5 V power from each HDMI source can be routed to the respective 5 V inputs of the ADV3002. The ADV3002 combines these four 5 V supplies into one labeled AMUXVCC to support EDID replication and CEC functionality when the local system power is off. An internal 5 V supply must be provided so that power is not drawn from the HDMI sources when the local system power is on. When the local supply is off, this internal 5 V should be high impedance. This can be assured by using a Schottky diode, as shown in Figure 32. ADV3002 MAIN PCB HDMI Rx OR SoC 07905-014 P5V_A 5V INTERNAL Figure 30. ADV3002 as an HDMI Multiplexer in an HDTV P5V_B TMDS Signals TMDS signals can be routed from an HDMI connector directly to the inputs of the ADV3002. Additional components are not required for the TMDS signals. AMUXVCC P5V_C DDC Signals 47 kΩ pull-up resistors to 5 V are recommended for the DDC input signals. P5V_D The CEC buffer in the ADV3002 provides a fully compliant input in situations where a general-purpose microcontroller is used to interpret CEC commands. The rise time of the CEC buffer is set by the time constant of the pull-up resistance and the capacitance on the node. A 2 kΩ pull-up resistor to 3.3 V is recommended for optimal output rise times. If a 3.3 V is not Rev. 0 | Page 21 of 28 07905-016 CEC Signal Figure 32. 5 V Power Connections ADV3002 5V OPTION 1 3.3V AMUXVCC 1µF 0.01µF 0.01µF 0.1µF 0.001µF AMUXVCC TMDS D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 1kΩ 47kΩ TMDS 1kΩ 47kΩ HPD_A DDC_SCL_A DDC_SDA_A OUT_DATA2+ OUT_DATA2– OUT_DATA1+ OUT_DATA1– OUT_DATA0+ OUT_DATA0– OUT_CLK+ OUT_CLK– IN_B_DATA2+ IN_B_DATA2– IN_B_DATA1+ IN_B_DATA1– IN_B_DATA0+ IN_B_DATA0– IN_B_CLK+ IN_B_CLK– P5V_B 47kΩ HPD DDC_SCL DDC_SDA CEC TMDS 1kΩ 47kΩ TMDS 2kΩ HDMI Rx 2kΩ DDC_SCL_COM DDC_SDA_COM DDC_SCL DDC_SDA AMUXVCC ADV3002 IN_C_DATA2+ IN_C_DATA2– IN_C_DATA1+ IN_C_DATA1– IN_C_DATA0+ IN_C_DATA0– IN_C_CLK+ IN_C_CLK– P5V_C 3.3V STANDBY 10kΩ 2kΩ 2kΩ I2C_SCL I2C_SDA I2C_ADDR[1:0] CEC_OUT 2kΩ STANDBY MCU 10kΩ OPTIONAL AVCC EDID_ENABLE 10kΩ 47kΩ HPD DDC_SCL DDC_SDA CEC D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– AMUXVCC HPD_B DDC_SCL_B DDC_SDA_B CEC_IN D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 10kΩ EDID_SCL EDID_SDA HPD_C DDC_SCL_C DDC_SDA_C AMUXVCC 10kΩ TMDS D2+ D2– IN_D_DATA2+ IN_D_DATA2– IN_D_DATA1+ IN_D_DATA1– IN_D_DATA0+ IN_D_DATA0– IN_D_CLK+ IN_D_CLK– P5V_D D1+ D1– D0+ D0– CLK+ CLK– 5V 47kΩ RESETB 1µF TX_EN SEL[1:0] 47kΩ HPD_D DDC_SCL_D DDC_SDA_D AVEE 07905-017 1kΩ HPD DDC_SCL DDC_SDA CEC AVCC 47kΩ HPD DDC_SCL DDC_SDA CEC D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V IN_A_DATA2+ IN_A_DATA2– IN_A_DATA1+ IN_A_DATA1– IN_A_DATA0+ IN_A_DATA0– IN_A_CLK+ IN_A_CLK– P5V_A Figure 33. Simplified Application Circuit Diagram (Option 1—No External EEPROM) Rev. 0 | Page 22 of 28 ADV3002 5V OPTION 2 3.3V AMUXVCC 1µF 0.01µF 0.1µF 0.01µF 0.001µF AMUXVCC TMDS D2+ D2– IN_A_DATA2+ IN_A_DATA2– D1+ D1– D0+ D0– CLK+ CLK– 5V IN_A_DATA1+ IN_A_DATA1– IN_A_DATA0+ IN_A_DATA0– IN_A_CLK+ IN_A_CLK– P5V_A 1kΩ 47kΩ 47kΩ HPD DDC_SCL DDC_SDA CEC HPD_A DDC_SCL_A DDC_SDA_A TMDS D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 1kΩ 47kΩ IN_B_DATA2+ IN_B_DATA2– IN_B_DATA1+ IN_B_DATA1– IN_B_DATA0+ IN_B_DATA0– IN_B_CLK+ IN_B_CLK– P5V_B 47kΩ HPD DDC_SCL DDC_SDA CEC TMDS OUT_DATA2+ OUT_DATA2– OUT_DATA1+ OUT_DATA1– OUT_DATA0+ OUT_DATA0– OUT_CLK+ OUT_CLK– TMDS 1kΩ 47kΩ DDC_SCL DDC_SDA 3.3V STANDBY 47kΩ 2kΩ I2C_SCL I2C_SDA I2C_ADDR[1:0] CEC_OUT MCU 10kΩ OPTIONAL AMUXVCC 3.3V STANDBY 10kΩ 3.3V STANDBY EDID_ENABLE 2kΩ 2kΩ EDID EEPROM IN_D_DATA2+ IN_D_DATA2– IN_D_DATA1+ IN_D_DATA1– IN_D_DATA0+ IN_D_DATA0– IN_D_CLK+ IN_D_CLK– P5V_D AMUXVCC 10kΩ RESETB TX_EN SEL[1:0] 1µF 47kΩ HPD_D DDC_SCL_D DDC_SDA_D AVEE 07905-018 1kΩ 2kΩ EDID_SCL EDID_SDA TMDS D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 2kΩ 47kΩ HPD_C DDC_SCL_C DDC_SDA_C HDMI Rx 2kΩ 2kΩ DDC_SCL_COM DDC_SDA_COM ADV3002 IN_C_DATA2+ IN_C_DATA2– IN_C_DATA1+ IN_C_DATA1– IN_C_DATA0+ IN_C_DATA0– IN_C_CLK+ IN_C_CLK– P5V_C HPD DDC_SCL DDC_SDA CEC D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– AMUXVCC HPD_B DDC_SCL_B DDC_SDA_B CEC_IN D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V HPD DDC_SCL DDC_SDA CEC AVCC Figure 34. Simplified Application Diagram (Option 2—External EDID EEPROM) Rev. 0 | Page 23 of 28 ADV3002 CABLE LENGTHS AND EQUALIZATION The ADV3002 offers two levels of programmable equalization for the high speed inputs: 6 dB and 18 dB. The equalizer of the ADV3002 supports video data rates of up to 2.25 Gbps and can equalize more than 20 meters of 24 AWG HDMI cable at 2.25 Gbps, which corresponds to the video format, 1080p with 12-bit Deep Color. The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors including • • • • Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors have lower signal degradation per unit length. Data rate: the data rate being sent over the cable. The signal degradation of HDMI cables increases with data rate. Edge rates: the edge rates of the source input. Slower input edges result in more significant data eye closure at the end of a cable. Receiver sensitivity: the sensitivity of the terminating receiver. As such, no particular equalizer setting is recommended for specific cable types or lengths. In nearly all applications, the ADV3002 equalization level can be set to high, or 18 dB, for all input cable configurations at all data rates, without degrading the signal integrity. PCB LAYOUT GUIDELINES The ADV3002 switches two distinctly different types of signals, both of which are required for HDMI and DVI video. These signal groups require different treatment when laying out a PCB. The first group of signals carries the A/V data. HDMI/DVI video signals are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating up to at least 2.25 Gbps. It is especially important to note that the differential traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 Ω. The ADV3002 provides single-ended 50 Ω terminations on-chip for both its inputs and outputs, and both the input and output terminations can be enabled or disabled through the serial interface. Output termination is recommended but not required by the HDMI standard but its inclusion improves the overall system signal integrity. The A/V data carried on these high speed channels is encoded by a technique called TMDS, and in the case of HDMI, is also encrypted according to the HDCP standard. The second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. Depending upon the application, these signals can include the DDC bus (this is an I2C bus used to send EDID information and HDCP encryption keys between the source and the sink), the CEC line, and the HPD line. These auxiliary signals are bidirectional, low speed, and transferred over a single-ended transmission line that does not need to have controlled impedance. The primary concern with laying out the auxiliary lines is ensuring that they conform to the I2C bus standard and do not have excessive capacitive loading. TMDS Signals In the HDMI/DVI standard, four differential pairs carry the TMDS signals. In DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data interleaves with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair is used for the A/V data-word clock, and runs at one-tenth the speed of the TMDS data channels. The ADV3002 buffers the TMDS signals, and the input traces can be considered electrically independent of the output traces. In most applications, the quality of the signal on the input TMDS traces are more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the ADV3002, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. Layout for the TMDS Signals The TMDS differential pairs can be either microstrip traces (routed on the outer layer of a board) or stripline traces (routed on an internal layer of the board). If microstrip traces are used, there should be a continuous reference plane on the PCB layer directly below the traces. If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stack-up. Additionally, the p and n of each differential pair must have a controlled differential impedance of 100 Ω. The characteristic impedance of a differential pair is a function of several variables including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the PCB binder material. Interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path; therefore, it is preferable to route the TMDS lines exclusively on one layer of the board, particularly for the input traces. Additionally, to prevent unwanted signal coupling and interference, route the TMDS signals away from other signals and noise sources on the PCB. Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (DCD). Always route the p and n of a given differential pair together to establish the required 100 Ω differential impedance. Leave enough space between the differential pairs of a given group to prevent the n of one pair from coupling with the p of another pair. For example, one technique is to make the interpair distance four to 10 times wider than the intrapair spacing. Any one group of four TMDS traces (Input A, Input B, Input C, Input D, or the output) should have closely matched trace lengths to minimize interpair skew. Severe interpair skew can Rev. 0 | Page 24 of 28 ADV3002 Minimizing intrapair and interpair skew becomes increasingly important as data rates increase. Any introduced skew constitutes a correspondingly larger fraction of a bit period at higher data rates. Though the ADV3002 features input equalization and output preemphasis, minimizing the length of the TMDS traces is needed to reduce overall system signal degradation. Commonly used PCB material, such as FR4, is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol interference (ISI). THROUGH-HOLE VIAS SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) SILKSCREEN KEEP REFERENCE PLANE ADJACENT TO SIGNAL ON ALL LAYERS TO PROVIDE CONTINUOUS GROUND CURRENT RETURN PATH. Controlling the Characteristic Impedance of a TMDS Differential Pair 07905-019 cause the data on the four different channels of a group to arrive out of alignment with one another. A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material. Figure 35. Example Routing of Reference Plane The characteristic impedance of a differential pair depends on a number of variables, including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the PCB binder material. To a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. There are many combinations that can produce the correct characteristic impedance. Generally, working with the PCB fabricator is required to obtain a set of parameters to produce the desired results. One consideration is how to guarantee a differential pair with a differential impedance of 100 Ω over the entire length of the trace. One technique to accomplish this is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other. When the two traces of a differential pair are close and strongly coupled, they should have a width that produces a100 Ω differential impedance. When the traces split apart to go into a connector, for example, and are no longer so strongly coupled, the width of the traces need to be increased to yield a differential impedance of 100 Ω in the new configuration. Ground Current Return In some applications, it can be necessary to invert the output pin order of the ADV3002. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers, it is necessary to also reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals. Standard plated through-hole vias are acceptable for both the TMDS traces and the reference plane. An example of this is illustrated in Figure 35. TMDS Terminations The ADV3002 provides internal 50 Ω single-ended terminations for all of its high speed inputs and outputs. It is not necessary to include external termination resistors for the TMDS differential pairs on the PCB. The output termination resistors of the ADV3002 back terminate the output TMDS transmission lines. These back terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the ADV3002 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. Auxiliary Control Signals There are four single-ended control signals associated with each source or sink in an HDMI/DVI application. These are hot plug detect (HPD), consumer electronics control (CEC), and two display data channel (DDC) lines. The two signals on the DDC bus are SDA and SCL (serial data and serial clock, respectively). The DDC and CEC signals are buffered and switched through the ADV3002, and the HPD signal is pulsed low by the ADV3002. These signals do not need to be routed with the same strict considerations as the high speed TMDS signals. In general, it is sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB. However, it is best to follow strict layout practices whenever possible to prevent the PCB design from affecting the overall application. The specific routing of the HPD, CEC, and DDC lines depends upon the application in which the ADV3002 is being used. For example, the maximum speed of signals present on the auxiliary lines are 100 kHz I2C data on the DDC lines, therefore, any layout that enables 100 kHz I2C to be passed over the DDC Rev. 0 | Page 25 of 28 ADV3002 bus should suffice. The HDMI 1.3a specification, however, places a strict 50 pF limit on the amount of capacitance that can be measured on either SDA or SCL at the HDMI input connector. This 50 pF limit includes the HDMI connector, the PCB, and whatever capacitance is seen at the input of the ADV3002, or an equivalent receiver. There is a similar limit of 150 pF of input capacitance for the CEC line. The benefit of the ADV3002 is that it buffers these lines, isolating the output capacitance so that only the capacitance at the input side contributes to the specified limit. HPD is a dc signal presented by a sink to a source to indicate that the source EDID is available for reading. The trace routing of this signal is not critical, but it should be routed as directly as possible. The parasitic capacitance of traces on a PCB increases with trace length. To help ensure that a design satisfies the HDMI specification, make the length of the CEC and DDC lines on the PCB as short as possible. Additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the PCB stackup, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. An example of the board stackup is shown in Figure 36. Power Supplies 3W W 3W When the ADV3002 is powered up, the DDC/CEC inputs of the selected channel are actively buffered and routed to the outputs, and the unselected auxiliary inputs are high impedance. When the ADV3002 is powered off, all DDC/CEC inputs are placed in a high impedance state. This prevents contention on the DDC bus, enabling a design to include an EDID in front of the ADV3002. The ADV3002 has two separate power supplies. The supply/ ground pairs are • • AVCC/AVEE AMUXVCC/AVEE The AVCC/AVEE (3.3 V) supply powers the core of the ADV3002. The AMUXVCC/AVEE supply (5 V) powers the auxiliary multiplexer and EDID replication core. Power Supply Bypassing The ADV3002 requires minimal supply bypassing. Generally, place bypass capacitors near the power pins and connect them directly to the relevant supplies (without long intervening traces). For example, to improve the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias. The capacitors should via down directly to the supply planes and should be placed within a few centimeters of the ADV3002. SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) REFERENCE LAYER RELIEVED UNDERNEATH MICROSTRIP 07905-020 SILKSCREEN Figure 36. Example Board Stackup for Auxiliary Control Signals Rev. 0 | Page 26 of 28 ADV3002 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY VIEW A 20 41 40 21 VIEW A 0.65 BSC LEAD PITCH ROTATED 90° CCW 0.38 0.32 0.22 051706-A 1.45 1.40 1.35 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 37. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters ORDERING GUIDE Model ADV3002BSTZ 1 ADV3002BSTZ-RL1 ADV3002-EVALZ1 1 Temperature Range 0°C to +85°C 0°C to +85°C Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP], Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option ST-80-2 ST-80-2 Ordering Quantity 1,000 ADV3002 NOTES Purchase of licensed I2C components of Analog Devices Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07905-0-12/08(0) Rev. 0 | Page 28 of 28