a FEATURES Guaranteed Monotonic Over Temperature Excellent Matching Between DACs Unipolar or Bipolar Operation Buffered Voltage Outputs High Speed Serial Digital Interface Reset to Zero- or Center-Scale Wide Supply Range, +5 V-Only to 615 V Low Power Consumption (35 mW max) Available in 16-Pin DIP and SOL Packages APPLICATIONS Software Controlled Calibration Servo Controls Process Control and Automation ATE Quad 12-Bit Serial Voltage Output DAC DAC8420 FUNCTIONAL BLOCK DIAGRAM The three-wire serial digital input is easily interfaced to microprocessors running at 10 MHz rates, with minimal additional circuitry. Each DAC is addressed individually by a 16-bit serial word consisting of a 12-bit data word and an address header. The user-programmable reset control CLR forces all four DAC outputs to either zero or midscale, asynchronously overriding the current DAC register values. The output voltage range, determined by the inputs VREFHI and VREFLO, is set by the user for positive or negative unipolar or bipolar signal swings within the supplies allowing considerable design flexibility. 1 REG DAC A REG AA 7 VOUTA REG DAC B B 6 VOUTB REG DAC C C 3 VOUTC REG DAC D D 2 VOUTD 12 CS 12 CLK 11 SHIFT REGISTER NC 13 4 DECODE LD 14 2 9 The DAC8420 is a quad, 12-bit voltage-output DAC with serial digital interface, in a 16-pin package. Utilizing BiCMOS technology, this monolithic device features unusually high circuit density and low power consumption. The simple, easy-to-use serial digital input and fully buffered analog voltage outputs require no external components to achieve specified performance. VDD 5 SDI 10 GND GENERAL DESCRIPTION VREFHI 16 15 CLSEL CLR 4 8 VREFLO VSS The DAC8420 is available in 16-pin epoxy DIP, cerdip, and wide-body SOL (small-outline surface mount) packages. Operation is specified with supplies ranging from +5 V-only to ± 15 V, with references of +2.5 V to ± 10 V respectively. Power dissipation when operating from ± 15 V supplies is less than 255 mW (max), and only 35 mW (max) with a +5 V supply. For applications requiring product meeting MIL-STD-883, contact your local sales office for the DAC8420/883 data sheet, which specifies operation over the –55°C to +125°C temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 DAC8420–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (at VDD = +5.0 V 6 5%, VSS = 0.0 V, VVREFHI = +2.5 V, VVREFLD = 0.0 V, and VSS = –5.0 V 6 5%, VVREFLO = –2.5 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.) Parameter Symbol STATIC ACCURACY Integral Linearity “E” Integral Linearity “E” Integral Linearity “F” Integral Linearity “F” Differential Linearity Min-Scale Error Full-Scale Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco INL INL INL INL DNL ZSE FSE ZSE FSE TCZSE TCFSE Condition Min Note 2, VSS = 0 V Note 2, VSS = 0 V Monotonic Over Temperature RL = 2 kΩ, VSS = –5 V RL = 2 kΩ, VSS = –5 V Note 2, RL = 2 kΩ, VSS = 0 V Note 2, RL = 2 kΩ, VSS = 0 V Note 3, RL = 2 kΩ, VSS = –5 V Note 3, RL = 2 kΩ, VSS = –5 V Typ Max Units ± 1/4 ± 1/2 ± 3/4 ±1 ± 1/4 ±1 ±3 ±2 ±4 ±1 ±4 ±4 ±8 ±8 LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C ± 10 ± 10 MATCHING PERFORMANCE Linearity Matching ±1 REFERENCE Positive Reference Input Range Negative Reference Input Range Negative Reference Input Range Reference High Input Current Reference Low Input Current VVREFHI VVREFLO VVREFLO IVREFHI IVREFLO Note 4 Note 4 Note 4, VSS = 0 V Codes 000H, 555H Codes 000H, 555H, VSS = –5 V VVREFLO +2.5 VSS 0 –0.75 –1.0 AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate IOUT tS SR VSS = –5 V to 0.01%, Note 5 10% to 90%, Note 5 –1.25 LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Input Capacitance VINH VINL IIN CIN LOGIC TIMING CHARACTERISTICS3, 6 Data Setup Time Data Hold Clock Pulse Width HIGH Clock Pulse Width LOW Select Time Deselect Delay Load Disable Time Load Delay Load Pulse Width Clear Pulse Width tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDW tCLRW SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation PSRR IDD ISS PDISS ± 0.25 –0.6 LSB VDD –2.5 VVREFHI –2.5 VVREFHI –2.5 +0.75 V V V mA mA +1.25 mA µs V/µs 8 1.5 2.4 0.8 10 Note 3 13 25 55 90 120 90 5 130 35 80 150 –6 VSS = 0 V V V µA pF ns ns ns ns ns ns ns ns ns ns 0.002 4 –3 20 0.01 7 35 %/% mA mA mW NOTES 1 All supplies can be varied ± 5% and operation is guaranteed. Device is tested with V DD = +4.75 V. 2 For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at code 003H. 3 Guaranteed but not tested. 4 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 5 VOUT swing between +2.5 V and –2.5 V with VDD = 5.0 V. 6 All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 7 Typical values indicate performance measured at +25°C. Specifications subject to change without notice. –2– REV. 0 DAC8420 ELECTRICAL CHARACTERISTICS (at VDD = +15.0 V 6 5%, VSS = –15.0 V 6 5%, VVREFHI = +10.0 V, VVREFLO = –10.0 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.) Parameter Symbol STATIC ACCURACY Integral Linearity “E” Integral Linearity “F” Differential Linearity Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco INL INL DNL ZSE FSE TCZSE TCFSE Condition Min Monotonic Over Temperature RL = 2 kΩ RL = 2 kΩ Note 2, RL = 2 kΩ Note 2, RL = 2 kΩ Typ Max Units ± 1/4 ± 1/2 ± 1/4 ± 1/2 ±1 ±1 ±2 ±2 LSB LSB LSB LSB LSB ppm/°C ppm/°C ±4 ±4 MATCHING PERFORMANCE Linearity Matching ±1 REFERENCE Positive Reference Input Range Negative Reference Input Range Reference High Input Current Reference Low Input Current VVREFHI VVREFLO IVREFHI IVREFLO Note 3 Note 3 Codes 000H, 555H Codes 000H, 555H AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate IOUT tS SR to 0.01%, Note 4 10% to 90%, Note 4 Note 2 Note 2 3 dB, VVREFHI = 5 V + 10 V p-p, VVREFLO = –10 V, Note 2 Code Transition = 7FFH to 800H, Note 2 DYNAMIC PERFORMANCE Analog Crosstalk Digital Feedthrough Large Signal Bandwidth Glitch Impulse LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Input Capacitance VINH VINL IIN CIN LSB VVREFLO +2.5 –10 –2.0 ± 1.0 –3.5 –2.0 VDD –2.5 VVREFHI –2.5 +2.0 V V mA mA –5 +5 13 2 mA µs V/µs >64 >72 90 dB dB kHz 64 nV-s 2.4 0.8 10 Note 2 13 V V µA pF 2, 5 LOGIC TIMING CHARACTERISTICS Data Setup Time Data Hold Clock Pulse Width HIGH Clock Pulse Width LOW Select Time Deselect Delay Load Disable Time Load Delay Load Pulse Width Clear Pulse Width tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDW tCLRW SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation PSRR IDD ISS PDISS 25 20 30 50 55 15 40 15 45 70 –8 0.002 6 –5 0.01 9 255 NOTES 1 All supplies can be varied ± 5% and operation is guaranteed. 2 Guaranteed but not tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 VOUT swing between +10 V and –10 V. 5 All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 6 Typical values indicate performance measured at +25°C. Specifications subject to change without notice. REV. 0 ns ns ns ns ns ns ns ns ns ns –3– %/% mA mA mW DAC8420 (at VDD = +15.0 V, VSS = –15.0 V, VREFHI = +10.0 V, VREFLO = –10.0 V, TA = +258C WAFER TEST LIMITS unless otherwise noted) Parameter Symbol Integral Linearity Differential Linearity Min-Scale Offset Max-Scale Offset Logic Input High Voltage Logic Input Low Voltage Logic Input Current Positive Supply Current Negative Supply Current INL DNL DAC8420G Limit Conditions Units ±1 ±1 ±1 ±1 2.4 0.8 1 8 7 VINH VINL IIN IDD ISS LSB max LSB max LSB max LSB max V min V max µA max mA max mA max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +36.0 V VSS to VVREFLO . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VSS – 2.0 V VVREFHI to VVREFLO . . . . . . . . . . . . . . . . . . . +2.0 V, VDD – VSS VVREFHI to VDD . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V IVREFHI, IVREFLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Digital Input Voltage to GND . . . . . . . . . –0.3 V, VDD + 0.3 V Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Operating Temperature Range EP, FP, ES, FS, EQ, FQ . . . . . . . . . . . . . . –40°C to +85°C Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C Package Type 16-Pin Plastic DIP (P) 16-Pin Hermetic DIP (Q) 16-Lead Small Outline Surface Mount (S) Thermal Resistance θJA θJC Units 701 821 27 9 °C/W °C/W 862 22 °C/W 3. Remove power before inserting or removing units from their sockets. 4. Analog Outputs are protected from short circuits to ground or either supply. DICE CHARACTERISTICS (SUBSTRATE) VOUTD VDD CLSEL 16 2 1 CLR 15 14 LD 13 NC VOUTC 3 VREFLO 4 VREFHI 5 NOTES 1 θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket. 2 θJA is specified for device on board. VOUTB 6 CAUTION 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 12 CS 11 CLK 7 VOUTA 2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 8 9 VSS GND 10 SDI NC = NO CONNECT Die Size 0.119 × 0.283 inch, 33,677 sq. mils (3.023 × 7.188 mm, 21.73 sq. mm) Transistor Count 2,207 For additional DICE ordering information, refer to databook. –4– REV. 0 DAC8420 DATA LOAD SEQUENCE tCSH CS tCSS SDI A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0 CLK tLD1 tLD2 LD DATA LOAD TIMING tDH tDS CLEAR TIMING SDI CLSEL CLK CLR tCLRW tCH tCL tS tCSH CS ±1LSB VOUT tLD2 tLDW LD tS VOUT ±1LSB Timing Diagram ORDERING GUIDE 5kΩ Model1 Temperature Range INL (6LSB) Package Description Package Option2 DAC8420EP DAC8420EQ DAC8420ES DAC8420FP DAC8420FQ DAC8420FS DAC8420QBC –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0.5 0.5 0.5 1.0 1.0 1.0 1.0 Plastic DIP Cerdip SOIC Plastic DIP Cerdip SOIC Dice3 P Q SOL P Q SOL 10Ω +15V + 1N4001 10µF 1 16 NC 2 15 NC 3 14 0.1µF 10Ω 4 –10V 1N4001 + 10µF DUT 0.1µF 5kΩ 13 NC 5 12 NC 6 11 NC 7 10 8 9 10Ω +10V + 10µF 1N4001 0.1µF NOTES 1 A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office. 2 PMI division letter designator. 3 Dice tested at +25°C only. 10kΩ 10Ω –15V 1N4001 + 10µF 0.1µF NC = NO CONNECT Burn-In Diagram REV. 0 –5– DAC8420 PIN CONFIGURATIONS SOL DIP VDD 1 16 VDD CLSEL 16 CLSEL 1 VOUTD 2 DAC-8420 VOUTC 3 VREFLO 4 TOP VIEW 14 LD DAC-8420 (Not to Scale) DAC8420 VREFHI 5 12 CS 15 CLR VOUTD 2 15 CLR VOUTC 3 14 LD VREFLO 4 DAC8420 13 NC VREFHI 5 TOP VIEW (Not to Scale) 12 CS VOUTB 6 11 CLK VOUTB 6 11 CLK VOUTA 7 10 SDI VOUTA 7 10 SDI VSS 8 9 GND TOP VIEW TOP VIEW (Not to Scale) (Not to Scale) 13 NC 9 VSS 8 GND NC = NO CONNECT NC = NO CONNECT PIN FUNCTION DESCRIPTION Power Supplies VDD: Positive Supply, +5 V to +15 V. VSS: Negative Supply, 0 V to –15 V. GND: Digital Ground. Clock CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS. Control Inputs (All are CMOS/TTL compatible.) CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is unaffected by this control. CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to midscale (800H). If LOW, the registers are set to zero (000H). CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table. LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data must remain stable while LD is LOW. Data Input (All are CMOS/TTL compatible.) SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH. The format of the 16-bit serial word is: (FIRST) (LAST) B0 B1 B2 B3 A1 A0 NC NC —Address Word— B4 B5 B6 D11 D10 D9 (MSB) B7 B8 B9 B10 B11 B12 B13 B14 D8 D7 D6 D5 D4 D3 D2 D1 —DAC Data Word— B15 D0 (LSB) NC = Don’t Care. Reference Inputs VREFHI: Upper DAC ladder reference voltage input. Allowable range is (VDD – 2.5 V) to (VVREFLO +2.5 V). VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is VSS to (VVREFHI – 2.5 V). Analog Outputs VOUTA through VOUTD: Four buffered DAC voltage outputs. –6– REV. 0 DAC8420 Table I. Control Function Logic Table CLK1 CS 1 LD CLR CLSEL Serial Input Shift Register DAC Registers A-D NC NC NC ↑ L H H NC H H H L ↑ NC (↑) NC H H H H H H ↓ L H L L ↑ H H H H H H L H/L NC NC NC NC NC No Change No Change No Change Shifts Register One Bit Shifts Register One Bit No Change No Change No Change Loads Midscale Value (800H) Loads Zero-Scale Value (000H) Latches Value No Change No Change Loads the Serial Data Word2 Transparent3 No Change NC = Don’t Care. NOTES 1 CS and CLK are interchangeable. 2 Returning CS HIGH while CLK is HIGH avoids an additional “false clock” of serial input data. See Note 1. 3 Do not clock in serial data while LD is LOW. (000H) or midscale (800H), depending on the state of CLSEL as shown in the Digital Function Table. The CLEAR function is asynchronous and is totally independent of CS. When CLR returns HIGH, the DAC outputs remain latched at the reset value until LD is strobed, reloading the individual DAC data word registers with either the data held in the serial input register prior to the reset, or new data loaded through the serial interface. OPERATION Introduction The DAC8420 is a quad, voltage-output 12-bit DAC with serial digital input, capable of operating from a single +5 V supply. The straightforward serial interface can be connected directly to most popular microprocessors and microcontrollers, and can accept data at a 10 MHz clock rate when operating from ± 15 V supplies. A unique voltage reference structure assures maximum utilization of DAC output resolution by allowing the user to set the zero- and full-scale output levels within the supply rails. The analog voltage outputs are fully buffered, and are capable of driving a 2 kΩ load. Output glitch impulse during major code transitions is a very low 64 nV-s (typ). Table II. DAC Address Word Decode Table Digital Interface Operation The serial input of the DAC-8420, consisting of CS, SDI, and LD, is easily interfaced to a wide variety of microprocessor serial ports. As shown in Table I and the Timing Diagram, while CS is LOW the data presented to the input SDI is shifted into the internal serial/parallel shift register on the rising edge of the clock, with the address MSB first, data LSB last. The data format, shown above, is two bits of DAC address and two “don’t care” fill bits, followed by the 12-bit DAC data word. Once all 16 bits of the serial data word have been input, the load control LD is strobed and the word is parallel-shifted out onto the internal data bus. The two address bits are decoded and used to route the 12-bit data word to the appropriate DAC data register, see the Applications Information. A1 A0 DAC Addressed 0 0 1 1 0 1 0 1 DAC A DAC B DAC C DAC D Programming the Analog Outputs The unique differential reference structure of the DAC8420 allows the user to tailor the output voltage range precisely to the needs of the application. Instead of spending DAC resolution on an unused region near the positive or negative rail, the DAC8420 allows the user to determine both the upper and lower limits of the analog output voltage range. Thus, as shown in Table III and Figure 1, the outputs of DACs A through D range between VREFHI and VREFLO, within the limits specified in the Electrical Characteristics tables. Note also that VREFHI must be greater than VREFLO. Correct Operation of CS and CLK VDD As mentioned in Table I, the control pins CLK and CS require some attention during a data load cycle. Since these two inputs are fed to the same logical “OR” gate, their operation is in fact identical. The user must take care to operate them accordingly in order to avoid clocking in false data bits. As shown in the Timing Diagram, CLK must be either halted HIGH, or CS brought HIGH during the last HIGH portion of the CLK following the rising edge which latched in the last data bit. Otherwise, an additional rising edge is generated by CS rising while CLK is LOW, causing CS to act as the clock and allowing a false data bit into the serial input register. The same issue must be considered in the beginning of the data load sequence also. 2.5V MIN VVREFHI FFFH 000H –10V MIN VVREFLO 0V MIN Using CLR and CLSEL VSS The CLEAR (CLR) control allows the user to perform an asynchronous reset function. Asserting CLR loads all four DAC data word registers, forcing the DAC outputs to either zero-scale REV. 0 1 LSB 2.5V MIN Figure 1. Output Voltage Range Programming –7– DAC8420 Table III. Analog Output Code DAC Data Word (HEX) VOUT Note FFF VREFLO + (VREFHI – VREFLO ) 801 VREFLO + (VREFHI –VREFLO ) × 2049 4096 800 VREFLO + (VREFHI – VREFLO ) 7FF VREFLO + (VREFHI – VREFLO ) 000 VREFLO + (VREFHI – VREFLO ) × 4095 4096 4096 4096 4096 Full-Scale Output Midscale + 1 × 2048 Midscale × 2047 Midscale – 1 ×0 Zero Scale Typical Performance Characteristics 0.3 0.10 TA = +25°C VDD = +15V, VSS = –15V VVREFLO = –10V DD DNL – LSB DNL – LSB 0.1 0 SS = 0V 0.2 VVREFLO = 0V 0 0.1 –0.05 INL – LSB 0.2 0.3 T = +25°C A V = +5V, V 0.05 –0.10 –0.15 –0.1 0 –0.1 TA = +25°C VDD = +15V, VSS = –15V VVREFLO = –10V –0.20 –0.2 –0.2 –0.25 –4 –2 0 2 4 6 VVREFHI – V 8 10 12 –0.30 14 TA = +25°C VDD = +5V, VSS = 0V VVREFLO = 0V INL – LSB 0.1 0 –0.1 –0.2 –0.3 –0.4 1.5 2.0 2.5 3.0 VVREFHI – V 3.5 Figure 5. INL vs. VREFHI (+5 V) FULL-SCALE ERROR WITH RL = 2k Ω – LSB 0.4 0.2 2.0 2.5 3.0 3.5 –0.3 –6 VVREFHI – V Figure 2. Differential Linearity vs. VREFHI (± 15 V) 0.3 1.5 –4 –2 0 2 4 6 VVREFHI – V 8 10 12 14 Figure 3. Differential Linearity vs. VREFHI (+5 V) Figure 4. INL vs. VREFHI (± 15 V) 0.7 1.2 x + 3σ 0.5 VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.3 x 0.1 –0.1 –0.3 x – 3σ –0.5 0 200 400 600 800 1000 T = HOURS OF OPERATION AT +125°C CURVES NOT NORMALIZED Figure 6. Full-Scale Error vs. Time Accelerated by Burn-In –8– ZERO-SCALE ERROR WITH RL = 2k Ω – LSB –0.3 –6 x + 3σ 1.0 VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.8 0.6 x 0.4 0.2 x – 3σ 0 0 200 400 600 800 1000 T = HOURS OF OPERATION AT +125°C CURVES NOT NORMALIZED Figure 7. Zero-Scale Error vs. Time Accelerated by Burn-In REV. 0 DAC8420 1.2 VDD = +15V, VSS = –15V VVREFHI = +10V 1.0 VVREFLO = –10V 0 DAC A –0.1 DAC C DAC D –0.2 –0.3 DAC B –0.4 ZERO-SCALE ERROR – LSB 0.8 DAC B DAC A 0 –0.6 –75 –0.4 –75 –0.5 –0.3 –0.7 –50 –25 0 25 50 75 –0.9 100 125 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE Figure 10. Channel-to-Channel Matching ± 15/± 10 +0.8 TA = +25°C VDD = +15V, VSS = –15V VVREFLO = –10V 12 11 TA = +25, –55, 125°C VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V +0.7 +0.6 +0.5 +0.4 10 IDD – mA 0 –0.1 –0.5 13 TA = +25°C VDD = +5V, VSS = 0V VVREFHI = +2.5V VVREFLO = 0V +0.5 0.1 Figure 9. Zero-Scale Error vs. Temperature +1.5 +1.0 0.3 TEMPERATURE – °C Figure 8. Full-Scale Error vs. Temperature ERROR – LSB 0.5 DAC D 0.2 –0.2 100 125 DAC C 0.4 –0.5 0 25 50 75 –50 –25 TEMPERATURE – °C VVREFHI = +10V VVREFLO = –10V 0.6 TA = +25°C VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V 0.7 INL – LSB FULL-SCALE ERROR – LSB 0.1 0.9 VDD = +15V, VSS = –15V ERROR – ±LSB 0.2 9 8 7 –1.0 +0.3 +0.2 +0.1 0 –0.1 –0.2 6 –0.3 –1.5 5 0 4 –7 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE Figure 11. Channel-to-Channel Matching +5/+2.5 +1.5 –0.4 –5 –3 –1 0 1 3 5 7 VVREFHI – V 9 11 13 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE Figure 13. INL vs. Code ± 15/± 10 Figure 12. IDD vs. VVREFHI, All DACs HIGH 6.5mV CLR –250µV LD TA = +25°C VDD = +5V, VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V IVREFHI – mA +1.0 1.22mV +0.5 1 LSB 0mV 0 0mV –0.5 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE Figure 14. IVREFHI vs. Code REV. 0 1 LSB TA = +25°C VDD = +5V, VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V TA = +25°C VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V –10.25mV –4.9µs 5µs/DIV –1.22mV 45.1µs tSETT ≈ 8µs –3.5mV –4.9µs +5µs/DIV +45.1µs tSETT ≈ 8µs Figure 15. Settling Time (+)(± 5 V) –9– Figure 16. Settling Time (–)(± 5 V) DAC8420 +43.75mV +31.25mV LD +5V CLR TA = +25°C VDD = +15V, VSS = –15V TA = +25°C VDD = +15V, VSS = –15V VVREFHI = +10V VVREFLO = –10V VVREFHI = +10V VVREFLO = –10V +1V /DIV 0 4.88mV 1 LSB 0mV 0mV 1 LSB –4.88mV –18.75mV –9.8µs +10µs/DIV +90.2µs –6.25mV –9.8µs tSETT ≈ 13µs +10µs/DIV +90.2µs –5V –47.6µs tSETT ≈ 13µs Figure 17. Settling Time (+)(± 15 V) SRRISE = 1.65 Figure 18. Settling Time (–)(± 15 V) 20µs/DIV 152.4µs V V SRFALL = 1.17 µs µs Figure 19. Slew Rate (± 5 V) +25V 100 LD 90 +5V /DIV 0 +10 80 0 70 –10 –20 –30 TA = +25°C VDD = +15V, VSS = –15V VVREFHI = +10V, VVREFLO = –10V –25V –33.6µs 20µs/DIV 166.4µs V V SRFALL = 2.02 SRRISE = 1.9 µs µs PSRR – dB GAIN – dB CLR 10 TA = +25°C VDD = +15V, VSS = –15V VVREFHI = 0 ± 100mV VVREFLO = –10V ALL BITS HIGH 200mV p-p 100 1k 10k 100k VDD = +15V ±1V, VSS = –15V VVREFHI = +10V 10 1M 10M 0 VVREFLO = –10V 10 100 1k 10k 100k 1M FREQUENCY – Hz Figure 22. PSRR vs. Frequency 10 2 10mA/DIV VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V ALL DACS HIGH (FULL SCALE) VOUTA THROUGH VOUTD TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V DATA = 800H –4 ISS 0 75 TEMPERATURE – °C 8 VOUT PEAK – V 4 –6 –75 TA = +25°C DATA = 000H FREQUENCY – Hz IDD –2 40 20 6 0 60 50 30 Figure 21. Small-Signal Response Figure 20. Slew Rate (± 15 V) POWER SUPPLY CURRENT – mA TA = +25°C VDD = +5V, VSS = –5V VVREFHI = +2.5V VVREFLO = –2.5V 6 4 TA = +25°C VDD = +15V VSS = –15V VVREFHI = +10V VVREFLO = –10V 2 DATA = FFFH OR 000H 0 150 Figure 23. Power Supply Current vs. Temperature 5V/DIV Figure 24. DAC Output Current vs. VOUTX –10– 10 100 1k 10k LOAD RESISTANCE – Ω Figure 25. Output Swing vs. Load Resistance REV. 0 DAC8420 VREFHI Input Requirements The DAC8420 utilizes a unique, patented DAC switch driver circuit which compensates for different supply, reference voltage, and digital code inputs. This ensures that all DAC ladder switches are always biased equally, ensuring excellent linearity under all conditions. Thus, as indicated in the specifications, the VREFHI input of the DAC8420 will require both sourcing and sinking current capability from the reference voltage source. Many positive voltage references are intended as current sources only, and offer little sinking capability. The user should consider references such as the AD584, AD586, AD587, AD588, AD780, and REF43 in this application. APPLICATIONS Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The DAC8420 has a single ground pin that is internally connected to the digital section as the logic reference level. The first thought may be to connect this pin to the digital ground; however, in large systems the digital ground is often noisy because of the switching currents of other digital circuitry. Any noise that is introduced at the ground pin could couple into the analog output. Thus, to avoid error causing digital noise in the sensitive analog circuitry, the ground pin should be connected to the system analog ground. The ground path (circuit board trace) should be as wide as possible to reduce any effects of parasitic inductance and ohmic drops. A ground plane is recommended if possible. The noise immunity of the onboard digital circuitry, typically in the hundreds of millivolts, is well able to reject the common-mode noise typically seen between system analog and digital grounds. Finally, the analog and digital ground should be connected together at a single point in the system to provide a common reference. This is preferably done at the power supply. Good grounding practice is essential to maintaining analog performance in the surrounding analog support circuitry as well. With two reference inputs, and four analog outputs capable of moderate bandwidth and output current, there is a significant potential for ground loops. Again, a ground plane is recommended as the most effective solution to minimizing errors due to noise and ground offsets. 1 +VS 10µF 8 –VS 10µF VDD 0.1µF VSS GND 9 0.1µF 10µF = TANTALUM 0.1µF = CERAMIC Figure 26. Recommended Supply Bypassing Scheme REV. 0 The DAC8420 should have ample supply bypassing, located as close to the package as possible. Figure 26 shows the recommended capacitor values of 10 µF in parallel with 0.1 µF. The 0.1 µF cap should have low “Effective Series Resistance” (ESR) and “Effective Series Inductance” (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. In order to preserve the specified analog performance of the device, the supply should be as noise free as possible. In the case of 5 V only systems it is desirable to use the same 5 V supply for both the analog circuitry and the digital portion of the circuit. Unfortunately, the typical 5 V supply is extremely noisy due to the fast edge rates of the popular CMOS logic families which induce large inductive voltage spikes, and busy microcontroller or microprocessor busses which commonly have large current spikes during bus activity. However, by properly filtering the supply as shown in Figure 27, the digital 5 V supply can be used. The inductors and capacitors generate a filter that not only rejects noise due to the digital circuitry, but also filters out the lower frequency noise of switch mode power supplies. The analog supply should be connected as close as possible to the origin of the digital supply to minimize noise pickup from the digital section. FERRITE BEADS: 2 TURNS, FAIR-RITE #2677006301 TTL/CMOS LOGIC CIRCUITS 100µF ELECT. +5V 10–22µF TANT. 0.1µF CER. +5V RETURN +5V POWER SUPPLY Figure 27. Single-Supply Analog Supply Filter Analog Outputs The DAC8420 features buffered analog voltage outputs capable of sourcing and sinking up to 5 mA when operating from ± 15 V supplies, eliminating the need for external buffer amplifiers in most applications while maintaining specified accuracy over the rated operating conditions. The buffered outputs are simply an op amp connected as a voltage follower, and thus have output characteristics very similar to the typical operational amplifier. These amplifiers are short-circuit protected. The designer should verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. The DAC8420 is stable with capacitive loads up to 2 nF typical. However, any capacitive load will increase the settling time, and should be minimized if speed is a concern. The output stage includes a p-channel MOSFET to pull the output voltage down to the negative supply. This is very important in single supply systems, where VREFLO usually has the same potential as the negative supply. With no load, the zero-scale output voltage in these applications will be less than 500 µV typically, or less than 1 LSB when VVREFHI = 2.5 V. However, when sinking current this voltage does increase because of the finite impedance of the output stage. The effective value of the pull-down resistor in the output stage is typically 320 Ω. With a 100 kΩ resistor connected to +5 V, the resulting zero-scale output voltage is 16 mV. Thus, the best –11– DAC8420 single supply operation is obtained with the output load connected to ground, so the output stage does not have to sink current. DACs to synthesize symmetric bipolar wave forms, which requires an accurate, low drift bipolar reference. The AD588 provides both voltages and needs no external components. Additionally, the part is trimmed in production for 12-bit accuracy over the full temperature range without user calibration. Performing a Clear with the reset select CLSEL HIGH allows the user to easily reset the DAC outputs to midscale, or zero volts in these applications. Like all amplifiers, the DAC8420 output buffers do generate voltage noise, 52 nV/√Hz typically. This is easily reduced by adding a simple RC low-pass filter on each output. Reference Configuration The two reference inputs of the DAC8420 allow a great deal of flexibility in circuit design. The user must take care, however, to observe the minimum voltage input levels on VREFHI and VREFLO to maintain the accuracy shown in the data sheet. These input voltages can be set anywhere across a wide range within the supplies, but must be a minimum of 2.5 V apart in any case. See Figure 1. A wide output voltage range can be obtained with ± 5 V references, which can be provided by the AD588 as shown in Figure 28. Many applications utilize the When driving the reference inputs VREFHI and VREFLO, it is important to note that VREFHI both sinks and sources current, and that the input currents of both are code dependent. Many voltage reference products have limited current sinking capability and must be buffered with an amplifier to drive VREFHI, in order to maintain overall system accuracy. The input VREFLO, however, has no such requirement. +15V SUPPLY 1µF +5V VREFHI 6 7 4 0.1µF 3 1 5 RB A3 +5V DAC-8420 1 DAC A 7 VOUTA DAC B 6 VOUTB DAC C 3 VOUTC DAC D 2 VOUTD A1 AD588 14 R4 R1 A4 –5V 15 R5 R2 +15V SUPPLY +VS 2 R3 R6 0.1µF A2 SYSTEM GROUND –VS 16 5 96 10 8 12 DIGITAL CONTROL 0.1µF 11 13 10 11 12 14 15 16 –15V SUPPLY 9 4 GND 8 VREFLO –5V DIGITAL INPUTS 0.1µF –15V SUPPLY Figure 28. ± 10 V Bipolar Reference Configuration Using the AD588 –12– REV. 0 DAC8420 For a single 5 V supply, VVREFHI is limited to at most 2.5 V, and must always be at least 2.5 V less than the positive supply to ensure linearity of the device. For these applications, the REF43 is an excellent low drift 2.5 V reference that consumes only 450 µA (max). It works well with the DAC8420 in a single 5 V system as shown in Figure 29. +5V SUPPLY One opto-isolated line (LD) can be eliminated from this circuit by adding an inexpensive 4-bit TTL Counter to generate the Load pulse for the DAC8420 after 16 clock cycles. The counter is used to count of the number of clock cycles loading serial data to the DAC8420. After all 16 bits have been clocked into the converter, the counter resets, and a load pulse is generated on clock 17. In either circuit, the DAC8420’s serial interface provides a simple, low cost method of isolating the digital control. REF-43 2 VIN +5V SUPPLY HIGH VOLTAGE ISOLATION 0.1µF +5V REG 2.5V 4 GND VOUT 6 0.1µF VREFHI 1 5 +5V POWER +5V +5V REF-43 DAC A DAC-8420 7 10kΩ VOUTA 2 VIN 4 VOUT 6 GND LD 6 DAC B +5V 2.5V VOUTB +5V 10kΩ DAC C 3 10kΩ VOUTC SCLK DIGITAL CONTROL 9 2 15 CLR 1µF VOUTD 7 VOUTA 6 VOUTB 3 VOUTC 2 VOUTD DAC-8420 8 4 GND 1 VDD 16 CLSEL +5V 15 16 5 VREFHI 14 LD DAC D 10 11 12 14 0.1µF 12 CS 10kΩ 11 CLK VREFLO 10 SDI SDI DIGITAL INPUTS VREFLO VSS GND 4 Figure 29. +5 V Single Supply Operation Using REF43 8 9 Isolated Digital Interface Because the DAC8420 is ideal for generating accurate voltages in process control and industrial applications, due to noise, safety requirements, or distance, it may be necessary to isolate it from the central controller. This can be easily achieved by using opto-isolators, which are commonly used to provide electrical isolation in excess of 3 kV. Figure 30 shows a simple 3-wire interface scheme to control the clock, data, and load pulse. For normal operation, CS is tied permanently LOW so that the DAC8420 is always selected. The resistor and capacitor on the CLR pin provide a power-on reset with 10 ms time constant. The three opto-isolators are used for the SDI, CLK, and LD lines. REV. 0 Figure 30. Opto-lsolated 3-Wire Interface Dual Window Comparator Often a comparator is needed to signal an out-of-range warning. Combining the DAC8420 with a quad comparator such as the CMP04 provides a simple dual window comparator with adjustable trip points as shown in Figure 31. This circuit can be operated with either a dual or a single supply. For the A input channel, DAC B sets the low trip point and DAC A sets the upper trip point. The CMP04 has open-collector outputs that are connected together in “Wired-OR” configuration to generate an out-of-range signal. For example, when VINA goes below the trip point set by DAC B, comparator C2 pulls the output down, turning the red LED on. The output can also be used as a logic signal for further processing. –13– DAC8420 +5V SUPPLY VINA REF-43 +5V +5V SUPPLY 2 VIN 0.1µF 4 GND 0.1µF 2.5V VOUT 6 +5V 0.1µF VREFHI 5 3 1 7 DAC A DAC-8420 604Ω CMP-04 VOUTA RED LED 5 C1 2 4 6 DAC B VOUTB OUT A +5V 7 C2 1 C3 14 C4 13 604Ω 6 3 DAC C VOUTC RED LED 9 DIGITAL CONTROL OUT B 8 2 DAC D VOUTD 11 10 10 11 12 14 15 16 9 4 GND 8 VREFLO VSS 12 DIGITAL INPUTS VINB Figure 31. Dual Programmable Window Comparator MC68HC11 Microcontroller Interfacing Figure 32 shows a serial interface between the DAC8420 and the MC68HC11 8-bit microcontroller. The SCK output of the 68HC11 drives the CLK input of the DAC, and the MOSI port outputs the serial data to load into the SDI input of the DAC. The port lines PD5, PC0, PC1, and PC2 provide the controls to the DAC as shown. PC2 CLSEL PC1 CLR PC0 CS MC68HC11* DAC-8420* (PD5) SS LD SCK CLK MOSI SDI *ADDITIONAL PINS OMITTED FOR CLARITY Figure 32. MC68HC11 Microcontroller Interface For correct operation, the 68HC11 should be configured such that its CPOL bit and CPHA bit are both set to 1. In this configuration, serial data on MOSI of the 68HC11 is valid on the rising edge of the clock, which is the required timing for the DAC8420 Data is transmitted in 8-bit bytes (MSB first), with only eight rising clock edges occurring in the transmit cycle. To load data to the DAC8420’s input register, PC0 is taken low and held low during the entire loading cycle. The first 8 bits are shifted in address first, immediately followed by another 8 bits in the second least-significant byte to load the complete 16-bit word. At the end of the second byte load, PC0 is then taken high. To prevent an additional advancing of the internal shift register, SCK must already be asserted before PC0 is taken high. To transfer the contents of the input shift register to the DAC register, PD5 is then taken low, asserting the LD input of the DAC and completing the loading process. PD5 should return high before the next load cycle begins. The DAC8420’s CLR input, controlled by the output PC1, provides an asynchronous clear function. –14– REV. 0 DAC8420 DAC8420 to M68HC11 Interface Assembly Program * M68HC11 Register Definitions PORTC EQU $1003 Port C control register * “0,0,0,0;0,CLSEL,CLR,CS” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,LD,SCLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex) * To select: DAC A – Set SDI1 to $0X DAC B – Set SDI1 to $4X DAC C – Set SDI1 to $8X DAC D – Set SDI1 to $CX SDI2 is encoded from 00 (Hex) to FF (Hex) * DAC requires two 8-bit loads – Address + 12 bits SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8” SDI2 EQU $01 SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0” * Main Program ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * Initialize Port C Outputs LDAA #$07 0,0,0,0;0,1,1,1 * CLSEL-Hi, CLR-Hi, CS-Hi * To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03) * To reset DAC to MID-SCALE, set CLSEL-Hi ($07) STAA PORTC Initialize Port C Outputs LDAA #$07 0,0,0,0;0,1,1,1 STAA DDRC CLSEL, CLR, and CS are now enabled as outputs * Initialize Port D Outputs LDAA #$30 0,0,1,1;0,0,0,0 * LD-Hi,SCLK-Hi,SDI-Lo STAA PORTD Initialize Port D Outputs LDAA #$38 0,0,1,1;1,0,0,0 STAA DDRD LD,SCLK, and SDI are now enabled as outputs REV. 0 * Initialize SPI Interface LDAA #$5F STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32 * Call update subroutine BSR UPDATE Xfer 2 8-bit words to DAC-8420 JMP $E000 Restart BUFFALO * Subroutine UPDATE UPDATE PSHX Save registers X, Y, and A PSHY PSHA * Enter Contents of SDI1 Data Register (DAC# and 4 MSBs) LDAA #$80 1,0,0,0;0,0,0,0 STAA SDI1 SDI1 is set to 80 (Hex) * Enter Contents of SDI2 Data Register LDAA #$00 0,0,0,0;0,0,0,0 STAA SDI2 SDI2 is set to 00 (Hex) LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * Clear DAC output to zero BCLR PORTC,Y $02 Assert CLR BSET PORTC,Y $02 Deassert CLR * Get DAC ready for data input BCLR PORTC,Y $01 Assert CS TFRLP LDAA 0,X Get a byte to transfer via SPI STAA SPDR Write SDI data reg to start xfer WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR * (when SPIF is set, SPSR is negated) INX Increment counter to next byte for xfer CPX #SDI2+ 1 Are we done yet ? BNE TFRLP If not, xfer the second byte * Update DAC output with contents of DAC register BCLR PORTD,Y 520 Assert LD BSET PORTD,Y $20 Latch DAC register BSET PORTC,Y $01 De-assert CS PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** –15– DAC8420 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16 C1836–18–9/93 16-Pin Epoxy DIP (P Suffix) 9 0.280 (7.11) 0.240 (6.10) PIN 1 1 8 0.325 (8.25) 0.300 (7.62) 0.840 (21.33) 0.745 (18.93) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.195 (4.95) 0.115 (2.93) 16-Pin Wide-Body SOL (SOL) 9 16 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PIN 1 8 1 0.1043 (2.65) 0.0926 (2.35) 0.4133 (10.50) 0.3977 (10.00) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8° 0° 16-Pin Cerdip (Q Suffix) PRINTED IN U.S.A. 0.080 (2.03) MAX 0.005 (0.13) MIN 9 16 0.310 (7.87) 0.220 (5.59) PIN 1 8 1 0.320 (8.13) 0.290 (7.37) 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) 0.008 (0.20) 15° 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) –16– SEATING PLANE 0° REV. 0