FUJITSU SEMICONDUCTOR DATA SHEET DS04-28314-2E ASSP 3-Channel 10-Bit D/A Converter MB40950 ■ DESCRIPTION The MB40950 is a 10-bit resolution high-speed digital-to-analog converter, designed for video processing applications such as TVsets and VCRS. The MB40950 has 10-bit resolution 3 channels D/A converters. Digital data are input to the 10-bit digital input ports, and the input digital data are converted into the analog data in minimum 60 Mega sample per seconds (MSPS). The analog output voltage is provided in a range of DC +3V to +5V (2Vp-p level) . The MB40950 is fabricated by the Fujitsu’s advanced bipolar process and housed in a 48-pin plastic QFP. The MB40950 is designed for video signal processing, and it is suitable for TVS and VCRS applications. ■ FEATURES • • • • • • 10-bit x 3 channels D/A converters Max. 60 MHz input clock frequency providing 60 MSPS data conversion rate Linearity error : Max. +/-0.07% Analog output voltage range : 3V to 5V (2Vp-p level) Digital input voltage level : TTL level On-chip reference voltage generator (Continued) ■ PACKAGE 48 pin, Plastic QFP (FPT-48P-M15) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. MB40950 (Continued) • Low power consumption : – Typical 460mW at 2Vp-p analog output voltage – Typical 350mW at 1Vp-p analog output voltage • Single +5V power supply • Operating temperature range : -20°C to +70°C • Fujitsu’s advanced bipolar process • Package : 48-pin plastic QFP (Suffix : -PF) ■ PIN ASSIGNMENT D.GND A.GND VCCA 48 47 46 45 A.GND GOUT 44 43 VCCA 42 VROUT2 BOUT 41 A.GND 40 39 VRIN 38 37 CLKR 1 36 VROUT1 CLKG 2 35 COMP CLKB 3 34 VCCD R1 4 33 B10 R2 5 32 B9 31 B8 30 B7 INDEX (TOP-VIEW) R3 6 R4 7 R5 8 29 B6 R6 9 28 B5 R7 10 27 B4 R8 11 26 B3 R9 12 25 B2 (FPT-48P-M15) 13 14 15 R10 G1 G2 2 VCCA ROUT 16 17 18 19 20 21 22 23 24 G3 G4 G5 G6 G7 G8 G9 G10 B1 MB40950 ■ PIN DESCRIPTION Symbol Pin No. Type Name & Function VCCD 34 — +5V DC power supply pins for digital block. D. GND 48 — Ground pin for digital block. VCCA 41, 44, 47 — DC power supply pins for analog block. A. GND 39, 42, 45 — Ground pins for analog block. CLKR 1 I Clock input pin for R channel. CLKG 2 I Clock input pin for G channel. CLKB 3 I Clock input pin for B channel. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 4 5 6 7 8 9 10 11 12 13 I Digital data input pins for R channel. 10-bit data is input to the pins. The R1 pin is the MSB and the R10 pin is the LSB. G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 14 15 16 17 18 19 20 21 22 23 I Digital data input pins for G channel. 10-bit data is input to the pins. The G1 pin is the MSB and the G10 pin is the LSB. B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 24 25 26 27 28 29 30 31 32 33 I Digital data input pins for B channel. 10-bit data is input to the pins. The B1 pin is the MSB and the B10 pin is the LSB. Power Supply Clock Digital Input (Continued) 3 MB40950 (Continued) Symbol Pin No. Type Name & Function ROUT 46 O Analog signal output pin for R channel. GOUT 43 O Analog signal output pin for G channel. BOUT 40 O Analog signal output pin for B channel. I Reference voltage input pin. This pin is used to set the analog output dynamic range. When the internal reference voltage is used, this pin is connected with VROUT1 pin (36 pin) or VROUT2 pin (38 pin). When the reference voltage is supplied from the external generator, 2.65V to 4.3V or VCCA - VRIN = 0.7V to 2.2V is input to this pin. O Reference voltage output #1 pin. The output voltage is set to 0.6 x VCCA by the resistor divided method. When this pin is connected with VRIN pin (37 pin), an analog voltage is output from this pin in a range of 0.6 x VCCA to VCCA. O Reference voltage output #2 pin. The output voltage is set to VCCA - 2V by the band-gap reference method. When this pin is connected with VRIN pin (37 pin), an analog voltage is output from this pin in a range of VCCA - 2V to VCCA. - Phase compesation capacitor pin. A phase compesation capacitor of 0.1µF or greater is connected between this pin and A. GND pin. Analog Output Reference Voltage VRIN VROUT1 VROUT2 37 36 38 Compesation Capacitor COMP 4 35 MB40950 ■ BLOCK DIAGRAM CLKR (MSB) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 ROUT Input buffer 10 Master slave Flip-Flop 10 Buffer 10 Current switch VCCA (LSB) CLKG (MSB) G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 GOUT Input buffer 10 Master slave Flip-Flop 10 Buffer 10 Current switch VCCA (LSB) CLKB (MSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 BOUT Input buffer 10 Master slave Flip-Flop 10 Buffer 10 Current switch VCCA (LSB) Reference resistor Amp. D. GND A. GND Reference voltage #1 0.6 x VCCA Reference voltage #2 VCCA - 2V VROUT1 VROUT2 VRIN COMP VCCD VCCA 5 MB40950 ■ ABSOLUTE MAXIMUM RATINGS (A. GND = D. GND = 0V) Parameter Symbol Rating Unit Power supply voltage VCCA, VCCD –0.5 to +7.0 V Power supply voltage difference VCCD – VCCA 1.5 V Analog reference voltage VRIN –0.5 to VCCA +7.0 V Digital input voltage VID –0.5 to +7.0 V Storage temperature Tstg –55 to +125 °C Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ■ RECOMMENDED OPERATING CONDITIONS (A. GND = D. GND = 0V) Parameter Value Min. Typ. Max. Unit Power supply voltage VCCA, VCCD 4.75 5.00 5.25 V Power supply voltage difference VCCA – VCCD –0.2 — 0.2 V VCCA – VRIN 0.70 2.00 2.20 V VRIN 2.65 3.00 4.30 V Digital "H" level input voltage VIHD 2.0 — — V Digital "L" level input voltage VILD — — 0.8 V Clock frequency fCLK — — 60 MHz Setup time tSU 8.0 — — ns Hold time th 2.0 — — ns Minimum clock "H" level pulse width twH 6.5 — — ns Minimum clock "L" level pulse width twL 6.5 — — ns Phase compesation capacitance CCOMP 0.1 — — µF Operating ambient temperature TOP –20 — 70 °C Analog reference voltage 6 Symbol MB40950 ■ ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions Otherwise Noted) 1. DC Characteristics Parameter Symbol Value Min. Typ. Max. Unit Remark — Resolution — — — 10 bit Linearity error LE — — ±0.07 % DC Accuracy Differential linearity error DLE — — ±0.07 % DC Accuracy Digital "H" level input current IIHD — — 20 µA VIHD = 2.7 (V) Digital "L" level input current IILD –100 — — µA VILD = 0.4 (V) Reference input current IRIN — — 10 µA VRIN = 3.000 (V) Reference voltage (Resister divided) VROUT1 2.900 3.000 3.100 V VCCA = VCCD = 5.00 (V) Reference voltage (BGR) VROUT2 VCCA –2.100 VCCA VCCA –2.000 –1.900 V — Reference voltage (BGR) — — 100 — ppm/°C — RGB output voltage ratio FSR 0 — 6 % Full-scale output voltage VOFS VCCA –20 VCCA — mV Zero-scale output voltage VOZS 2.932 3.002 3.072 V VCCA = VCCD = 5.00 (V) VRIN = 3.000 (V) Output resistance RO 192 240 288 Ω Ta = 25°C Supply current ICC — 92* 152 mA VCCA = VCCD = 5.00 (V) — VCCA = VCCD = 5.25 (V) VRIN = VROUT1 * : VCCA = VCCD = 5.00V 2. AC Characteristics Parameter Symbol Value Min. Typ. Max. Unit Maximum conversion rate FS 60 — — MSPS Output propagation delay time tpd — 7 — ns Output rising time tr — 5 — ns Output falling time tf — 5 — ns tset — 17.5 — ns Setting time Remark Terminated A. OUT pin with 240Ω, CL = 15pF 7 MB40950 ■ AC TIMING CHART tsu th 3V 1.5V Data Input 0V tWH tWL 3V Clock Input 1.5V 0V ±1/2 LSB VOFS 90% 50% Analog Output 10% VOZS tr tf tpdLH tpdHL tsetLH tsetHL ■ DAC OUTPUT VOLTAGE RANGE Input Output R1 ~ 10 ROUT G1 ~ 10 GOUT B1 ~ 10 BOUT 1023 0 (VCCA) VOFS 5.000V 5.000V VOZS (VRIN) 3.002V 3.000V 1LSB 8 2mV ±1/2 LSB MB40950 ■ CALCULATION OF DAC OUTPUT VOLTAGE AT IDEAL CONVERSION 1023 – N ROUT (GOUT, BOUT) = VCCA – 1024 X ( VCCA – VRIN ) [ N : Digital Input Code (0 to 1023) ] VOFS = VCCA VOZS = VCCA – 1023 X ( VCCA – VRIN ) 1024 ■ TYPICAL CONNECTION EXAMPLE 5V 2.2µH 2.2µH 0.01µF 47µF VCCD Data Input R 1 to 10 G1 to 10 B1 to 10 CLK Input CLKR CLKG CLKB D. GND 47µF 0.01µF VCCA ROUT GOUT BOUT VROUT2 VRIN VROUT1 COMP A. GND Connect to VROUT1, VROUT2, or external reference voltage source. 0.1µF ■ NOTES ON USE 1. Power Supply Patterns of the PCB The power supply wire patterns (VCC and GND patterns) of the PCB should be designed as wide as possible in order to reduce parasitic impedance. 2. Switching Noise In order to reduce switching noise as much as possible, noise limit capacitor must be connected between VCCD and D. GND pins and VCCA and A. GND pins. In this case, the capacitor should be connected to the GND pins side as near as possible. 9 MB40950 ■ PACKAGE DIMENSION 48 pin, Plastic QFP (FPT-48P-M15) 36 15.30±0.40 SQ (.602±.016) +0.30 12.00 –0.10 SQ +.012 .472 –.004 2.70(.106)MAX 0.05(.002)MIN (STAND OFF) 25 37 Details of "A" part 24 0.15(.006) 8.80 (.346) REF 13.60±0.40 (.535±.016) 0.20(.008) 0.15(.006)MAX INDEX 0.50(.020)MAX 48 13 "A" Details of "B" part LEAD No. 1 0.80(.0315)TYP 12 +0.05 0.30±0.06 (.012±.002) 0.16(.006) "B" M 0.15 –0.01 +.002 .006 –.0004 0~10° 0.85±0.30 (.033±.012) 0.10(.004) C 10 1994 FUJITSU LIMITED F48025S-1C-1 Dimensions in mm (inches). MB40950 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 FUJITSU LIMITED 12 Printed in Japan