Dual Output Synchronous Buck PWM Controller With Tracking ADP1877 VIN RAMP1 RAMP1 EN1 EN2 VDL VCCO PGOOD1 PGOOD2 TRK1 TRK2 SYNC FREQ COMP2 SS1 SS2 AGND Set top boxes Printers Communication infrastructure Distributor power dc systems Industrial and instrumentation The ADP1877 includes externally adjustable soft start, output overvoltage protection, externally adjustable current limit, power good, and a programmable oscillator frequency that ranges from 200 kHz to 1.5 MHz. The ADP1877 provides an L1 SW1 ILIM1 FB1 RTOP1 VOUT1 M2 RBOT1 DL1 RCSG1 PGND1 RRAMP2 VIN RAMP2 DH2 BST2 L2 SW2 ILIM2 FB2 RTOP2 VOUT2 M4 DL2 RBOT2 RCSG2 PGND2 Figure 1. Typical Operation Circuit 1.0 VO = 3.3V PSM 0.9 GENERAL DESCRIPTION The boost diodes are built into the ADP1877, thus lowering the overall system cost and component count. The ADP1877 can be set to operate in pulse skip high efficiency mode under light load or in PWM continuous conduction mode. M1 DH1 BST1 M3 COMP1 APPLICATIONS 0.8 VO = 1.8V PSM 0.7 EFFICIENCY The ADP1877 is a Flexmode® (proprietary architecture of Analog Devices, Inc.), dual-channel, step-down switching controller with integrated drivers that drive N-channel synchronous power MOSFETs. The two PWM outputs are phase shifted 180°, which reduces the input RMS current, thus minimizing required input capacitance. VIN 08299-001 Input voltage range: 2.75 V to 14.5 V Output voltage range: 0.6 V to 0.9 V Maximum output current 20 A or higher per channel Programmable frequency: 200 kHz to 1.5 MHz Flexmode® architecture with integrated drivers 180° phase shift minimizes input ripple current and required input capacitance ±0.85% output voltage accuracy 0°C to 70°C Integrated boost diodes Pulse skip high efficiency mode under light load Power good with internal pull-up resistor Overvoltage and overcurrent limit protection Thermal overload protection Input undervoltage lockout (UVLO) Externally adjustable soft start, slope compensation and current sense gain Independent precision enable inputs Synchronization input Suitable for any output capacitors Available in 32-lead 5 mm × 5 mm LFCSP output voltage accuracy of ±0.85% from 0°C to 85°C and ±1.5% from −40°C to 125°C in junction temperature. This part can be powered from a 2.75 V to 14.5 V supply, operates over the −40oC to +125oC junction temperature range, and is available in a 32-lead 5 mm × 5 mm LFCSP package. VO = 3.3V PWM 0.6 0.5 VO = 1.8V PWM 0.4 0.3 0.2 0.1 0 0.01 VIN = 12V, 300kHz 0.1 1 10 LOAD (A) 100 08299-002 FEATURES Figure 2. Efficiency Plot of Figure 42, 20 A Output Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP1877 TABLE OF CONTENTS Features .............................................................................................. 1 Setting the Current Limit .......................................................... 17 Applications ....................................................................................... 1 Accurate Current Limit Sensing ............................................... 17 General Description .......................................................................... 1 Setting the Slope Compensation .............................................. 18 Revision History ............................................................................... 2 Setting the Current Sense Gain ................................................ 18 Specifications..................................................................................... 3 Input Capacitor Selection .......................................................... 19 Absolute Maximum Ratings............................................................ 6 Input Filter................................................................................... 19 ESD Caution .................................................................................. 6 Boost Capacitor Selection ......................................................... 20 Simplified Block Diagram ............................................................... 7 Inductor Selection ...................................................................... 20 Pin Configuration and Function Descriptions ............................. 8 Output Capacitor Selection....................................................... 20 Typical Performance Characteristics ........................................... 10 MOSFET Selection ..................................................................... 21 Theory of Operation ...................................................................... 13 Loop Compensation .................................................................. 22 Control Architecture .................................................................. 13 Switching Noise and Overshoot Reduction ............................ 23 Oscillator Frequency .................................................................. 13 Voltage Tracking ......................................................................... 23 Mode of Operation ..................................................................... 14 Coincident Tracking .................................................................. 23 Synchronization .......................................................................... 14 Ratiometric Tracking ................................................................. 24 Soft Start ...................................................................................... 14 PCB Layout Guideline ................................................................... 25 Synchronous Rectifier and Dead Time ................................... 15 MOSFETs, Input Bulk Capacitor, and Bypass Capacitor ...... 25 Input Undervoltage Lockout ..................................................... 15 High Current and Current Sense Paths ................................... 25 Internal Linear Regulator .......................................................... 15 Signal Paths ................................................................................. 25 Overvoltage Protection .............................................................. 15 PGND Plane ................................................................................ 25 Power Good................................................................................. 15 Feedback and Current Limit Sense Paths ............................... 25 Short Circuit and Current Limit Protection ........................... 16 Switch Node ................................................................................ 26 Shutdown Control ...................................................................... 16 Gate Driver Paths ....................................................................... 26 Thermal Overload Protection................................................... 16 Output Capacitors ...................................................................... 26 Applications Information .............................................................. 17 Typical Operating Circuits ............................................................ 27 Setting the Output Voltage ........................................................ 17 Outline Dimensions ....................................................................... 31 Soft Start ...................................................................................... 17 Ordering Guide .......................................................................... 31 REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 32 ADP1877 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1. Parameter POWER SUPPLY Input Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Quiescent Current Symbol VIN INUVLO IIN Shutdown Current ERROR AMPLIFIER FB Input Bias Current Transconductance IFB Gm TRK1, TRK2 Input Bias Current CURRENT SENSE AMPLIFIER GAIN ITRK ACS OUTPUT CHARACTERICTISTICS Feedback Accuracy Voltage Line Regulation of PWM Load Regulation of PWM OSCILLATOR Frequency SYNC Input Frequency Range SYNC Input Pulse Width SYNC Pin Capacitance to GND LINEAR REGULATOR VCCO Output Voltage VCCO Load Regulation VCCO Line Regulation VCCO Current Limit1 VCCO Short-Circuit Current1 VIN to VCCO Dropout Voltage2 IIN_SD VFB ΔVFB/ΔVIN ΔVFB/ΔVCOMP fOSC fSYNC Conditions Min VIN rising VIN falling 2.75 2.45 2.4 TJ = 0°C to +70°C, VFB = 0.6 V TJ = −40°C to +125°C, VFB = 0.6 V tSYNCMIN CSYNC VDROPOUT Units 14.5 2.75 2.6 V V 5 V mA 100 200 μA −100 440 385 −100 2.4 +1 550 550 +1 3 +100 660 715 +100 3.6 nA μs μs nA V/V 5.2 6 6.9 V/V 10.5 20.5 12 24 13.5 26.5 V/V V/V −0.85% −1.5% +0.6 +0.6 ±0.015 ±0.3 +0.85% +1.5% V V %/V % 170 744 1275 235 475 400 200 800 1500 300 600 235 856 1725 345 690 3000 kHz kHz kHz kHz kHz kHz VCOMP range 0.9 V to 2.2 V RFREQ = 340 kΩ to AGND RFREQ = 78.7 kΩ to AGND RFREQ = 39.2 kΩ to AGND FREQ to AGND FREQ to VCCO fSYNC = 2 × fsw; fSYNC = fOSC; the minimum sync frequency is 1 × the fOSC set by the resistor Max 2.6 2.5 0.1 4.5 EN1 = EN2 = VIN = 12 V, VFB = VCCO in PWM mode (no switching) EN1 = EN2 = GND, VIN = 5.5 V or 14.5 V Sink or source 1 μA, TA = 25 oC Sink or source 1 μA 0 V < VTRK1/TRK2 < 1.5 V Gain resistor connected to DL, RCSG = 47 kΩ ± 5% Gain resistor connected to DL, RCSG = 22 kΩ ± 5% Default setting, RCSG = open Gain resistor connected to DL, RCSG = 100 kΩ ± 5% Typ 100 ns pF 5 TA = 25°C, IVCCO = 100 mA TJ = −40°C to +125°C IVCCO = 0 mA to 100 mA, VIN = 5.5 V to 14.5 V, IVCCO = 20 mA VCCO drops to 4 V from 5 V VCCO < 0.5 V IVCCO = 100 mA, VIN ≤ 5 V Rev. 0 | Page 3 of 32 4.8 4.7 5.0 5.0 35 10 350 370 0.33 5.18 5.3 75 400 0.45 V V mV mV mA mA V ADP1877 Parameter LOGIC INPUTS EN1, EN2 EN1, EN2 Hysteresis EN1, EN2 Input Leakage Current SYNC Logic Input Low SYNC Logic Input High SYNC Input Leakage Current GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH to DL Dead Time DH or DL Driver RON, Sourcing Current1 Symbol DH or DL Driver RON, Tempco DH or DL Driver RON, Sinking Current1 DH Maximum Duty Cycle DH Maximum Duty Cycle Minimum DH On Time Minimum DH Off Time Minimum DL On Time COMP VOLTAGE RANGE COMP Pulse Skip Threshold COMP Clamp High Voltage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis OVERVOLTAGE AND POWER GOOD THRESHOLDS FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis TRK INPUT VOLTAGE RANGE FB TO TRK OFFSET VOLTAGE SOFT START SS Output Current SS Pull-Down Resistor Conditions Min Typ Max Units EN1/EN2 rising 0.57 0.63 0.03 1 0.68 V V nA V V μA IEN VIN = 2.75 V to 14.5 V 200 1.3 ISYNC SYNC = 5 V, internal 1 MΩ pull-down 5 RON_SOURC CDH = 3 nF, VBST − VSW = 5 V CDH = 3 nF, VBST − VSW = 5 V CDL = 3 nF CDL = 3 nF External 3 nF is connected to DH and DL Sourcing 2 A with a 100 ns pulse 16 14 16 14 25 2 ns ns ns ns ns Ω TCRON RON_SINK Sourcing 1 A with a 100 ns pulse, VIN = 3 V VIN = 3 V or 12 V Sinking 2 A with a 100 ns pulse 2.3 0.3 1.5 Ω %/oC Ω 2 Ω % % ns ns ns 1.9 Sinking 1 A with a 100 ns pulse, VIN = 3 V fOSC = 300 kHz fOSC = 1500 kHz fOSC = 200 kHz to 1500 kHz fOSC = 200 kHz to 1500 kHz fOSC = 200 kHz to 1500 kHz VCOMP,THRES VCOMP,HIGH 90 50 130 330 280 In pulse skip mode 0.9 V V 155 20 °C °C 2.25 TTMSD VOV VFB rising 0.67 VUV VFB rising 0.51 TRK = 0.5 V to 0.6 V; offset = VFB − VTRK 0 −120 ISS 6.5 During start-up During a fault condition Rev. 0 | Page 4 of 32 4.6 0.7 40 0.54 30 −70 6.5 1 0.73 0.57 5 −25 8.4 V mV V mV V mV μA kΩ ADP1877 Parameter PGOOD PGOOD Pull-up Resistor PGOOD Delay Overvoltage or Undervoltage Minimum Duration ILIM1, ILIM2 Threshold Voltage1 ILIM1, ILIM2 Output Current Current Sense Blanking Period INTEGRATED RECTIFIER (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET (SW TO PGND)1 1 2 Symbol Conditions RPGOOD Internal pull-up resistor to VCCO Min Typ Max 12.5 12 12 This is the minimum duration required to trip the PGOOD signal. Relative to PGND ILIM = PGND After DL goes high, current limit is not sensed during this period. At 20 mA forward current −5 40 In pulse skip mode only; fOSC = 600 kHz 0 0 50 100 kΩ μs μs +5 60 16 2 Units mV μA ns Ω 4 mV Guaranteed by design. Connect VIN to VCCO when VIN < 5.5 V. For applications with VIN < 5.5 V and VIN not connected to VCCO, keep in mind that VCCO = VIN − VDROPOUT. VCCO must be ≥ 2.75 V for proper operation. Rev. 0 | Page 5 of 32 ADP1877 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, EN1/EN2, RAMP1/RAMP2 FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1/TRK2, FREQ, SYNC, VCCO, VDL, PGOOD1/PGOOD2 ILIM1/ILIM2 BST1/BST2, DH1/DH2, SW1/SW2 to PGND1/PGND2 DL1/DL2 to PGND1/PGND2 BST1/BST2 to PGND1/PGND2, SW1/SW2 to PGND1/PGND2 20 ns Transients DL1/DL2, SW1/SW2, ILIM1/ILIM2 to PGND1/PGND2 20 ns Negative Transients PGND1/PGND2 to AGND PGND1/PGND2 to AGND 20 ns Transients θJA, =on a Multilayer PCB (Natural Convection)1, 2 Operating Ambient Temperature Range3 Operating Junction Temperature Range3 Storage Temperature Range Maximum Soldering Lead Temperature Rating 15 V −0.3 V to +6 V −0.3 V to +16 V −0.3 V to +22 V −0.3 V to VCCO + 0.3 V +25 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND. ESD CAUTION −8 V −0.3 V to +0.3 V −8 V to +4 V 32.6°C/W −40°C to +85°C −40°C to +125°C −65°C to +150°C 260°C 1 Measured with exposed pad attached to PCB. Junction-to-ambient thermal resistance (θJA) of the package was calculated or simulated on a multilayer PCB. 3 The device can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature, TJ, of the device is dependent on the ambient temperature, TA, the power dissipation of the device, PD, and the junction to ambient thermal resistance of the package, θJA. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula TJ = TA + PD × θJA. 2 Rev. 0 | Page 6 of 32 ADP1877 SIMPLIFIED BLOCK DIAGRAM VIN THERMAL SHUTDOWN VCCO AGND UVLO 0.6V EN1_SW EN2_SW LOGIC + – EN1 OV 0.6V UV REF LDO + EN2 VCCO – OV1 LOGIC SYNC UV1 PH1 1MΩ FREQ COMP1 FB1 TRK1 SS1 FB1 0.6V – + + Gm + PGOOD1 + – OV ERROR AMPLIFIER 10kΩ DUPLICATE FOR CHANNEL 2 PH2 OSCILLATOR + – UV VCCO BST1 SYNC EN1_SW VREF = 0.6V – 6.5µA FAULT 1kΩ 3.2V LOGIC 0.9V OV1 EN1 OVER_LIM1 DH1 DRIVER LOGIC CONTROL AND STATE MACHINE OVER_LIM1 OV1 SW1 PULSE SKIP + – DCM + PWM COMPARATOR ZERO CROSS DETECT VDL + – DL1 CS GAIN RAMP1 DL DRIVER – AV = 3, 6, 12, 24 SLOPE COMP AND RAMP GENERATOR + + – CURRENT SENSE AMPLIFIER 50µA ILIM1 08299-003 CURRENT LIMIT OVER_LIM1 CONTROL PGND1 VCCO Figure 3. Block Diagram Rev. 0 | Page 7 of 32 ADP1877 32 31 30 29 28 27 26 25 TRK1 FB1 COMP1 RAMP1 SS1 PGOOD1 ILIM1 BST1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADP1877 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 DH1 PGND1 DL1 DL2 PGND2 DH2 SW2 NOTES 1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE. 08299-004 TRK2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 EN1 SYNC VIN VCCO VDL AGND FREQ EN2 Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic EN1 2 SYNC 3 VIN 4 VCCO 5 VDL 6 7 AGND FREQ 8 EN2 9 TRK2 10 11 FB2 COMP2 12 RAMP2 13 SS2 14 PGOOD2 Description Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND, and tie the midpoint to this pin. Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator frequency, fOSC, set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip mode. Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as possible and PGND. Output of the Internal Linear Dropout Regulator (LDO). The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even during fault conditions and cannot be turned off even if EN1/EN2 is low. For operations at VIN below 5 V, VIN can be jumped to VCCO. Do not use the LDO to power other auxiliary system loads. Power Supply for the Low-Side Driver. Bypass VDL to PGND with a 1 μF or greater ceramic capacitor. Connect VCCO to VDL. Analog Ground. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. See Table 4 for more details. Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for a 600 kHz operating frequency. Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND, and tie the midpoint to this pin. Tracking Input for Channel 2. If the tracking function is not used, it is recommended to connect TRK2 to VCCO through a resistor higher than 1 MΩ, or simply connect TRK2 between 0.7 V and 2 V to reduce the bias current going into the TRK2 pin. Output Voltage Feedback for Channel 2. Connect to Channel 2 via a resistor divider. Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor network from COMP2 to AGND to compensate the regulation control loop. Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The voltage at RAMP2 is 0.2 V. Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is internally pulled up to 3.2 V through a 6.5 μA current source. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An external pull-up resistor is not required. Rev. 0 | Page 8 of 32 ADP1877 Pin No. 15 Mnemonic ILIM2 16 BST2 17 SW2 18 DH2 19 PGND2 20 DL2 21 DL1 22 PGND1 23 DH1 24 SW1 25 BST1 26 ILIM1 27 PGOOD1 28 SS1 29 RAMP1 30 COMP1 31 32 FB1 TRK1 33 Bottom exposed pad Description Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source of the low-side MOSFET. Boot Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a 0.1 μF to a 0.22 μF multilayer ceramic capacitor (MLCC) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2. Switch Node for Channel 2. Connect to the source of the high-side N-channel MOSFET and the drain of the lowside N-channel MOSFET of Channel 2. High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up to 20 nF. Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2 and PGND2. It is not recommended to short PGND2 to PGND1 directly. Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier, connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier, connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1 and PGND1. It is not recommended to short PGND2 to PGND1 directly. High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Power Switch Node for Channel 1. Connect to the source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET of Channel 1. Boot Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a 0.1 μF to a 0.22 μF multilayer ceramic capacitor (MLCC) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL and BST1. Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source of the low-side MOSFET. Power Good. Open drain power good indicator logic output with an internal 12 kΩ resistor connected between PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window. An external pull-up resistor is not required. Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is internally pulled up to 3.2 V through a 6.5 μA current source. Programmable Current Setting for Slope Compensation of Channel 1. Connect a resistor from RAMP1 to VIN. The voltage at RAMP1 is 0.2 V during operation. This pin is high impedance when the channel is disabled. Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor network from COMP1 to AGND to compensate the regulation control loop. Output Voltage Feedback for Channel 1. Connect to Channel 1 via a resistor divider. Tracking Input for Channel 1. If the tracking function is not used, it is recommended to connect TRK1 to VCCO through a resistor higher than 1 MΩ, or simply connect TRK1 between 0.7 V and 2 V to reduce the bias current going into the TRK1 pin. Connect the bottom exposed pad of the LFCSP package to the system AGND plane. Rev. 0 | Page 9 of 32 ADP1877 TYPICAL PERFORMANCE CHARACTERISTICS 0.06 1.0 VOUT = 3.3V AT 1A LOAD 0.9 PSM LINE REGULATION (%) EFFICIENCY 0.7 0.6 PWM 0.5 0.4 0.3 0.2 0.1 1 100 10 0.02 LOAD (A) 0 08299-023 0 0.01 0.03 0.01 VIN = 12V VOUT = 3.3V 600kHz 0.1 0.04 6 14 0 0.8 –0.05 VOUT = 1.05V PSM 0.7 0.6 Δ VCCO (V) EFFICIENCY 12 Figure 8. Line Regulation of Figure 42 VIN = 3V VOUT = 1.8V PWM 0.9 10 VIN (V) Figure 5. Efficiency Plot of Figure 41, 10 A Output 1.0 8 08299-026 0.8 0.05 0.5 VOUT = 1.8V PSM 0.4 –0.10 50mA LOAD –0.15 PWM VO = 1.05V 1.05V_PWM 0.3 100mA LOAD 0.2 –0.20 0.1 1 10 LOAD (A) –0.25 2.5 08299-024 0 0.01 3.0 5.0 5.10 VIN = 12V VOUT = 3.3V 5.05 0.3 NO LOAD ON LDO 5.00 100mA LOAD ON LDO 0.2 4.95 VCCO (V) 0.1 0 –0.1 4.90 4.85 –0.3 4.75 –0.4 4.70 0 5 10 15 LOAD (A) 20 Figure 7. Load Regulation of Figure 42 4.65 5 7 9 11 13 VIN (V) Figure 10. LDO Line Regulation Rev. 0 | Page 10 of 32 15 17 08299-028 4.80 –0.2 08299-025 LOAD REGULATION (%) 4.5 Figure 9. LDO Load Regulation 0.5 –0.5 4.0 VIN (V) Figure 6. Efficiency Plot of Figure 44, 2 A Output 0.4 3.5 08299-027 0.1 ADP1877 6 5 OUTPUT RESPONSE 1 VCCO (V) 4 3 OUTPUT STEP LOAD 0.5A TO 0.8A 2 4 1 0 1 2 3 4 5 6 VIN (V) CH1 20mV 08299-029 0 Figure 11. VCCO vs. VIN CH4 500mA Ω M100µs A CH4 750mA 08299-037 VIN = 3V VOUT = 1.8V Figure 14. Step Load Transient of Figure 44 SW1 1 DH1 1 SW2 DL1 2 2 VOUT1 3 3 IL1 4 SYNC 600kHz CH2 10V M1µs A CH1 5.60V CH1 5V CH3 1V Figure 12. An Example of Synchronization, fSW = 600 kHz CH2 5V CH4 1A Ω M1ms A CH1 2.4V 08299-038 CH1 10V CH3 5V 08299-035 VIN = 12V VOUT = 1.8V OUTPUT PRECHARGED TO 1V Figure 15. Soft Start into Precharged Output EN IS TIED TO VIN CSS = 100nF VIN POWER SUPPLY VOUT (CH2) OUTPUT RESPONSE 1 1 SS 5A TO 10A STEP LOAD SW 2 4 4 A CH4 8.10A CH4 5A Ω 08299-036 M200µs CH1 50mV CH1 5V CH3 10V Figure 13. Step Load Transient of Figure 42, 5 A to 10 A CH2 1V CH4 500mV M2ms A CH2 Figure 16. Power-On Sequence Rev. 0 | Page 11 of 32 2.42V 08299-039 3 VIN = 12V VOUT = 1.8V ADP1877 2.0 VIN = 12V; REFERENCED AT 25°C 1.5 1.0 CHANGE IN fOSC (%) SW VOUT (CH3) EN CH2 2V CH4 1V M10ms A CH2 1.52V –1.0 –2.5 –40 08299-040 CH1 10V –0.5 –2.0 CSS = 100nF CH3 1V 0 –1.5 SS (CH4) 3 2 4 0.5 –15 10 35 60 85 110 135 TEMPERATURE (°C) Figure 17. Enable Function 08299-031 1 Figure 20. fOSC vs. Temperature 350 SW1 300 1 DH MINIMUM OFF TIME PGOOD1 TIME (ns) 250 VCCO (CH3) 2 150 VOUT, PRELOADED (CH4) 3 200 DH MINIMUM ON TIME CH2 2V CH4 2V Ω CH3 2V M10ms A CH2 3.76V 50 2.5 CHANGE IN MINIMUM ON/OFF TIME (%) 300kHz –1.5 –2.5 850kHz 2 4 6 8 10 VIN (V) 12 14 08299-030 CHANGE IN fOSC (%) 600kHz –2.0 10.5 12.5 14.5 135 4 0 –1.0 8.5 Figure 21. Typical DH Minimum On Time and Off Time REFERENCE AT VIN = 2.75V –0.5 6.5 VIN (V) Figure 18. Thermal Shutdown Waveform 0.5 4.5 08299-032 CH1 10V 08299-041 4 08299-033 100 Figure 19. Change in fOSC vs. VIN 3 DH MINIMUM OFF TIME 2 1 DH MINIMUM ON TIME 0 –1 –2 –3 –4 –40 –15 10 35 60 85 110 TEMPERATURE (°C) Figure 22. DH Minimum On Time and Off Time Overtemperature Rev. 0 | Page 12 of 32 ADP1877 THEORY OF OPERATION The ADP1877 is a current mode (using ADI proprietary FlexMode® architecture), dual-channel, step-down switching controller with integrated MOSFET drivers that drive N-channel synchronous power MOSFETs. The two outputs are phase shifted 180°. This reduces the input RMS current, thus minimizing required input capacitance. The ADP1877 can be set to operate in pulse skip high efficiency mode under light load or in forced PWM. The integrated boost diodes in the ADP1877 reduce the overall system cost and component count. The ADP1877 includes programmable soft start, output overvoltage protection, programmable current limit, power good, and tracking function. The ADP1877 can be set to operate in any switching frequency between 200 kHz and 1.5 MHz with one external resistor. CONTROL ARCHITECTURE The ADP1877 is based on a fixed frequency current mode PWM control architecture. The inductor current is sensed by the voltage drop measured across the external low-side MOSFET RDSON during the off period of the switching cycle (valley inductor current). The current sense signal is further processed by the current sense amplifier. The output of the current sense amplifier is held, and the emulated current ramp is multiplexed and fed into the PWM comparator as shown in Figure 23. The valley current information is captured at the end of the off period, and the emulated current ramp is applied at that point when the next on cycle begins. An error amplifier integrates the error between the feedback voltage and the generated the error voltage from the COMP pin (from error amp in Figure 23). OSC VIN Q FF RRAMP IRAMP S R OSCILLATOR FREQUENCY The internal oscillator frequency, which ranges from 200 kHz to 1.5 MHz, is set by an external resistor, RFREQ, at the FREQ pin. Some popular fOSC values are shown in Table 4, and a graphical relationship is shown in Figure 24. For instance, a 78.7 kΩ resistor sets the oscillator frequency to 800 kHz. Furthermore, connecting FREQ to AGND or FREQ to VCCO sets the oscillator frequency to 300 kHz or 600 kHz, respectively. For other frequencies that are not listed in Table 4, the values of RFREQ and fOSC can be obtained from Figure 24, or use the following empirical formula to calculate these values: RFREQ (kΩ) = 96568 × fOSC (kHz)−1.065 Table 4. Setting the Oscillator Frequency RFREQ 332 kΩ 78.7 kΩ 60.4 kΩ 51 kΩ 40.2 kΩ FREQ to AGND FREQ to VCCO 410 RFREQ (kΩ) = 96568 fOSC (kHz)–1.065 TO DRIVERS 360 Q 310 RFREQ (kΩ) AR CR FROM ERROR AMP ACS FROM LOW SIDE MOSFET 260 210 160 110 08299-005 VCS fOSC (Typical) 200 kHz 800 kHz 1000 kHz 1200 kHz 1500 kHz 300 kHz 600 kHz 60 10 100 Figure 23. Simplified Control Architecture As shown in Figure 23, the emulated current ramp is generated inside the IC but offers programmability through the RAMPx pin. Selecting an appropriate value resistor from VIN to the RAMP pin programs a desired slope compensation value and, at the same time, provides a feed forward feature. The benefits realized by deploying this type of control scheme are that there is no need to worry about the turn-on current spike corrupting the current ramp. Also, the current signal is stable because the current signal is sampled at the end of the turn-off period, which gives time for the switch node ringing to settle. Other Rev. 0 | Page 13 of 32 400 700 1000 1300 fOSC (kHz) Figure 24. RFREQ vs. fOSC 1600 1900 08299-034 VIN benefits of using current mode control scheme still apply, such as simplicity of loop compensation. Control logic enforces antishoot-through operation to limit cross conduction of the internal drivers and external MOSFETs. ADP1877 MODE OF OPERATION The SYNC pin is a multifunctional pin. PWM mode is enabled when SYNC is connected to VCCO or a high logic. With SYNC connected to ground or left floating, pulse skip mode is enabled. Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or pulse skip mode to forced PWM, respectively, in two clock cycles. DH1 1 DL1 2 OUTPUT RIPPLE 3 Table 5. Mode of Operation Truth Table Mode of Operation Pulse skip mode Forced PWM Pulse skip mode Forced PWM 4 INDUCTOR CURRENT CH1 10V CH3 20mV SW1 1 COMP1 (CH2) VOUT RIPPLE 2 CH1 10V CH3 20mV CH2 200mV CH4 2A Ω M200µs A CH1 7.8V 08299-042 INDUCTOR CURRENT 4 M1µs A CH1 13.4V Figure 26. Example of Discontinuous Conduction Mode (DCM) Waveform The ADP1877 has a built-in pulse skip sensing circuitry that allows the controller to skip PWM pulses, thus reducing the switching frequency at light loads and, therefore, maintaining high efficiency during a light load operation. The switching frequency is a fraction of the natural oscillator frequency and is automatically adjusted to regulate the output voltage. The resulting output ripple is larger than that of the fixed frequency forced PWM. Figure 25 shows that the ADP1877 operates in PSM under a light load of 10 mA. Pulse skip frequency under a certain light load is dependent on the inductor input and output voltages. 3 CH2 5V CH4 2A Ω 08299-043 SYNC Pin Low High No Connect Clock Signal Figure 25. Example of Pulse Skip Mode Under a Light 5 mA Load When the output load is greater than the pulse skip threshold current (when VCOMP reaches the threshold of 0.9 V), the ADP1877 exits the pulse skip mode operation and enters the fixed frequency discontinuous conduction mode (DCM), as shown in Figure 26. When the load increases further, the ADP1877 enters CCM. In forced PWM, the ADP1877 always operates in CCM at any load. The inductor current is always continuous (and even goes negative when there is no load); thus, efficiency is poor at light loads. SYNCHRONIZATION The switching frequency of the ADP1877 can be synchronized to an external clock by connecting SYNC to a clock signal, which should be between 1× and 2.3× of the internal oscillator frequency, fOSC. The resulting switching frequency, fSW, is ½ of the external SYNC frequency because the SYNC input is divided by 2, and the resulting phases are used to clock the two channels alternately. In synchronization, the ADP1877 operates in PWM, and fSW equals ½ of fSYNC. When an external clock is detected at the first SYNC edge, the internal oscillator is reset, and the clock control shifts to SYNC. The SYNC edges then trigger subsequent clocking of the PWM outputs. The DH1/DH2 rising edges appear approximately 100 ns after the corresponding SYNC edge, and the frequency is locked to the external signal. Depending on the start-up conditions of Channel 1 and Channel 2, either Channel 1 or Channel 2 can be the first channel synchronized to the rising edge of the SYNC clock. If the external SYNC signal disappears during operation, the ADP1877 reverts to its internal oscillator. When the SYNC function is used, it is recommended to connect a pull-up resistor from SYNC to VCCO so that when the SYNC signal is lost, the ADP1877 continues to operate in PWM. SOFT START The soft start period is set by an external capacitor between SS1/SS2 and AGND. When EN1/EN2 is enabled, a current source of 6.5 μA starts charging the capacitor, and the regulation voltage is reached when the voltage at SS1/SS2 reaches 0.6 V. For more information, see the Applications Information section. Rev. 0 | Page 14 of 32 ADP1877 VIN = 2.75V TO 5.5V SYNCHRONOUS RECTIFIER AND DEAD TIME When the bias input voltage, VIN, is less than the undervoltage lockout (UVLO) threshold, the switch drivers stay inactive. When VIN exceeds the UVLO threshold, the switchers start switching. INTERNAL LINEAR REGULATOR The internal linear regulator is low dropout (LDO), meaning it can regulate its output voltage, VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers. It is guaranteed to have more than 200 mA of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETs driven at up to 1.5 MHz. VCCO is always active and cannot be shut down by the EN1/EN2 pins. Bypass VCCO to AGND with a 1 μF or greater capacitor. ADP1877 Figure 27. Configuration for VIN < 5.5 V OVERVOLTAGE PROTECTION The ADP1877 has a built-in circuit for detecting output overvoltage at the FB node. When the FB voltage, VFB, rises above the overvoltage threshold, the low-side NMOSFET is immediately turned on, and the high-side NMOSFET is turned off until the VFB drops below the undervoltage threshold. This action is known as the crowbar overvoltage protection. If the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the output is regulated to within approximately +16% and −10% of the regulation voltage. During an overvoltage event, the SS node discharges toward zero through an internal 1 kΩ pull-down resistor. When the voltage at FB drops below the undervoltage threshold, the soft start sequence restarts. The following graph shows the overvoltage protection scheme in action in PSM. The VDL pin provides power to the low-side driver. Connect VDL to VCCO. Bypass VDL to PGND with a 1 μF (minimum) ceramic capacitor, which must be placed close to the VDL pin. For an input voltage less than 5.5 V, it is recommended to bypass the LDO by connecting VIN to VCCO, as shown in Figure 27, thus eliminating the dropout voltage. However, for example, if the input range is 4 V to 7 V, the LDO cannot be bypassed by shorting VIN to VCCO because the 7 V input has exceeded the maximum voltage rating of the VCCO pin. In this case, use the LDO to drive the internal drivers, but keep in mind that there is a dropout when VIN is less than 5 V. DH1 1 PGOOD1 2 VO1 = 1.8V SHORTED TO 2.2V SOURCE Because the LDO supplies the gate drive current, the output of VCCO is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the VCCO output for other external auxiliary system load is not recommended. The LDO includes a current limit well above the expected maximum gate drive load. This current limit also includes a short-circuit fold back to further limit the VCCO current in the event of a short-circuit fault. VCCO VIN (CH3) 3 4 CH1 10V CH3 5V CH2 5V CH4 500mV M200µs A CH4 2.05V 08299-044 INPUT UNDERVOLTAGE LOCKOUT VIN 08299-006 The synchronous rectifier (low-side MOSFET) improves efficiency by replacing the Schottky diode that is normally used in an asynchronous buck regulator. In the ADP1877, the antishootthrough circuit monitors the SW and DL nodes and adjusts the low-side and high-side drivers to ensure break-before-make switching to prevent cross-conduction or shoot-through between the high-side and low-side MOSFETs. This break-before-make switching is known as the dead time, which is not fixed and depends on how fast the MOSFETs are turned on and off. In a typical application circuit that uses medium sized MOSFETs with input capacitance of approximately 3 nF, the typical dead time is approximately 30 ns. When small and fast MOSFETs are used, the dead time can be as low as 13 ns. Figure 28. Overvoltage Protection in PSM POWER GOOD The PGOODx pin is an open-drain NMOS with an internal 12 kΩ pull-up resistor connected between PGOODx and VCCO. PGOODx is internally pulled up to VCCO during normal operation and is active low when tripped. When the feedback voltage, VFB, rises above the overvoltage threshold or drops below the undervoltage threshold, the PGOODx output is pulled to ground after a delay of 12 μs. The overvoltage or undervoltage condition must exist for more than 12 μs for PGOODx to become active. The PGOODx output also becomes active if a thermal overload condition is detected. Rev. 0 | Page 15 of 32 ADP1877 SHUTDOWN CONTROL When the output is shorted or the output current exceeds the current limit set by the RILIM resistor for eight consecutive cycles, the ADP1877 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 1 kΩ resistor during an overcurrent or short-circuit event. Figure 29 shows that the ADP1877 (a 20 A application circuit) is entering current limit hiccup mode when the output is shorted. SW1 1 The EN1 and EN2 pins are used to enable or disable Channel 1 and Channel 2, respectively, of the ADP1877. The precision enable threshold for EN1/EN2 is typically 0.63 V. When the EN1/EN2 voltage rises above 0.63 V, the ADP1877 is enabled and starts normal operation after the soft start period. When the voltage at EN1/EN2 drops below 0.57 V, the switchers and the internal circuits in the ADP1877 are turned off. Note that EN1/EN2 cannot shut down the LDO at VCCO, which is always active. For the purpose of start-up power sequencing, the startup of the ADP1877 can be programmed by connecting an appropriate resistor divider from the master power supply to the EN1/EN2 pin, as shown in Figure 30. For instance, if the desired start-up voltage from the master power supply is 10 V, R1 and R2 can be set to 156 kΩ and 10 kΩ, respectively. MASTER SUPPLY VOLTAGE SS1 3 VOUT1 ADP1877 R1 R2 INDUCTOR CURRENT EN1 OR EN2 FB1 OR FB2 RTOP RBOT 4 08299-007 SHORT CIRCUIT AND CURRENT LIMIT PROTECTION M2ms A CH1 11.2V CH4 10A Ω Figure 29. Current Limit Hiccup Mode, 20 A Circuit 08299-045 Figure 30. Optional Power-Up Sequencing Circuit CH1 10V CH3 500mV THERMAL OVERLOAD PROTECTION The ADP1877 has an internal temperature sensor that senses the junction temperature of the chip. When the junction temperature of the ADP1877 reaches approximately 155°C, the ADP1877 goes into thermal shutdown, the converter is turned off, and SS discharges toward zero through an internal 1 kΩ resistor. At the same time, VCCO discharges to zero. When the junction temperature drops below 135°C, the ADP1877 resumes normal operation after the soft start sequence. Rev. 0 | Page 16 of 32 ADP1877 Once the voltage at SSx exceeds the regulation voltage (typically 0.6 V), the reverse current is reenabled to allow the output voltage regulation to be independent of load current. APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider divides down the output voltage to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage can be set to as low as 0.6 V and as high as 90% of the power input voltage. The maximum input bias current into FB is 100 nA. For a 0.15% degradation in regulation voltage and with 100 nA bias current, the low-side resistor, RBOT, must be less than 9 kΩ, which results in 67 μA of divider current. For RBOT, use a 1 kΩ to 20 kΩ resistor. A larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the FB pin, while lower values cause increased quiescent current consumption. Choose RTOP to set the output voltage by using the following equation: ⎛ V − VFB RTOP = R BOT ⎜⎜ OUT VFB ⎝ The minimum output voltage is dependent on fSW and minimum DH on time. The maximum output voltage is dependent on fSW, the minimum DH off time, and the IR drop across the high-side N-channel MOSFET (NMOSFET) and the DCR of the inductor. For example, with an fSW of 600 kHz (or 1.67 μs) and minimum on time of 130 ns, the minimum duty cycle is approximately 7.8% (130 ns/1.67 μs). If VIN is 12 V and the duty cycle is 7.8%, then the lowest output is 0.94 V. As an example for the maximum output voltage, if VIN is 5 V, fSW is 600 kHz, and the minimum DH off time is 390 ns (330 ns DH off time plus approximately 60 ns total dead time), then the maximum duty cycle is 76%. Therefore, the maximum output is approximately 3.8 V. If the IR drop across the high-side NMOSFET and the DCR of the inductor is 0.5 V, then the absolute maximum output is 4.5 V (5 V − 0.5 V), independent of fSW and duty cycle. SOFT START Program the soft start by connecting a capacitor from SSx to AGND. The soft start function limits the input inrush current and prevents the output overshoot. On startup, a 6.5 μA current source charges the SSx capacitor. The soft start period is approximated by 0.6 V 6.5 μA SETTING THE CURRENT LIMIT The current limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set by an external current limit resistor, RILIM. The current sense pin, ILIMx, sources 50 μA to this external resistor. This creates an offset voltage of RILIM multiplied by 50 μA. When the drop across the low-side MOSFET, RDSON, is equal to or greater than this offset voltage, the ADP1877 flags a current limit event. Because the ILIMx current and the MOSFET, RDSON, vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. To do this, use the peak current in the inductor, which is the desired output current limit level plus ½ of the ripple current, the maximum RDSON of the MOSFET at its highest expected temperature, and the minimum ILIM current. ⎞ ⎟ ⎟ ⎠ where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V. t SS = When a controller is disabled, for instance, EN1/EN2 is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 1 kΩ pull-down resistor. RILIM = I LPK × RDSON _ MAX 40 μA where: ILPK is the peak inductor current. The buck converters usually run a fairly high current. PCB layout and component placement may affect the current limit setting. An iteration of the RILIM value may be required for a particular board layout and MOSFET selection. If alternative MOSFETs are substituted at some point in production, these resistor values may also need an iteration. Keep in mind that the temperature coefficient of the MOSFET, RDSON, is typically 0.4%/oC. ACCURATE CURRENT LIMIT SENSING RDSON of the MOSFET can vary by more than 50% over the temperature range. Accurate current limit sensing can be achieved by adding a current sense resistor from the source of the low-side MOSFET to PGND. Make sure that the power rating of the current sense resistor is adequate for the application. Apply the above equation and calculate RILIM by replacing RDSON_MAX with RSENSE. The Figure 31 illustrates the implementation of this accurate current limit sensing. C SS The SSx pin reaches a final voltage equal to VCCO. If the output voltage is precharged prior to turn-on, the ADP1877 prevents reverse inductor current, which discharges the output capacitor. Rev. 0 | Page 17 of 32 ADP1877 VIN VIN ADP1877 RRAMP DHx SWx RAMP RILIM DHx SWx RSENSE 08299-008 DLx ILIMx RILIM DLx Figure 31. Accurate Current Limit Sensing ADP1877 RCSG SETTING THE SLOPE COMPENSATION In a current-mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. The external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the RAMPx pin. To implement the slope compensation, connect a resistor between RAMPx and the input voltage. The resistor, RRAMP, is calculated by R RAMP = 3.6 × 10 10 L ACS × R DSON _ MAX where: 3.6 × 1010 is an internal parameter. L is the inductance of the inductor. RDSON_MAX is the the low-side MOSFET maximum on resistance. ACS is the gain, either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, of the current sense amplifier (see the Setting the Current Sense Gain section for more details). Keep in mind that RDSON is temperature dependent and can vary as much as 0.4%/oC. Choose RDSON at the maximum operating temperature. The voltage at RAMPx is fixed at 0.2 V, and the current going into RAMPx should be in between 10 μA and 200 μA. Make sure that the following condition is satisfied: 10 μA ≤ V IN − 0.2V ≤ 200 μA R RAMP Figure 32. Slope Compensation and CS Gain Connection SETTING THE CURRENT SENSE GAIN The voltage drop across the external low-side MOSFET is sensed by a current sense amplifier by multiplying the peak inductor current and the RDSON of the MOSFET. The result is then amplified by a gain factor of either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, which is programmable by an external resistor, RCSG, connected to the DL pin. This gain is sensed only during power-up and not during normal operation. The amplified voltage is summed with the slope compensation ramp voltage and fed into the PWM controller for a stable regulation voltage. The voltage range of the internal node, VCS, is between 0.4 V and 2.2 V. Select the current sense gain such that the internal minimum amplified voltage (VCSMIN) is above 0.4 V and the maximum amplified voltage (VCSMAX) is 2.1 V. Do not set VCSMAX above 2.1 V to account for temperature and part-to-part variations. Note that VCSMIN or VCSMAX is not the same as VCOMP, which has a range of 0.75 V to 2.25 V. The following are equations for VCSMIN and VCSMAX: VCSMIN = 0.75 V − 1 I LPP × R DSON _ MIN × ACS 2 VCSMAX = 0.75 V + (I LOADMAX + For instance, with an input voltage of 12 V, RRAMP should not exceed 1.1 MΩ. If the calculated RRAMP produces less than 10 μA, then select a RRAMP value that produces between 10 μA and 20 μA. Figure 32 illustrates the connection of the slope compensation resistor RRAMP and the current sense gain resistor RCSG. 08299-009 ILIMx 1 I LPP ) × R DSON _ MAX × ACS 2 where: VCSMIN is the minimum amplified voltage of the internal current sense amplifier at zero output current. VCSMAX is the maximum amplified voltage of the internal current sense amplifier at maximum output current. RDSON_MIN is the the low-side MOSFET minimum on resistance. The zero-current level voltage of the current sense amplifier is 0.75 V. ILPP is the peak-to-peak ripple current in the inductor. ILOADMAX is the maximum output DC load current. Table 6 shows the appropriate current sense gain settings for a given RDSON maximum load current and a 33% inductor current ripple. Because of the variation in RDSON of the power MOSFETs (part-to-part variation and overtemperature) and the variation of the inductors, the users must verify that VCOMP does not exceed 2.2 V at the maximum output load current. Rev. 0 | Page 18 of 32 ADP1877 Table 6. CS Gain Setting Selection Table for Some Popular Configurations ILPP = 33% Load RDSON (mΩ) 1.5 2 2 3 5 7 10 15 18 20 25 30 40 60 80 100 120 ACS = 3 Load (A) 25 25 20 20 15 10 10 8 8 7 5 5 5 3 2 2 2 VCS Min (V) 0.73 0.73 0.73 0.72 0.71 0.72 0.70 0.69 0.68 0.68 0.69 0.68 0.65 0.66 0.67 0.65 0.63 VCS Max (V) 0.9 0.9 0.9 1.0 1.0 1.0 1.1 1.2 1.3 1.2 1.2 1.3 1.4 1.4 1.3 1.4 1.6 ACS = 6 VCS Min (V) 0.71 0.70 0.71 0.69 0.68 0.68 0.65 0.63 0.61 0.61 0.63 0.60 INPUT CAPACITOR SELECTION The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the direct current. The input capacitor needs sufficient ripple current rating to handle the input ripple, as well as an ESR that is low enough to mitigate input voltage ripple. For the usual current ranges for these converters, it is good practice to use two parallel capacitors placed close to the drains of the high-side switch MOSFETs (one bulk capacitor of sufficiently high current rating and a 10 μF ceramic decoupling capacitor, typically). Select an input bulk capacitor based on its ripple current rating. First, determine the duty cycle of the output. V D = OUT V IN The input capacitor RMS ripple current is given by I RMS = I O D(1 − D ) where: IO is the output current. D is the duty cycle The minimum input capacitance required for a particular load is C IN , MIN = I O × D(1 − D ) (V PP − I O × DR ESR ) f SW ACS = 12 VCS Max (V) 1.01 1.10 1.03 1.17 1.27 1.24 1.45 1.59 1.76 1.73 1.62 1.80 VCS Min (V) 0.7 0.7 0.7 0.6 0.6 0.6 VCS Max (V) 1.3 1.4 1.3 1.6 1.8 1.7 ACS = 24 VCS Min (V) 0.6 VCS Max (V) 1.80 where: VPP is the desired input ripple voltage. RESR is the equivalent series resistance of the capacitor. If an MLCC capacitor is used, the ESR is near 0, then the equation is simplified to C IN , MIN = I O × D(1 − D ) V PP × f SW The capacitance of MLCC is voltage dependent. The actual capacitance of the selected capacitor must be derated accordingly. In addition, add more bulk capacitance, such as by using electrolytic or polymer capacitors, as necessary for large step load transisents. Make sure the current ripple rating of the bulk capacitor exceeds the minimum input current ripple of a particular design. INPUT FILTER Normally the input pin, VIN, with a 0.1 μF or greater value bypass capacitor to AGND, is sufficient for filtering out any unwanted switching noise. However, depending on the PCB layout, some switching noises can be passed down to the ADP1877 internal circuitry; therefore, it is recommended to have a low pass filter at the VIN pin. Connecting a resistor, between 2 Ω and 5 Ω, in series with VIN and a 1 μF ceramic capacitor between VIN and AGND creates a low pass filter that effectively filters out any unwanted glitches caused by the switching regulator. Keep in mind that the input current could be larger than 100 mA when driving large MOSFETs. A 100 mA across a 5 Ω resistor creates a 0.5 V drop, which is the same voltage drop in VCCO. In this case, a lower resistor value is desirable. Rev. 0 | Page 19 of 32 ADP1877 Solving COUT in the previous equation yields 1µF VIN COUT ≅ ADP1877 AGND Figure 33. Input Filter Configuration BOOST CAPACITOR SELECTION To lower system component count and cost, the ADP1877 has a built-in rectifier (equivalent to the boost diode) between VCCO and BSTx. Choose a boost ceramic capacitor with values between 0.1 μF and 0.22 μF, which provides the current for the high-side driver during switching. INDUCTOR SELECTION The output LC filter smoothes the switched voltage at SWx. Choose an inductor value such that the inductor ripple current is approximately 1⁄3 of the maximum dc output load current. Using a larger value inductor results in a physical size larger than required, and using a smaller value results in increased losses in the inductor and/or MOSFET switches and larger voltage ripples at the output. ΔVOUT ≅ ΔI L × RESR Electrolytic capacitors also have significant ESL, on the order of 5 nH to 20 nH, depending on type, size, and geometry. PCB traces contribute some ESR and ESL, as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required. In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output cap is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the output capacitance equation reduces to C OUT ≅ Choose the inductor value by the following equation: L= 1 ΔI L × 8 f SW ΔVOUT − ΔI L RESR − 4 ΔI L f SW × LESL Usually, the impedance is dominated by ESR, such as in electrolytic or polymer capacitors, at the switching frequency, as stated in the maximum ESR rating on the capacitor data sheet; therefore, output ripple reduces to 08299-010 VIN 2Ω TO 5Ω VIN − VOUT VOUT × f SW × ΔI L VIN ΔI L 8 ΔVOUT × f SW Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. ΔIL is the inductor ripple current, typically 1⁄3 of the maximum dc load current. During a load step transient on the output, for instance, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation results in a voltage droop or undershoot. The output capacitance, assuming 0 ESR, required to satisfy the voltage droop requirement can be approximated by C OUT ≅ OUTPUT CAPACITOR SELECTION Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL). The output voltage ripple can be approximated with ΔV DROOP × f SW where: ΔISTEP is the step load. ΔVDROOP is the voltage droop at the output. When a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. The output capacitance required to satisfy the output overshoot requirement can be approximated by ⎛ ⎞ 1 ΔVOUT ≅ ΔI L ⎜ R ESR + + 4 f SW × L ESL ⎟ ⎜ ⎟ × 8 f C SW OUT ⎝ ⎠ C OUT ≅ where: ΔVOUT is the output ripple voltage. ΔIL is the inductor ripple current. RESR is the equivalent series resistance of the output capacitor (or the parallel combination of ESR of all output capacitors). LESL is the equivalent series inductance of the output capacitor (or the parallel combination of ESL of all capacitors). ΔI STEP (VOUT ΔI STEP 2 L + ΔVOVERSHOOT )2 − VOUT 2 where: ΔVOVERSHOOT is the overshoot voltage during the step load. Select the largest output capacitance given by any of the previous three equations. Rev. 0 | Page 20 of 32 ADP1877 MOSFET SELECTION The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and low gate charge reduces transition losses. The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter. Typically, the lower the on resistance of the MOSFET, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by the equation ⎛V PC ≅ (I LOAD ) 2 × R DSON ⎜⎜ OUT ⎝ V IN ⎞ ⎟ ⎟ ⎠ where: RDSON is the MOSFET on resistance. The gate charging loss is approximated by the equation PG ≅ V PV × Q G × f SW where VPV is the gate driver supply voltage. QG is the MOSFET total gate charge. IDRIVER_RISE and IDRIVER_FALL can be estimated by V IN × I LOAD × (t R + t F ) × f SW 2 where: PT is the high-side MOSFET switching loss power. tR is the rise time in charging the high-side MOSFET. tF is the fall time in discharging the high-side MOSFET. tF ≅ QGSW I DRIVER _ FALL VSP RON _ SINK + RGATE The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in the calculation. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time. Therefore, to achieve high efficiency, it is critical to optimize the low-side MOSFET for low on resistance. In cases where the power loss exceeds the MOSFET rating or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET conduction power loss is ⎡ V ⎤ PCLS ≅ (I LOAD ) 2 × R DSON ⎢1 − OUT ⎥ V IN ⎦ ⎣ There is also additional power loss during the time, known as dead time, between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the lowside MOSFET conducts the output current. The power loss in the body diode is given by where: QGSW is the gate charge of the MOSFET during switching and is given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL are the driver current put out by the ADP1877 internal gate drivers. If QGSW is not given in the data sheet, it can be approximated by QGSW ≅ Q GD + I DRIVER _ FALL ≅ where: VDD is the input supply voltage to the driver and is between 2.75 V and 5 V, depending on the input voltage. VSP is the switching point where the MOSFET fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the MOSFET data sheet. RON_SOURCE is the on resistance of theADP1877 internal driver, given in Table 1, when charging the MOSFET. RON_SINK is the on resistance of the ADP1877 internal driver, given in Table 1, when discharging the MOSFET. RGATE is the on gate resistance of MOSFET given in the MOSFET data sheet. If an external gate resistor is added, add this external resistance to RGATE. tR and tF can be estimated by QGSW I DRIVER _ RISE VDD − VSP RON _ SOURCE + RGATE PHS ≅ PC + PT The high-side MOSFET transition loss is approximated by the equation tR ≅ I DRIVER _ RISE ≅ The total power dissipation of the high-side MOSFET is the sum of conduction and transition losses: Note that the gate charging power loss is not dissipated in the MOSFET but rather in the ADP1877 internal drivers. This power loss should be taken into consideration when calculating the overall power efficiency. PT ≅ where: QGD and QGS are the gate-to-drain and gate-to-source charges given in the MOSFET data sheet. PBODYDIODE = VF × t D × f SW × I O where: VF is the forward voltage drop of the body diode, typically 0.7 V. tD is the dead time in the ADP1877, typically 30 ns when driving some medium-size MOSFETs with input capacitance of approximately 3 nF. Q GS 2 Rev. 0 | Page 21 of 32 ADP1877 Then the power loss in the low-side MOSFET is Z FILTER = PLS = PCLS + PBODYDIODE Note that MOSFET, RDSON, increases with increasing temperature with a typical temperature coefficient of 0.4%/oC. The MOSFET junction temperature rise over the ambient temperature is TJ = TA + θJA × PD 1 Because CC2 is very small relative to CCOMP, ZCOMP can be written as Z COMP = RCOMP + Z COMP ( f CROSS ) = ( LOOP COMPENSATION As with most current mode step-down controller, a transconductance error amplifier is used to stabilize the external voltage loop. Compensating the ADP1877 is fairly easy; an RC compensator is needed between COMP and AGND. Figure 34 shows the configuration of the compensation components: RCOMP, CCOMP, and CC2. Because CC2 is very small compared to CCOMP, to simplify calculation, CC2 is ignored for the stability compensation analysis. COMPx f ZERO = (4) sC COMP 2π × f CROSS G m × G CS )( C OUT × VOUT VREF ) (5) 1 2πR COMP × C COMP Z COMP ( f CROSS ) = RCOMP × (6) f CROSS + f ZERO (7) f CROSS Combining Equations 5 and Equation 7 and solving for RCOMP gives RCOMP = C ×V 2π× fCROSS fCROSS ×( )×( OUT OUT ) fCROSS + f ZERO Gm ×GCS VREF (8) Choose the crossover and zero frequencies as follows: CCOMP AGND ADP1877 08299-011 0.6V Figure 34. Compensation Components The open loop gain transfer function at angular frequency, s, is given by VREF × Z COMP (s) × Z FILTER (s) VOUT ACS × R DSON _ MIN f SW 13 f ZERO = f CROSS f SW = 5 65 (9) (10) RCOMP = 0.83 × ACS × RDSON ( 2π× fCROSS Gm )× ( COUT ×VOUT VREF ) (11) where: Gm is the transconductance of the error amplifer, 500 μs. ACS is the current sense gain of 3 V/V, 6 V/V, 12 V/V or 24 V/V. RDSON is on resistance of the low-side MOSFET. VREF = 0.6 V And combining Equation 6 and Equation 10 yields GCS with units of A/V is given by 1 f CROSS = Substituting Equation 2, Equation 9, and Equation 10 into Equation 8 yields (1) where: Gm is the transconductance of the error amplifer, 500 μs. GCS is the tranconductance of the current sense amplifier. ZCOMP is the impedance of the compensation network. ZFILTER is the impedance of the output filter. VREF = 0.6 V G CS = 1 + sRCOMP × C COMP At the crossover frequency, Equation 4 can be shown as Gm H (s) = G m × G CS × sC COMP = The zero produced by RCOMP and CCOMP is FBx CC2 1 At the crossover frequency, the open loop transfer function is unity of 0 dB, H (fCROSS) = 1. Combining Equation 1 and Equation 3, ZCOMP at the crossover frequency can be written as where: θJA is the thermal resistance of the MOSFET package. TA is the ambient temperature. PD is the total power dissipated in the MOSFET. RCOMP (3) sC OUT C COMP = (2) where: ACS is the current sense gain of either 3 V/V, 6 V/V, 12 V/V, or 24 V/V set by the gain resistor between DL and PGND. RDSON_MIN is the the low-side MOSFET minimum on resistance. 2 πR COMP × f CROSS (12) And lastly set CC2 to Because the zero produced by the ESR of the output capacitor is not needed to stabilize the control loop, the ESR is ignored for analysis. Then ZFILTER is given by Rev. 0 | Page 22 of 32 1 1 × C COMP ≤ C C 2 ≤ × C COMP 20 10 (13) ADP1877 SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING In any high speed step-down regulator, high frequency noise (generally in the range of 50 MHz to 100 MHz) and voltage overshoot are always present at the gate, the switch node (SW), and the drains of the external MOSFETs. The high frequency noise and overshoot are caused by the parasitic capacitance, CGD, of the external MOSFET and the parasitic inductance of the gate trace and the packages of the MOSFETs. When the high current is switched, electromagnetic interference (EMI) is generated, which can affect the operation of the surrounding circuits. To reduce voltage ringing and noise, it is required to add an RC snubber between SW and PGND for applications with more than 10 A output current, as illustrated in Figure 35. Snubbers may also be needed in applications where the duty cycle in one of the channels is higher than or equal to 50%. In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB typically 1.2 nF to 3 nF. The ADP1877 includes a tracking feature that tracks a master voltage. This feature is especially important when the ADP1877 is powering separate power supply voltages on a single integrated circuit, such as the core and I/O voltages of a DSP or microcontroller. In these cases, improper sequencing can cause damage to the load. RSNUB can be estimated by Two tracking configurations are possible with the ADP1877: coincident and ratiometric trackings. Full time DDR termination is not recommended when using these tracking features. COINCIDENT TRACKING And CSNUB can be estimated by C SNUB ≅ C OSS where: LMOSFET is the total parasitic inductance of the high-side and low-side MOSFETs, typically 3 nH, and is package dependent. COSS is the total output capacitance of the high-side and lowside MOSFETs given in the MOSFET data sheet. The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage. For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT, as shown in Figure 37. MASTER VOLTAGE The size of the RC snubber components need to be chosen correctly to handle the power dissipation. The power dissipated in RSNUB is SLAVE VOLTAGE PSNUB = V IN 2 × C SNUB × f SW TIME In most applications, a component size 0805 for RSNUB is sufficient. However, the use of an RC snubber reduces the overall efficiency, generally by an amount in the range of 0.1% to 0.5%. The RC snubber cannot reduce the voltage overshoot. A resistor, shown as RRISE in Figure 35, at the BSTx pin helps to reduce overshoot and is generally between 2 Ω and 4 Ω. Adding a resistor in series, typically between 2 Ω and 4 Ω, with the gate driver also helps to reduce overshoot. If a gate resistor is added, then RRISE is not needed. VDL BST1 EN1 VCCO 1MΩ RRISE M1 VOUT COUTx CSNUB ADP1877 08299-012 PGND1 (CHANNEL 1) RTRKT 20kΩ 1.1V 10kΩ RTRKB 10kΩ ADP1877 CSS1 100nF SS1 TRK2 SS2 RTOP 20kΩ CSS2 20nF 1.8V VOUT2_SLAVE Figure 37. Example of a Coincident Tracking Circuit RILIM1 RSNUB 45.3kΩ FB1 TRK1 RBOT 10kΩ L M2 EN2 FB2 SW1 DL1 3.3V VOUT1_MASTER EN VIN DH1 ILIM1 Figure 36. Coincident Tracking Figure 35. Application Circuit with a Snubber Rev. 0 | Page 23 of 32 08299-014 C OSS 08299-013 L MOSFET VOLTAGE (V) R SNUB ≅ 2 In all tracking configurations, the output can be set as low as 0.6 V for a given operating condition. The soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relationship is not seen at the output. ADP1877 The ratio of the slave output voltage to the master voltage is a function of the two dividers. As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRKx input continues to increase and thus removes itself from influencing the output voltage. To ensure that the output voltage accuracy is not compromised by the TRKx pin being too close in voltage to the 0.6 V reference, make sure that the final value of the TRKx voltage of the slave channel is at least 0.7 V. Another ratiometric tracking configuration is having the slave channel rise more quickly than the master channel, as shown in Figure 38 and Figure 39. The tracking circuits in Figure 37 and Figure 38 are virtually identical with the exception that RTRKB > RTRKT, as shown in Figure 38. 3.3V VOUT1_MASTER EN EN1 VCCO 1MΩ EN2 45.3kΩ RTRKT 5kΩ 2.2V 10kΩ RTRKB 10kΩ FB1 TRK1 ADP1877 CSS1 100nF TRK2 SS1 SS2 CSS2 20nF FB2 RBOT 10kΩ RTOP 20kΩ 08299-015 VOUT _ MASTER Ratiometric tracking limits the output voltage to a fraction of the master voltage. For ratiometric tracking, the simplest configuration is to tie the TRK pin of the slave channel to the FBx pin of the master channel. However, because of the large internal offset between TRKx and FBx, this ratiometric tracking configuration is not recommended. A tracking configuration that requires the TRKx voltage of the slave channel below 0.6 V is not recommended because of the large internal TRKx to FBx offset voltage. 1.8V VOUT2_SLAVE Figure 38. A Simple Ratiometric Tracking Circuit (Slave Channel Has a Faster Ramp Rate) VOLTAGE (V) MASTER VOLTAGE SLAVE VOLTAGE TIME 08299-016 VOUT _ SLAVE ⎛ R ⎞ ⎜⎜1 + TOP ⎟⎟ R BOT ⎠ = ⎝ ⎛ ⎞ R ⎜⎜1 + TRKT ⎟⎟ RTRKB ⎠ ⎝ RATIOMETRIC TRACKING Figure 39. Ratiometric Tracking (Slave Channel Has a Faster Ramp Rate) Rev. 0 | Page 24 of 32 ADP1877 PCB LAYOUT GUIDELINE VIN In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. When designing PCB layouts, be sure to keep high current loops small. In addition, keep compensation and feedback components away from the switch nodes and their associated components. DH1 23 L1 DL1 21 CDECOUPLE1 SW1 24 M2 PGND1 22 CIN1 VOUT1 COUT1 PGND PLANE DL2 20 CDECOUPLE2 PGND2 19 The following is a list of recommended layout practices for the synchronous buck controller, arranged by decreasing order of importance. M4 SW2 17 MOSFETS, INPUT BULK CAPACITOR, AND BYPASS CAPACITOR DH2 18 CIN2 COUT2 L2 VOUT2 M3 ADP1877 08299-017 The current waveform in the top and bottom FETs is a pulse with very high dI/dt; therefore, the path to, through, and from each individual FET should be as short as possible, and the two paths should be commoned as much as possible. In designs that use a pair of D-Pak or a pair of SO-8 FETs on one side of the PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair, and the high-side drain can be bypassed to the low side source with a suitable ceramic bypass capacitor, placed as close as possible to the FETs. This minimizes the inductance around this loop through the FETs and capacitor. The recommended bypass ceramic capacitor values range from 1 μF to 22 μF, depending upon the output current. This bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGNDx plane. M1 VIN Figure 40. Grounding Technique for Two Channels SIGNAL PATHS The negative terminals of AGND, VIN bypass, compensation components, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to an almost isolated small AGND plane. All of these connections sh from their respective pins to the AGND plane should be as short as possible. No high current or high dI/dt signals should be connected to this AGND plane. The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors. HIGH CURRENT AND CURRENT SENSE PATHS PGND PLANE Part of the ADP1877 architecture is sensing the current across the low-side FET between the SWx and PGNDx pins. The switching GND currents of one channel creates noise and can be picked up by the other channel. It is essential to keep the SW1/SW2 and PGND1/PGND2 traces as short as possible and placed very close to the FETs to achieve accurate current sensing. The following schematic illustrates the proper connection technique for the SW1/SW2, PGND1/PGND2, and PGNDx plane. Note that PGND1 and PGND2 are only jointed at the PGND plane. The PGNDx pin handles a high dI/dt gate drive current returning from the source of the low side MOSFET. The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection function and the ILIMx pin. A PGND plane should connect the PGNDx pin and the VDL bypass capacitor, 1 μF, through a wide and direct path to the source of the low side MOSFET. The placement of CIN is critical for controlling ground bounce. The negative terminal of CIN must be placed very close to the source of the low-side MOSFET. FEEDBACK AND CURRENT LIMIT SENSE PATHS Avoid long traces or large copper areas at the FBx and ILIMx pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. It is best to position any series resistors and capacitors as close as possible to these pins. Avoid running these traces close and/or parallel to high dI/dt traces. Rev. 0 | Page 25 of 32 ADP1877 SWITCH NODE The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. This node should be wide to keep resistive voltage drop down. To minimize the generation of capacitively coupled noise, the total area should be small. Place the FETs and inductor close together on a small copper plane to minimize series resistance and keep the copper area small. GATE DRIVER PATHS Gate drive traces (DH and DL) handle high dI/dt and tend to produce noise and ringing. They should be as short and direct as possible. If possible, avoid using feedthrough vias in the gate drive traces. If vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. If the overall PCB layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. It is occasionally helpful to place small value resistors, such as between 2 Ω and 4 Ω, on the DH and DL pins. These can be populated with 0 Ω resistors if resistance is not needed. Note that the added gate resistance increases the switching rise and fall times as well as switching power loss in the MOSFET. OUTPUT CAPACITORS The negative terminal of the output filter capacitors should be tied close to the source of the low side FET. Doing this helps to minimize voltage differences between AGND and PGNDx. Rev. 0 | Page 26 of 32 ADP1877 TYPICAL OPERATING CIRCUITS 330pF 66.5kΩ 47pF VIN = 10V TO 14V M1 RTOP1 45.3kΩ 845kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 4kΩ 2Ω VCCO 26 25 BST1 VIN 4 27 ILIM1 SYNC 3 28 PGOOD1 2 29 SS1 EN1 30 RAMP1 1 31 FB1 TRK1 32 COMP1 1MΩ L1 0.1µF COUT11 COUT12 VOUT1 3.3V 10A M2 SW1 24 DH1 23 1µF PGND1 RCSG1 4kΩ 22 1µF DL1 21 1µF 8 EN2 SW2 17 11 12 13 845kΩ 10 1MΩ VCCO 36.5kΩ 15 16 RBOT2 10kΩ CIN2 RILIM2 4kΩ L2 M4 COUT21 0.1µF COUT22 VOUT2 1.8V 10A 100nF RCSG2 4kΩ TO VIN 47pF fSW = 600kHz 14 M3 RTOP2 20kΩ L1, L2: 1.2µH, WURTH ELEKTRONIK, 744325120 M1, M2, M3, M4: IRLR7821 CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MURATA COUT11, COUT21: 330µF/6.3V/POSCAP × 2, 6TPF330M9L, SANYO COUT12, COUT22: 22µF/X5R/0805/6.3V, GRM21BR60J226ME39, MURATA Figure 41. Typical Medium Current Operating Circuit Rev. 0 | Page 27 of 32 08299-019 680pF BST2 DH2 18 PGOOD2 FREQ ILIM2 7 SS2 PGND2 19 RAMP2 AGND COMP2 6 FB2 VDL 9 VIN = 10V TO 14V, OR CAN BE CONNECTED TO A SEPARATE POWER SUPPLY 5V DL2 20 5 TRK2 VCCO ADP1877 ADP1877 2.2nF 18.7kΩ 220pF VIN = 10V TO 14V RTOP1 20kΩ RILIM1 3.7kΩ 2Ω FB1 COMP1 RAMP1 28 27 26 25 BST1 29 ILIM1 30 SS1 31 PGOOD1 32 TRK1 1MΩ 0.1µF COUT11 4Ω SW1 24 EN1 2 SYNC 3 VIN 4 VCCO 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 DH1 23 RDH1 3Ω 1µF PGND1 22 1µF DL1 21 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 10 11 12 13 14 15 16 845kΩ FB2 9 1MΩ VCCO 3.9nF DL2 20 TRK2 VCCO ADP1877 12.7kΩ 1.2nF RCSG1 22kΩ RDL1 3Ω RDL2 3Ω VIN M3 RDH2 3Ω RBOT2 10kΩ CIN2 RILIM2 3.7kΩ L2 M4 0.1µF COUT21 COUT22 VOUT2 1.05V 20A 4Ω 100nF RCSG2 22kΩ TO VIN 220pF COUT12 VOUT1 1.8V 20A M2 1 1µF L1 1.2nF RTOP2 7.5kΩ CIN = 180µF/20V, 20SP180M, OSCON, SANYO L1, L2: 1.3µH, WURTH ELEKTRONIK, 7443551130 M1, M3: BSC080N03LS M2, M4: BSC030N03LS CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MURATA COUT11, COUT21: 680µF/2.5V/POSCAP × 2, 2R5TPD680M5, SANYO COUT12, COUT22: 22µF/X5R/0805/6.3V × 3, GRM21BR60J226ME39, MURATA Figure 42. Typical 20 A Operating Circuit Rev. 0 | Page 28 of 32 08299-020 RBOT1 10kΩ CIN1 100nF VCCO fSW = 300kHz M1 CIN 845kΩ ADP1877 820pF 22.6kΩ 68pF VIN = 10V TO 14V M1A RTOP1 73.2kΩ 698kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 2.8kΩ 3Ω 25 BST1 VCCO 26 ILIM1 VIN 4 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 FB1 EN1 31 COMP1 1 32 TRK1 1MΩ L1 0.1µF COUT1 VOUT1 5V 5A M1B SW1 24 DH1 23 1µF RCSG1 22kΩ PGND1 22 1µF DL1 21 1µF 8 EN2 SW2 17 10 11 12 13 698kΩ 9 15 16 CIN2 RILIM2 2.8kΩ COUT2 VOUT2 1.8V 5A RCSG2 22kΩ RTOP2 20kΩ L1: 2µH, 744310200, WURTH ELEKTRONIK L2: 1.15µH, 744310115, WURTH ELEKTRONIK CIN1, CIN2: 10µF/X5R/16V/1206 × 2, GRM31CR61C106KA88, MURATA M1, M2: Si4944DY OR BSON03MD COUT1: 22µF/X5R/1210/6.3V × 3, GRM32DR60J226KA01, MURATA COUT2: 22µF/X5R/1210/6.3V × 3, GRM32DR60J226KA01, MURATA Figure 43. Typical Low Current Operating Circuit Rev. 0 | Page 29 of 32 08299-021 RBOT2 10kΩ L2 M2B 0.1µF TO VIN 120pF fSW = 750kHz 14 M2A 100nF VCCO 8.25kΩ BST2 DH2 18 PGOOD2 FREQ ILIM2 7 SS2 PGND2 19 RAMP2 AGND COMP2 6 FB2 VDL 1MΩ 2.2nF DL2 20 5 TRK2 84.5kΩ VIN ADP1877 ADP1877 1.8nF 5.34kΩ 33pF VIN = 3V TO 5.5V M1 RTOP1 73.2kΩ 121kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 4.99kΩ 5Ω 25 BST1 VCCO 26 ILIM1 VIN 4 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 COMP1 EN1 31 FB1 1 32 TRK1 1MΩ L1 0.1µF COUT1 VOUT1 1.05V 1.8A M2 SW1 24 DH1 23 1µF RCSG1 47kΩ PGND1 22 1µF DL1 21 1µF 8 EN2 SW2 17 10 11 13 14 15 16 L2 M4 COUT2 VOUT2 1.8V 1.8A 100nF RCSG2 47kΩ RTOP2 20kΩ CIN1, CIN2: 4.7µF/X5R/16V/0805 × 2, GRM219R60J475KE19, MURATA M1, M2, M3, M4: Si2302ADS, SOT23 COUT1, COUT2: 22µF/X5R/0805/6.3V, GRM21BR60J226ME39, MURATA Figure 44. Typical Low Current Application with VIN < 5.5 V Rev. 0 | Page 30 of 32 08299-022 L1, L2: 1µH, D62LCB1R0M, TOKO CIN2 0.1µF TO VIN RBOT2 10kΩ M3 RILIM2 4.99kΩ VCCO 8.66kΩ 33pF fSW = 800kHz 12 121kΩ 9 BST2 DH2 18 ILIM2 FREQ PGOOD2 7 RAMP2 PGND2 19 SS2 AGND COMP2 6 FB2 VDL 1MΩ 1nF DL2 20 5 TRK2 78.7kΩ VIN ADP1877 ADP1877 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 45. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body, Very Thin Quad (CP-32-11) Dimensions shown in millimeters ORDERING GUIDE Model ADP1877ACPZ-R7 1 ADP1877HC-EVALZ1 1 Temperature Range −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board with 13 A Output Z = RoHS Compliant Part. Rev. 0 | Page 31 of 32 Package Option CP-32-11 ADP1877 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08299-0-9/09(0) Rev. 0 | Page 32 of 32