6 GHz Ultrahigh Dynamic Range Differential Amplifier ADL5565 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC RF ENBL VIP2 VIP1 VIN1 VIN2 RG2 VON RG1 VCOM RG1 RG2 VOP RF GND ADL5565 09959-001 3 dB bandwidth of 6 GHz (AV = 6 dB) Pin strappable gain adjust: 6 dB, 12 dB, and 15.5 dB Gain range from 0 dB to 15.5 dB using two external resistors Differential or single-ended input to differential output Low noise input stage: NF = 8.7 dB at 15.5 dB gain Low broadband distortion (AV = 6 dB) 10 MHz: −107 dBc (HD2), −110 dBc (HD3) 100 MHz: −108 dBc (HD2), −103 dBc (HD3) 200 MHz: −82 dBc (HD2), −87 dBc (HD3) 500 MHz: −68 dBc (HD2), −63 dBc (HD3) IMD3 of −113 dBc at 100 MHz center Slew rate: 11 V/ns Fast settling and overdrive recovery of 2 ns Single-supply operation: 2.8 V to 5.2 V Power down Fabricated using the high speed XFCB3 SiGe process Figure 1. APPLICATIONS Differential ADC drivers Single-ended-to-differential conversion RF/IF gain blocks SAW filter interfacing GENERAL DESCRIPTION The ADL5565 is a high performance differential amplifier optimized for RF and IF applications. The amplifier offers low noise of 1.5 nV/√Hz and excellent distortion performance over a wide frequency range making it an ideal driver for high speed 8-bit to 16-bit analog-to-digital converters (ADCs). The ADL5565 provides three gain levels of 6 dB, 12 dB, and 15.5 dB through a pin strappable configuration. For the single-ended input configuration, the gains are reduced to 5.3 dB, 10.3 dB, and 13 dB. Using two external series resistors expands the gain flexibility of the amplifier and allows for any gain selection from 0 dB to 15.5 dB for a differential input and 0 dB to 13 dB for a single-ended input. The quiescent current of the ADL5565 is typically 70 mA, and when disabled, consumes less than 5 mA with −25 dB of inputto-output isolation at 100 MHz. The device is optimized for wideband, low distortion, and noise performance, giving it unprecedented performance for overall spurious-free dynamic range. These attributes, together with its adjustable gain capability, make this device the amplifier of choice for driving a wide variety of ADCs, mixers, pin diode attenuators, SAW filters, and multielement discrete devices. Fabricated on an Analog Devices, Inc., high speed SiGe process, the ADL5565 is supplied in a compact 3 mm × 3 mm, 16-lead LFCSP package and operates over the −40°C to +85°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADL5565 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description......................................................................... 16 Applications....................................................................................... 1 Basic Structure ............................................................................ 16 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 17 General Description ......................................................................... 1 Basic Connections...................................................................... 17 Revision History ............................................................................... 2 Input and Output Interfacing ................................................... 18 Specifications..................................................................................... 3 Gain Adjustment and Interfacing ............................................ 19 3.3 V Specifications ...................................................................... 3 ADC Interfacing ......................................................................... 20 5 V Specifications ......................................................................... 6 Layout Considerations............................................................... 22 Absolute Maximum Ratings............................................................ 9 Soldering Information ............................................................... 23 ESD Caution.................................................................................. 9 Evaluation Board ........................................................................ 23 Pin Configuration and Function Descriptions........................... 10 Outline Dimensions ....................................................................... 26 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 26 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADL5565 SPECIFICATIONS 3.3 V SPECIFICATIONS VS = 3.3 V, VCM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified ac-coupled differential input and differential output, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Range Output Common-Mode Range Maximum Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage CMRR Output Differential Offset Drift Input Bias Current Input Resistance (Differential) Input Resistance (Single-Ended) Input Capacitance (Single-Ended) Output Resistance (Differential) POWER INTERFACE Supply Voltage ENBL Threshold ENBL Input Bias Current Quiescent Current Test Conditions/Comments Min AV = 6 dB, VOUT ≤ 1.0 V p-p AV = 12 dB, VOUT ≤ 1.0 V p-p AV = 15.5 dB, VOUT ≤ 1.0 V p-p VOUT ≤ 1.0 V p-p VS ± 5% −40°C to +85°C Rise, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step Fall, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step 2 V step to 1% VIN = 4 V to 0 V step, VOUT ≤ ±10 mV AV = 6 dB, 12 dB, and 15.5 dB 1 dB compressed Referenced to VCC/2 −40°C to +85°C Typ MHz MHz MHz MHz dB mdB/V mdB/°C V/ns 11 V/ns 2 <3 70 ns ns dB 1.2 to 2 1.4 to 1.8 4 V V V p-p mV mV/°C mV dB mV/°C μA Ω Ω Ω Ω Ω Ω pF Ω −100 +20 0.34 AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 5.6 dB AV = 11.1 dB AV = 14.1 dB 2.8 Rev. 0 | Page 3 of 28 +20 60 1.5 ±5 200 100 67 158 96 74 0.3 10 −40°C to +85°C Unit 6750 6500 6250 1000 ±1 1.9 0.35 11 −20 ENBL high ENBL low ENBL high ENBL low Max 3.3 1.5 500 −165 70 5 5.2 V V nA μA mA mA ADL5565 Parameter NOISE/HARMONIC PERFORMANCE 10 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 1 dB Compression Point, RTO (OP1dB) 100 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 1 dB Compression Point, RTO (OP1dB) Test Conditions/Comments AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Rev. 0 | Page 4 of 28 Min Typ Max Unit −107/−110 −101/−107 −106/−112 +48/−100 dBc dBc dBc dBm/dBc +52/−108 dBm/dBc +50/−105 dBm/dBc −86 dBc −86 dBc −86 dBc 2.24 1.52 1.53 10.24 8.66 8.78 13.1 12.8 13.1 nV/√Hz nV/√Hz nV/√Hz dB dB dB dBm dBm dBm −108/−103 −91/−99 −89/−100 +54/−113 dBc dBc dBc dBm/dBc +53/−112 dBm/dBc +52/−111 dBm/dBc −85 dBc −85 dBc −86 dBc 2.25 1.53 1.52 10.27 8.69 8.7 13 12.8 12.8 nV/√Hz nV/√Hz nV/√Hz dB dB dB dBm dBm dBm ADL5565 Parameter 200 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 500 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) Test Conditions/Comments AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Rev. 0 | Page 5 of 28 Min Typ Max Unit −82/−87 −72/−86 −71/−86 +46/−97 dBc dBc dBc dBm/dBc +46/−99 dBm/dBc +46/−98 dBm/dBc −85 dBc −73 dBc −70 dBc 2.36 1.64 1.51 10.65 9.25 8.49 nV/√Hz nV/√Hz nV/√Hz dB dB dB −68/−63 −56/−62 −57/−63 +34/−77 dBc dBc dBc dBm/dBc +36/−82 dBm/dBc +39/−88 dBm/dBc −75 dBc −70 dBc −70 dBc 2.62 1.57 1.47 11.47 8.93 8.07 nV/√Hz nV/√Hz nV/√Hz dB dB dB ADL5565 5 V SPECIFICATIONS VS = 5.0 V, VCM = 2.5 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified ac-coupled differential input and differential output, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Range Output Common-Mode Range Maximum Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage CMRR Output Differential Offset Drift Input Bias Current Input Resistance (Differential) Input Resistance (Single-Ended) Input Capacitance (Single-Ended) Output Resistance (Differential) POWER INTERFACE Supply Voltage ENBL Threshold ENBL Input Bias Current Quiescent Current Test Conditions/Comments Min AV = 6 dB, VOUT ≤ 1.0 V p-p AV = 12 dB, VOUT ≤ 1.0 V p-p AV = 15.5 dB, VOUT ≤ 1.0 V p-p VOUT ≤ 1.0 V p-p VS ± 5% −40°C to +85°C Rise, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step Fall, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step 2 V step to 1% VIN = 4 V to 0 V step, VOUT ≤ ±10 mV AV = 6 dB, 12 dB, and 15.5 dB 1 dB compressed Referenced to VCC/2 −40°C to +85°C Typ MHz MHz MHz MHz dB mdB/V mdB/°C V/ns 11 V/ns 2 <3 70 ns ns dB 1.2 to 3.8 1.4 to 3 8 V V V p-p mV mV/°C mV dB mV/°C μA Ω Ω Ω Ω Ω Ω pF Ω −100 +20 0.4 AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 5.6 dB AV = 11.1 dB AV = 14.1 dB 2.8 Rev. 0 | Page 6 of 28 +20 60 1.5 ±5 200 100 67 158 96 74 0.3 10 −40°C to +85°C Unit 7000 6750 6500 1000 ±1 1.6 0.37 11 −20 ENBL high ENBL low ENBL high ENBL low Max 5 1.5 1 −250 80 6 5.2 V V μA μA mA mA ADL5565 Parameter NOISE/HARMONIC PERFORMANCE 10 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 1 dB Compression Point, RTO (OP1dB) 100 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 1 dB Compression Point, RTO (OP1dB) Test Conditions/Comments AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Rev. 0 | Page 7 of 28 Min Typ Max Unit −111/−116 −100/−104 −105/−106 +47/−99 dBc dBc dBc dBm/dBc +50/−105 dBm/dBc +50/−105 dBm/dBc −78 dBc −86 dBc −91 dBc 2.25 1.54 1.55 10.29 8.77 9.04 16.8 16.7 16.6 nV/√Hz nV/√Hz nV/√Hz dB dB dB dBm dBm dBm −108/−109 −92/−103 −89.5/−105 +53/−112 dBc dBc dBc dBm/dBc +53/−112 dBm/dBc +52/−110 dBm/dBc −87 dBc −91 dBc −87 dBc 2.28 1.53 1.52 10.39 8.73 8.7 16.8 16.5 16.4 nV/√Hz nV/√Hz nV/√Hz dB dB dB dBm dBm dBm ADL5565 Parameter 200 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) 500 MHz Second/Third Harmonic Distortion (HD2/HD3) Output IP3/Third-Order Intermodulation Distortion (OIP3/IMD3) Second-Order Intermodulation Distortion (IMD2) Noise Spectral Density, RTI (NSD) Noise Figure (NF) Test Conditions/Comments AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Rev. 0 | Page 8 of 28 Min Typ Max Unit −82/−87 −72/−86 −71/−86 +46/−97 dBc dBc dBc dBm/dBc +46/−99 dBm/dBc +46/−98 dBm/dBc −85 dBc −74 dBc −70 dBc 2.43 1.63 1.51 10.88 9.2 8.54 nV/√Hz nV/√Hz nV/√Hz dB dB dB −69/−66 −56/−65 −58/−66 +35/−78 dBc dBc dBc dBm/dBc +35/−81 dBm/dBc +37/−85 dBm/dBc −73 dBc −75 dBc −72 dBc 2.64 1.6 1.48 11.56 9.06 8.17 nV/√Hz nV/√Hz nV/√Hz dB dB dB ADL5565 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Output Voltage Swing × Bandwidth Product Supply Voltage, VCC VIPx, VINx ±IOUT Maximum Internal Power Dissipation θJA θJC Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 2000 V p-p MHz 5.25 V VCC + 0.5 V 30 mA 525 mW 52°C/W 34.6°C/W 125°C −40°C to +100°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 9 of 28 ADL5565 13 GND 14 GND 16 GND 15 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIP2 1 12 ENBL ADL5565 TOP VIEW VIN1 3 11 VOP 10 VON 9 VCOM VCC 8 VCC 7 VCC 5 VCC 6 VIN2 4 NOTES 1. EXPOSED PADDLE IS INTERNALLY CONNECT TO GND AND MUST BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. 09959-002 VIP1 2 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VIP2 2 VIP1 3 VIN1 4 VIN2 5, 6, 7, 8 9 VCC VCOM 10 11 12 13, 14, 15, 16, Exposed Paddle VON VOP ENBL GND Description Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to VIP1 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to VIP2 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to VIN2 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to VIN1 for AV = 15.5 dB. Positive Supply. Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and output common mode floats to midsupply (VCC/2). Balanced Differential Output. Biased to VCOM, typically ac-coupled. Balanced Differential Output. Biased to VCOM, typically ac-coupled. Enable. Apply positive voltage (1.3 V < ENBL < VCC) to activate device. Ground. Exposed paddle is internally connected to GND and must be soldered to a low impedance ground plane. Rev. 0 | Page 10 of 28 ADL5565 TYPICAL PERFORMANCE CHARACTERISTICS VS = 3.3 V, VCM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified ac-coupled differential input and differential output, unless otherwise noted. 25 25 AV = 15.5dB AV = 12dB AV = 6dB 20 20 10 OP1dB (dBm) 5 0 –5 15 10 –10 5 –15 –25 10 100 1000 10000 FREQUENCY (MHz) 0 09959-003 –20 AV = 15dB AV = 12dB AV = 6dB 0 15 100 150 200 250 FREQUENCY (MHz) Figure 6. OP1dB vs. Frequency at Three Gains, 25°C, 200 Ω Differential Load, VPOS = 3.3 V Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load, AV = 6 dB, AV = 12 dB, and AV = 15.5 dB, VPOS = 3.3 V and VPOS = 5 V, 25°C 20 50 09959-005 VOLTAGE GAIN (dB) 15 25 –40°C +85°C +25°C +100°C –40°C +25°C +85°C +100°C 20 5 OP1dB (dBm) VOLTAGE GAIN (dB) 10 0 –5 –10 15 10 5 100 1000 10000 FREQUENCY (MHz) 0 09959-004 15 18 –40°C +25°C +85°C +100°C 16 150 200 250 AV = 6dB AV = 12dB AV = 15.5dB 14 NOISE FIGURE (dB) 5 0 –5 –10 12 10 8 6 –15 4 –20 2 100 1000 10000 FREQUENCY (MHz) Figure 5. Gain vs. Frequency Response for 200 Ω Differential Load, AV = 6 dB, Four Temperatures, VPOS = 5 V, 25°C 0 10 09959-105 VOLTAGE GAIN (dB) 100 Figure 7. OP1dB vs. Frequency for 200 Ω Differential Load, AV = 6 dB, Four Temperatures, VPOS = 3.3 V 10 –25 10 50 FREQUENCY (MHz) Figure 4. Gain vs. Frequency Response for 200 Ω Differential Load, AV = 6 dB, Four Temperatures, VPOS = 3.3 V, 25°C 20 0 100 FREQUENCY (MHz) 1000 09959-007 –20 10 09959-006 –15 Figure 8. Noise Figure vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB, VPOS = 3.3 V Rev. 0 | Page 11 of 28 ADL5565 18 60 AV = 6dB AV = 12dB AV = 15.5dB 16 50 40 10 8 30 5V, –40°C 5V, +25°C 5V, +85°C 5V, +100°C 3.3V, –40°C 3.3V, +25°C 3.3V, +85°C 3.3V, +100°C 20 6 4 10 2 100M 1G FREQUENCY (Hz) Figure 9. Noise Figure vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB, VPOS = 5 V 3.5 150 200 250 300 350 400 450 500 70 60 50 3.0 2.5 2.0 1.5 40 30 20 3.3V, AV = 6dB 3.3V, AV = 12dB 3.3V, AV = 15.5dB 5V, AV = 6dB 5V, AV = 12dB 5V, AV = 15.5dB 1.0 10 0.5 100 1000 FREQUENCY (MHz) 0 09959-009 0 10 60 0 2 3 4 5 6 7 8 9 10 3.3V, AV = 6dB 3.3V, AV = 12dB 3.3V, AV = 15.5dB 5V, AV = 6dB 5V, AV = 12dB 5V, AV = 15.5dB –20 –40 IMD3 (dBc) 40 30 1 Figure 13. Output Third-Order Intercept (OIP3) vs. Power (POUT), Frequency 100 MHz, AV = 15.5 dB, VPOS = 3.3 V and VPOS = 5 V 5V, AV = 6dB 5V, AV = 12dB 5V, AV = 15.5dB 3.3V, AV = 6dB 3.3V, AV = 12dB 3.3V, AV = 15.5dB 50 0 POUT/TONE (dBm) Figure 10. Noise Spectral Density vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB, VPOS = 3.3 V and VPOS = 5 V OIP3 (dBm) 100 Figure 12. Output Third-Order Intercept (OIP3) vs. Frequency, Over Temperature, Output Level at 2 V p-p Composite, RL = 200 Ω, Av = 6 dB, VPOS = 3.3 V and VPOS = 5 V, Four Temperatures OIP3 (dBm) NOISE SPECTRAL DENSITY (nV/√Hz) 4.0 50 FREQUENCY (MHz) AV = 6dB AV = 12dB AV = 15.5dB AV = 6dB AV = 12dB AV = 15.5dB 4.5 0 09959-012 5.0 0 09959-008 0 10M 09959-011 12 OIP3 (dBm) NOISE FIGURE (dB) 14 –60 –80 20 –100 10 50 100 150 200 250 300 FREQUENCY (MHz) 350 400 450 500 –140 Figure 11. Output Third-Order Intercept (OIP3) at Three Gains, Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V 0 50 100 150 200 250 300 FREQUENCY (MHz) 350 400 450 500 09959-013 0 09959-010 0 –120 Figure 14. Output IMD3 vs. Frequency, Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V Rev. 0 | Page 12 of 28 3.3V, –40°C 3.3V, +25°C 3.3V, +85°C 3.3V, +100°C 5V, –40°C 5V, +25°C 5V, +85°C 5V, +100°C –20 HD2 (dBc) –60 –80 0 –60 –20 –80 –40 –100 –60 –120 –80 –100 –140 –120 –160 –140 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) –180 09959-014 IMD3 (dBm) –40 –40 50 100 150 200 250 300 HD3, HD3, HD3, HD3, HD3, HD3, HD3, HD3, 350 5V, –40°C 5V, +25°C 5V, +85C 5V, +100°C 3.3V, –40°C 3.3V, +25°C 3.3V, +85°C 3.3V, +100°C 400 450 –100 –120 –140 500 Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency, Over Temperature, Output Level at 2 V p-p Composite, RL = 200 Ω, AV = 6 dB, VPOS = 3.3 V and VPOS = 5 V, Four Temperatures –60 AV = 5.3dB AV = 10.3dB AV = 13dB 50 0 5V, –40°C 5V, +25°C 5V, +85°C 5V, +100°C 3.3V, –40°C 3.3V, +25°C 3.3V, +85°C 3.3V, +100°C FREQUENCY (MHz) Figure 15. IMD3 vs. Frequency, Over Temperature, Output Level at 2 V p-p Composite, RL = 200 Ω, AV = 6 dB, VPOS = 3.3 V and VPOS = 5 V, Four Temperatures 55 HD2, HD2, HD2, HD2, HD2, HD2, HD2, HD2, 09959-017 0 HD3 (dBc) ADL5565 0 3.3V, HD2 5V, HD2 3.3V, HD3 5V, HD3 –80 –20 –100 –40 –120 –60 –140 –80 –160 –100 –180 –120 35 30 50 100 150 200 250 FREQUENCY (MHz) –200 –6 –80 –40 –100 –60 –120 –80 –140 –100 –180 0 50 100 150 200 250 300 FREQUENCY (MHz) HD3, HD3, HD3, HD3, HD3, HD3, 350 3.3V, AV = 6dB 3.3V, AV = 12dB 3.3V, AV = 15.5dB 5V, AV = 6dB 5V, AV = 12dB 5V, AV = 15.5dB 400 450 2 4 6 8 –140 10 5V 5V 3.3V 3.3V –40 –60 –80 –100 –120 –140 500 HD2, HD3, HD2, HD3, –20 HD2 AND HD3 (dBc) –20 HD3 (dBc) –60 0 09959-016 HD2 (dBc) 0 3.3V, AV = 6dB 3.3V, AV = 12dB 3.3V, AV = 15.5dB 5V, AV = 6dB 5V, AV = 12dB 5V, AV = 15.5dB 0 Figure 19. Harmonic Distortion vs. Output Power per Tone, Frequency = 100 MHz, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V –40 HD2, HD2, HD2, HD2, HD2, HD2, –2 POUT/TONE (dBm) Figure 16. Single-Ended OIP3 vs. Frequency –160 –4 Figure 17. Harmonic Distortion (HD2/HD3) vs. Frequency, Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V Rev. 0 | Page 13 of 28 –120 1.0 1.5 2.0 2.5 VCOM Figure 20. Harmonic Distortion (HD2/HD3) vs. VCOM, AV = 6 dB, VPOS = 3.3 V and VPOS = 5 V 3.0 09959-019 0 09959-015 25 HD3 (dBc) 40 09959-018 HD2 (dBc) OIP3 (dBm) 45 ADL5565 90 HD2 AV = 5.3dB HD2 AV = 10.3dB HD2 AV = 13dB HD3 AV = 5.3dB HD3 AV = 10.3dB HD3 AV = 13dB –65 –70 80 70 –75 –80 –85 50 40 –90 30 –95 20 –100 10 –105 0 50 100 150 200 250 300 0 10 FREQUENCY (MHz) 100 09959-021 CMRR (dB) 60 09959-020 1000 FREQUENCY (MHz) Figure 21. Single-Ended Harmonic Distortion (HD2/HD3) vs. Frequency, Figure 24. Common-Mode Rejection Ratio (CMRR) vs. Frequency 3.5 GROUP DELAY (ns) 3.0 3 1 2.5 2.0 1.5 1.0 50Ω B W 8:0G 25GS/s 2ns/DIV A CH3 832mV 0 0 500 100 1500 2000 2500 3000 FREQUENCY (MHz) Figure 22. ENBL Time Domain Response 09959-024 CH3 400mV/DIV CH1 70.4mV 09959-022 0.5 Figure 25. Group Delay vs. Frequency 0 REVERSE ISOLATION (dB) –10 1 –20 –30 –40 –50 –60 CH1 340mV CH2 1.025V 25GS/s 2ns/DIV A CH2 10mV 09959-023 –70 –80 10 100 1000 FREQUENCY (GHz) Figure 23. Large Signal Pulse Response, AV = 15.5 dB Figure 26. Reverse Isolation (S12) vs. Frequency AV = 6 dB Rev. 0 | Page 14 of 28 09959-025 HARMONIC DISTORTION HD2, HD3 (dBc) –60 45 600 40 500 35 400 30 300 25 200 20 100 15 0 10 100 1000 10 FREQUENCY (MHz) 80 5V 7 90 6 75 5 60 4 45 3 30 2 15 0 10 1 RS 100 1000 FREQUENCY (MHz) 0 09959-128 8 105 EQUIVALENT SERIES OUTPUT INDUCTANCE (nH) EQUIVALENT SERIES OUTPUT RESISTANCE (Ω) 120 9 LS 60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 29. ISUPPLY vs. Temperature, RL = 200 Ω, AV = 6 dB, VPOS = 3.3 V and VPOS = 5 V 10 135 3.3V 70 65 Figure 27. S11 Equivalent RLC Parallel Network, AV = 6 dB 150 75 Figure 28. S22 Equivalent RLC Parallel Network, AV = 6 dB Rev. 0 | Page 15 of 28 100 09959-027 700 85 ISUPPLY (mA) 50 EQUIVALENT PARALLEL INPUT CAPACITANCE (pF) 800 09959-026 EQUIVALENT PARALLEL INPUT RESISTANCE (Ω) ADL5565 ADL5565 CIRCUIT DESCRIPTION BASIC STRUCTURE The ADL5565 is a low noise, fully differential amplifier/ADC driver that can operate from 2.8 V to 5.2 V. It provides three gain options, 6 dB, 12 dB, and 15.5 dB, without the need for external resistors and has wide bandwidths of greater than 6 GHz for all gains. Differential input impedance is 200 Ω for 6 dB, 100 Ω for 12 dB, and 67 Ω for 15.5 dB. It has a differential output impedance of 10 Ω. 0.1µF 200Ω + 1/ 2 VIP2 RS 5Ω 50Ω VIP1 100Ω 1/ 2 RL VIN1 100Ω VIN2 RS 50Ω 5Ω 200Ω + 0.1µF 09959-032 AC Figure 30. Basic Structure The ADL5565 is composed of a fully differential amplifier with on-chip feedback and feed forward resistors. The two feedforward resistors on each input set this pin-strappable amplifier in three different gain configurations of 6 dB, 12 dB, and 15.5 dB, and by using two external resistors, any gain from 0 dB to 15.5 dB can be realized. The amplifier is designed to provide high differential open-loop gain and an output common-mode circuit that enables the user to change the common-mode voltage from the VCOM pin. The amplifier is designed to provide superior low distortion at frequencies up to and beyond 300 MHz with low noise and low power consumption from a 3.3 V power supply at 70 mA. The ADL5565 is very flexible in terms of I/O coupling. It can be ac-coupled or dc-coupled at the inputs and/or the outputs within the specified input and output common-mode levels. The input of the device can be configured as single-ended or differential with similar third-order distortion performance. Due to the internal connections between the inputs and outputs, an output common-mode voltage between 1.4 V and 1.8 V at 3.3 V and 1.4 V to 3 V at 5 V must be maintained for the best distortion. For a dc-coupled input, the input common mode should be between 1.2 V and 2 V at the 3.3 V supply, and 1.2 V to 3.8 V at the 5 V supply. The device has been characterized using 2 V p-p into a 200 Ω ac-coupled output. If the inputs are ac-coupled, the input and output common-mode voltages are set by VCC/2 when no external circuitry is used. The ADL5565 provides an output common-mode voltage set by VCOM, which allows driving an ADC directly without external components. Although distortion is similar over the specified frequency range at both 3.3 V and 5 V, lower distortion results on the 5 V supply for signal swings larger than 2 V p-p. Rev. 0 | Page 16 of 28 ADL5565 APPLICATIONS INFORMATION is applied to VIN2, the gain is 12 dB (middle gain). When Input A is applied to both VIP1 and VIP2 and Input B is applied to both VIN1 and VIN2, the gain is 15.5 dB (maximum gain). BASIC CONNECTIONS Figure 31 shows the basic connections for operating the ADL5565. Apply a voltage between 3 V and 5 V to the VCC pins, and decouple each supply pin with at least one low inductance, 0.1 μF surface-mount ceramic capacitor, placed as close as possible to the device. Also, decouple the VCOM pin (Pin 9) using a 0.1 μF capacitor. Pin 1 to Pin 4, Pin 10, and Pin 11 are biased at 1/2 VCC above ground and can be dc-coupled (if within the specified input or output common-mode voltage levels) or ac-coupled as shown in Figure 31. To enable the ADL5565, the ENBL pin must be pulled high. Pulling the ENBL pin low puts the ADL5565 in sleep mode, reducing the current consumption to 5 mA at ambient. The gain of the part is determined by the pin-strappable input configuration. When Input A is applied to VIP1 and Input B is applied to VIN1, the gain is 6 dB (minimum gain, see Equation 1 and Equation 2). When Input A is applied to VIP2 and Input B VCC RS/2 0.1µF 15 GND 14 GND 2 VIP1 AC 13 GND ENBL 12 VOP 11 ADL5565 3 VIN1 0.1µF B VCOM 9 4 VIN2 VCC 5 VCC 10µF 0.1µF RL BALANCED LOAD VON 10 VCC 6 0.1µF VCC 7 0.1µF Figure 31. Basic Connections Rev. 0 | Page 17 of 28 VCC 8 0.1µF 0.1µF 09959-033 A RS/2 BALANCED SOURCE 16 GND 1 VIP2 ADL5565 INPUT AND OUTPUT INTERFACING Single-Ended Input to Differential Output The ADL5565 can be configured as a differential input to differential output driver, as shown in Figure 32. The resistors, R1 and R2, combined with the ETC1-1-13 balun transformer, provide a 50 Ω input match for the three input impedances that change with the variable gain strapping. The input and output 0.1 μF capacitors isolate the VCC/2 bias from the source and balanced load. The load should equal 200 Ω to provide the expected ac performance (see the Specifications section and the Typical Performance Characteristics section). The ADL5565 can also be configured in a single-ended input to differential output driver, as shown in Figure 34. In this configuration, the gain of the part is reduced due to the application of the signal to only one side of the amplifier. The strappable gain values are listed in Table 7 with the required terminations to match to a 50 Ω source using R1 and R2. The input and output 0.1 μF capacitors isolate the VCC/2 bias from the source and the balanced load. The performance for this configuration is shown in Figure 16 and Figure 21. 3V TO 5V 3V TO 5V 0.1µF 0.1µF VIN2 + RL 2 R2 VIN1 B AC + R1 VIP1 + 0.1µF VIN2 RL 2 RL 2 + AC 50Ω VIN1 B RL 2 0.1µF VIP2 A + 0.1µF 0.1µF + + VIP1 R2 50Ω 0.1µF VIP2 A + ETC1-1-13 0.1µF R1 Figure 32. Differential Input to Differential Output Configuration Table 5. Differential Termination Values for Figure 32 R1 (Ω) 29 33 40.2 Figure 34. Single-Ended Input to Differential Output Configuration R2 (Ω) 29 33 40.2 Table 7. Single-Ended Termination Values for Figure 34 The differential gain of the ADL5565 is dependent on the source impedance and load, as shown in Figure 33. 0.1µF R1 (Ω) 30 30 30 + 5Ω 50Ω 200Ω VIP1 100Ω VIN1 100Ω 0.1µF 50Ω 5Ω 200Ω RS R2 + VIN2 + (1) In Equation 1, RG is the gain setting resistor (see Figure 1). Table 6. Values of RG for Differential Gain Gain (dB) 6 12 15.5 RG (Ω) 100 50 33.5 Rev. 0 | Page 18 of 28 50Ω 5Ω 0.1µF RL 2 RL 2 + RL 200 × RG 10 + R L 0.1µF VIN1 100Ω Figure 33. Differential Input Loading Circuit AV = VIP1 100Ω AC The differential gain can be determined using the following formula. The values of RG for each gain configuration are shown in Table 6. 5Ω 50Ω + VIN2 VIP2 0.1µF + 1/ R 2 S RL 09959-035 AC R2 (Ω) 73 104 154 The single-ended gain configuration of the ADL5565 is dependent on the source impedance and load, as shown in Figure 35. 200Ω VIP2 1/ R 2 S Gain (dB) 5.3 10.3 13 0.1µF 200Ω R1 Figure 35. Single-Ended Input Loading Circuit 09959-037 Gain (dB) 6 12 15.5 09959-036 NOTES 1. FOR 5.3dB GAIN (AV = 1.84), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1. 2. FOR 10.3dB GAIN (AV = 3.3), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2. 3. FOR 13dB GAIN (AV = 4.5), CONNECT INPUT A TO BOTH VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2. 09959-034 NOTES 1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1. 2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2. 3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2. ADL5565 The necessary shunt component, RSHUNT, to match to the source impedance, RS, can be expressed as The single-ended gain can be determined using the following formula. The values of RG and RX for each gain configuration are shown in Table 8. R + RS RL R2 200 AV 1 = × × X × RX 10 + R L ⎛ R S × R2 ⎞ R S + R 2 ⎟ RG + ⎜⎜ ⎟ ⎝ R S + R2 ⎠ RSHUNT = (2) The insertion loss and the resultant power gain for multiple shunt resistor values are summarized in Table 9. The source resistance and input impedance need careful attention when using Equation 3, Equation 4, and Equation 5. The reactance of the input impedance of the ADL5565 and the ac coupling capacitors must be considered before assuming that they make a negligible contribution. Table 8. Values of RG and RX for Single-Ended Gain RG (Ω)1 100 50 33.5 1 2 RX (Ω) R2 || 1582 R2 || 962 R2 || 742 RG is the gain setting resistor (see Figure 1). These values are based on a 50 Ω input match. Table 9. Differential Gain Adjustment Using Series Resistor GAIN ADJUSTMENT AND INTERFACING The effective gain of the ADL5565 can be reduced using a number of techniques. A matched attenuator network can reduce the effective gain; however, this requires the addition of a separate component that can be prohibitive in size and cost. Instead, a simple voltage divider can be implemented using the combination of additional series resistors at the amplifier input and the input impedance of the ADL5565, as shown in Figure 36. A pair of resistors is used to match to the impedance of the previous stage. AC 1/ R 2 S 0.1µF 1/2 RSERIES 1/ 2 VIN1 VIN2 RSHUNT 0.1µF 1/2 RSERIES VIP1 ADL5565 VIP2 1/ R 2 SHUNT 09959-038 1/ R 2 S Figure 36. Gain Adjustment Using a Series Resistor Figure 36 shows a typical implementation of the divider concept that effectively reduces the gain by adding attenuation at the input. For frequencies less than 100 MHz, the input impedance of the ADL5565 can be modeled as a real 66 Ω, 100 Ω, or 200 Ω resistance (differential) for maximum, middle, and minimum gains, respectively. Assuming that the frequency is low enough to ignore the shunt reactance of the input and high enough so that the reactance of moderately sized ac coupling capacitors can be considered negligible, the insertion loss, Il, due to the shunt divider can be expressed as ⎛ RG Il(dB) = 20 log ⎜⎜ R ⎝ SERIES + RG (5) In Equation 5, RG is the gain setting resistor (see Figure 1). In Equation 2, RG is the gain setting resistor (see Figure 1). Gain (dB) 5.3 10.3 13 1 1 1 − RS RSERIES + RG ⎞ ⎟ ⎟ ⎠ Gain (dB) 01 11 21 31 41 51 61 72 82 92 102 112 122 133 143 15.53 1 RS (Ω) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 Differential RSERIES (Ω) 200 154 118 84.5 52.3 24.9 0 78.7 59 42.2 26.7 12.7 0 23.7 13.7 0 Differential RSHUNT (Ω)5 57.6 57.6 59 60.4 61.9 64.9 66.5 69.8 73.2 76.8 82.5 88.7 100 113 133 200 Amplifier is configured for 6 dB gain setting. Amplifier is configured for 12 dB gain setting. Amplifier is configured for 15.5 dB gain setting. 4 RG is the gain setting resistor (see Figure 1). 5 The resistor values are rounded to the nearest real resistor value. 2 3 (3) In Equation 3, RG is the gain setting resistor (see Figure 1). Adjusted Gain (dB) = 6 dB, 12 dB, or 15.5 dB Gain – Il (dB) Differential RG (Ω)4 200 200 200 200 200 200 200 100 100 100 100 100 100 66.7 66.7 66.7 (4) Rev. 0 | Page 19 of 28 ADL5565 ADC INTERFACING Applying a full-scale, single-tone signal from the ADL5565, an SFDR of 89.2 dBc is realized (see Figure 37). Applying two halfscale signals from the ADL5565 in a gain of 6 dB, an SFDR of 87.5 dBc is achieved at 100 MHz (see Figure 38). The bandwidth of the circuit in Figure 40 is shown in Figure 39. 0 –30 FUNDAMENTAL1 = –7.078dBFS FUNDAMENTAL2 = –7.169dBFS IMD (2f1 – f2) = –88.237dBc IMD (2f2 + f1) = –91.37dBc NOISE FLOOR = –115.96dB AMPLITUDE (dBFS) –30 –45 –60 –75 –90 F1 – F2 –105 2F1 – F2 2F2 – F1 2F2 – 2F1 2F1 – 2F2 F2 – F1 –120 –150 0 15 30 45 60 75 90 105 120 FREQUENCY (MHz) 09959-041 –135 Figure 38. Measured Two-Tone Performance of the Circuit in Figure 40 for a 100 MHz Input Signal 0 –1 GAIN = 6dB SNR = 69.44dBc SFDR = 89.2dBc SECOND = –85.1dBc THIRD = –89.3dBc NOISE FLOOR = –115.7dB –15 –45 –60 –2 –3 –4 –90 2 + 5 4 –105 –5 3 6 200 100 300 400 500 FREQUENCY (MHz) –120 Figure 39. Measured Frequency Response of the Wideband ADC Interface Depicted in Figure 40 –135 0 15 30 45 60 75 90 105 120 FREQUENCY (MHz) The wideband frequency response is an advantage in broadband applications, such as predistortion receiver designs and instrumentation applications. However, by designing for a wide analog input frequency range, the cascaded SNR performance is somewhat degraded due to high frequency noise aliasing into the wanted Nyquist zone. Figure 37. Measured Single-Tone Performance of the Circuit in Figure 40 for a 100 MHz Input Signal 0.1µF B VIN1 VIN2 VOP 0.1µF ADL5565 VON 0.1µF + 40Ω VIP1 33Ω + 40Ω VIP2 + AC 0.1µF A ETC1-1-13 + 50Ω VIN+ AD9467 33Ω VIN– Figure 40. Wideband ADC Interfacing Example Featuring the AD9467 Rev. 0 | Page 20 of 28 16 16-BIT ADC 09959-039 –150 0 09959-042 –75 09959-049 AMPLITUDE (dBFS) 0 –15 NORMALIZED (dBFS) The ADL5565 is a high output linearity amplifier that is optimized for ADC interfacing. There are several options available to the designer when using the ADL5565. Figure 40 uses a wideband 1:1 transmission line balun followed by two 40 Ω resistors in parallel with the three input impedances (which change with the gain selection of the ADL5565) to provide a 50 Ω differential impedance and provides a wideband match to a 50 Ω source. The ADL5565 is ac-coupled from the AD9467 to avoid commonmode dc loading. The 33 Ω resistors improve the isolation between the ADL5565 and any switching currents present at the analogto-digital, sample-and-hold circuitry. The AD9467 input presents a 530 Ω differential load impedance and requires a 2 V to 2.5 V differential input swing to reach full scale (VREF = 1 V to 1.25 V). This circuit provides variable gain, isolation, and source matching for the AD9467. ADL5565 capacitance and a portion of the capacitance presented by C4 to form a resonant tank circuit. The resonant tank helps to ensure that the ADC input looks like a real resistance at the target center frequency. The inductor, L5, shorts the ADC inputs at dc, which introduces a zero into the transfer function. In addition, the ac coupling capacitors introduce additional zeros into the transfer function. The final overall frequency response takes on a bandpass characteristic, helping to reject noise outside of the intended Nyquist zone. Table 10 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed to help compensate for actual PCB parasitics. By designing a narrow band-pass antialiasing filter between the ADL5565 and the target ADC, the output noise of the ADL5565 outside of the intended Nyquist zone can be attenuated, helping to preserve the available SNR of the ADC. In general, the SNR improves several decibels when including a reasonable order antialiasing filter. In this example, a low loss 1:1 input transformer is used to match the ADL5565 balanced input to a 50 Ω unbalanced source, resulting in minimum insertion loss at the input. Figure 41 is optimized for driving some of Analog Devices popular ADCs, such as the AD9467. Table 10 includes antialiasing filter component recommendations for popular IF sampling frequencies. Inductor L5 works in parallel with the on-chip ADC input 1nF 4Ω L1 L3 105Ω C2 1nF 4Ω L1 C4 L3 CML L5 AD9467 09959-043 ADL5565 105Ω Figure 41. Narrow-Band IF Sampling Solution for an ADC Application Table 10. Interface Filter Recommendations for Various IF Sampling Frequencies Center Frequency (MHz) 96 140 170 211 1 dB Bandwidth (MHz) 30 40 32 33 L1 (nH) 3.3 3.3 3.3 3.3 Rev. 0 | Page 21 of 28 C2 (pF) 47 47 56 47 L3 (nH) 27 27 27 27 C4 (pF) 75 27 18 15 L5 (nH) 82 150 120 51 ADL5565 LAYOUT CONSIDERATIONS many board designs, the signal trace widths should be minimal where the driver/receiver is no more than one-eighth of the wave-length from the amplifier. This nontransmission line configuration requires that underlying and adjacent ground and low impedance planes be dropped from the signal lines. High-Q inductive drives and loads, as well as stray transmission line capacitance in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. If RF transmission lines connecting the input or output are used, design them such that stray capacitance at the input/output pins is minimized. In R3 R1 0.1µF R4 ETC1-1-13 VIP2 0.1µF VIP1 VOP R9 R7 ETC1-1-13 ADL5565 R5 VIN1 0.1µF R6 VON 0.1µF R10 VIN2 09959-044 R2 SPECTRUM ANALYZER R8 Figure 42. General-Purpose Characterization Circuit Table 11. Gain Setting and Input Termination Components for Figure 42 AV (dB) 6 12 15.5 R1 (Ω) 29 33 40.2 R2 (Ω) 29 33 40.2 R3 (Ω) Open 0 0 R4 (Ω) 0 Open 0 R9 (Ω) 34.8 R10 (Ω) 34.8 R5 (Ω) 0 Open 0 R6 (Ω) Open 0 0 Table 12. Output Matching Network for Figure 42 RL (Ω) 200 R7 (Ω) 84.5 R8 (Ω) 84.5 R3 R1 R4 PORT 1 VIP2 VIP1 R9 VOP R7 PORT 2 ADL5565 R8 R5 VIN1 R2 R6 VON PORT 4 R10 VIN2 09959-045 PORT 3 Figure 43. Differential Characterization Circuit Using Agilent E8357A Four-Port PNA Table 13. Gain Setting and Input Termination Components for Figure 43 AV (dB) 6 12 15.5 R1 (Ω) 100 Open Open R2 (Ω) 100 Open Open R3 (Ω) Open 0 0 R4 (Ω) 0 Open 0 R9 (Ω) Open R10 (Ω) Open Table 14. Output Matching Network for Figure 43 RL (Ω) 200 R7 (Ω) 50 R8 (Ω) 50 Rev. 0 | Page 22 of 28 R5 (Ω) 0 Open 0 R6 (Ω) Open 0 0 ADL5565 Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6 and leaving R3 and R4 open. R1 and R2 must be 50 Ω for a 50 Ω input impedance. SOLDERING INFORMATION On the underside of the chip-scale package, there is an exposed compressed paddle. This paddle is internally connected to the ground of the chip. Solder the paddle to the low impedance ground plane on the PCB to ensure the specified electrical performance and to provide thermal relief. To further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias. For the maximum gain (15.5 dB into a 200 Ω load), both inputs are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1 and R2 are open for a 50 Ω input impedance. The balanced input and output interfaces are converted to single ended with a pair of baluns (M/A-COM ETC1-1-13). The balun at the input, T1, provides a 50 Ω single-ended-todifferential transformation. The output balun, T2, and the matching components are configured to provide a 200 Ω to 50 Ω impedance transformation with an insertion loss of about 11 dB. EVALUATION BOARD Figure 44 shows the schematic of the ADL5565 evaluation board. The board is powered by a single supply in the 3 V to 5 V range. The power supply is decoupled by 10 μF and 0.1 μF capacitors. Table 15 details the various configuration options of the evaluation board. Figure 45 and Figure 46 show the component and circuit side layouts of the evaluation board. As an alternative, the input transformer, T1, can be replaced with one of the following transformers to provide a low loss balanced input to the ADL5565. To realize the minimum gain (6 dB into a 200 Ω load), Input 1 (VIN1 and VIP1) must be used by installing 0 Ω resistors at R3 and R4, leaving R5 and R6 open. R1 and R2 must be 33.2 Ω for a 50 Ω input impedance. • 6 dB gain configuration, Mini-Circuits TC4-1W+ • 12 dB gain configuration, Mini-Circuits, TC2-1T+ • 15.5 dB gain configuration, Mini-Circuits TC1.5-52T When using these alternative transformers, R1 and R2 are left open. Replace C1 and C2 with 0 Ω jumpers and add a 0.1 μF capacitor to C12. GND J1 R1 OPEN C12 OPEN R12 OPEN C2 0.01µF R2 OPEN R3 0Ω R4 0Ω R6 0Ω J2 OPEN VPOS R13 0Ω R5 0Ω C3 10µF 15 14 13 GND GND GND GND 1 VIP2 ENBL 12 2 VIP1 VOP 11 3 VIN1 ADL5565 4 VIN2 VCC 5 VON 10 VCC 6 VCOM 9 VCC VCC 7 ENBL VPOS P1 AGND C9 0.01µF C10 0.01µF 8 C5 0.1µF C6 0.1µF R9 34.8Ω R8 84.5Ω R10 34.8Ω C11 0.1µF C7 0.1µF Figure 44. Evaluation Board Schematic Rev. 0 | Page 23 of 28 T2 R7 84.5Ω VCOM C4 0.1µF C8 0.1µF R11 OPEN C13 OPEN R15 OPEN J3 J4 OPEN R14 0Ω 09959-046 C1 0.01µF T1 16 ADL5565 Table 15. Evaluation Board Configuration Options Component VPOS, GND C3, C4, C5, C6, C7, C11 J1, J2, R1, R2, R3, R4, R5, R6, R12, R13, C1, C2, C12, T1 J3, J4, R7, R8, R9, R10, R11, R14, R15 C9, C10, C13, T2 ENBL, P1, C8 Description Ground and supply vector pins. Power supply decoupling. The supply decoupling consists of a 10 μF capacitor (C3) to ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground. Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun to transform a single-ended input into a balanced differential signal. Removing R13, installing R12 (0 Ω), and installing an SMA connector (J2) allows driving from a differential source. C1 and C2 provide ac coupling. C12 is a bypass capacitor. R1 and R2 provide a differential 50 Ω input termination. R3 to R6 are used to select the input for the pin-strappable gain. The maximum gain is R3, R4, R5, R6 = 0 Ω and R1 and R2 = open. The middle gain is R5 and R6 = 0 Ω, R3 and R4 = open, and R1 and R2 = 50 Ω. The minimum gain is R3 and R4 = 0 Ω, R5 and R6 = open, and R1 and R2 = 33.2 Ω. Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio balun to transform a balanced differential signal to a single-ended signal. Removing R14, installing R15 (0 Ω), and installing an SMA connector (J4) allows differential loading. C13 is a bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of matching components. The evaluation board is configured to provide a 200 Ω to 50 Ω impedance transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling. Device enabled. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label, the ENBL pin is connected to the supply, enabling the device. In the opposite direction, toward the GND label, the ENBL pin is grounded, putting the device in power-down mode. Default Condition VPOS, GND = installed C3 = 10 μF (Size D), C4, C5, C6, C7, C11 = 0.1 μF (Size 0402) J1 = installed, J2 = not installed, R1, R2 = open, R3, R4, R5, R6, R13 = 0 Ω (Size 0402), R12, = open, C1, C2 = 0.01 μF (Size 0402), C12 = open, T1 = ETC1-1-13 (M/A-COM) J3 = installed, J4 = not installed, R7, R8 = 84.5 Ω (Size 0402), R9, R10 = 34.8 Ω (Size 0402), R11, R15 = open (Size 0402), R14 = 0 Ω (Size 0402) C9, C10 = 0.01 μF (Size 0402), C13 = open T2 = ETC1-1-13 (M/A-COM) ENBL, P1 = installed, C8 = 0.1 μF (Size 0402) Table 16. Differential Values for Figure 44 Gain (dB) 6 12 15.5 R1 (Ω) 29 33 Open R2 (Ω) 29 33 Open Table 17. Alternative Differential Input Configuration for Figure 44 Gain (dB) 6 12 15.5 R1 and R2 (Ω) Open Open Open C12 (μF) 0.1 0.1 0.1 C1 and C2 (Ω) 0 0 0 Rev. 0 | Page 24 of 28 T1 Mini Circuits TC4-1W+ Mini Circuits TC2-1T+ Mini Circuits TC1.5-52T+ Figure 45. Layout of Evaluation Board, Component Side 09959-048 09959-047 ADL5565 Figure 46. Layout of Evaluation Board, Circuit Side Rev. 0 | Page 25 of 28 ADL5565 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 16 13 1 12 1.65 1.50 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229. 091609-A 3.10 3.00 SQ 2.90 Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-27) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5565ACPZ-R7 ADL5565-EVALZ 1 Temperature Range −40°C to + 85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part Rev. 0 | Page 26 of 28 Package Option CP-16-27 ADL5565 NOTES Rev. 0 | Page 27 of 28 ADL5565 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09959-0-10/11(0) Rev. 0 | Page 28 of 28