a Y2 +VS TOP VIEW (Not to Scale) FLEXIBILITY OF OPERATION The AD532 multiplies in four quadrants with a transfer function of (X1 – X 2)(Y 1 – Y 2)/10 V, divides in two quadrants with a 10 V Z/(X1 – X2) transfer function, and square roots in one quadrant with a transfer function of ±√ 10 V Z. In addition to these basic functions, the differential X and Y inputs provide significant operating flexibility both for algebraic computation and transducer instrumentation applications. Transfer functions, such as XY/10 V, (X2 – Y2)/10 V, ± X2/10 V and 10 V Z/(X1 – X2), are easily attained and are extremely useful in many modulation and function generation applications, as well as in trigonometric calculations for airborne navigation and guidance applications, where the monolithic construction and small size of the AD532 offer considerable system advantages. In addition, the high CMRR (75 dB) of the differential inputs makes the AD532 especially well qualified for instrumentation applications, as it can provide an output signal that is the product of two transducergenerated input signals. +VS 13 Y1 12 Y2 –VS 3 AD532 VOS TOP VIEW (Not to Scale) 10 NC 5 GND X2 NC 4 11 NC 6 9 X2 X1 7 8 NC –VS Z NC +VS 3 2 1 20 19 Y1 OUT NC = NO CONNECT –VS 4 18 Y2 NC 5 17 NC 16 VOS 15 NC 14 GND NC 7 AD532 TOP VIEW (Not to Scale) NC 8 X2 10 11 12 13 NC 9 NC The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of ± 1.0% and a ± 10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks (such as the AD530). 14 X1 OUT NC 6 PRODUCT DESCRIPTION GND AD532 Z Z 1 OUT 2 VOS Y1 X1 APPLICATIONS Multiplication, Division, Squaring, Square Rooting Algebraic Computation Power Measurements Instrumentation Applications Available in Chip Form PIN CONFIGURATIONS NC FEATURES Pretrimmed to ⴞ1.0% (AD532K) No External Components Required Guaranteed ⴞ1.0% max 4-Quadrant Error (AD532K) Diff Inputs for (X 1 – X 2) (Y 1 – Y2 )/10 V Transfer Function Monolithic Construction, Low Cost Internally Trimmed Integrated Circuit Multiplier AD532 NC = NO CONNECT GUARANTEED PERFORMANCE OVER TEMPERATURE The AD532J and AD532K are specified for maximum multiplying errors of ± 2% and ± 1% of full scale, respectively at +25°C, and are rated for operation from 0°C to +70°C. The AD532S has a maximum multiplying error of ± 1% of full scale at +25°C; it is also 100% tested to guarantee a maximum error of ±4% at the extended operating temperature limits of –55°C and +125°C. All devices are available in either the hermeticallysealed TO-100 metal can, TO-116 ceramic DIP or LCC packages. J, K and S grade chips are also available. ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE MONOLITHIC AD532 1. True ratiometric trim for improved power supply rejection. 2. Reduced power requirements since no networks across supplies are required. 3. More reliable since standard monolithic assembly techniques can be used rather than more complex hybrid approaches. 4. High impedance X and Y inputs with negligible circuit loading. 5. Differential X and Y inputs for noise rejection and additional computational flexibility. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD532–SPECIFICATIONS (@ +25ⴗC, VS = ⴞ15 V, R ≥ 2 k⍀ VOS grounded) Model AD532J Typ Min Max Min AD532K Typ Max Min AD532S Typ Max Units MULTIPLIER PERFORMANCE Transfer Function Total Error (–10 V ≤ X, Y ≤ +10 V) TA = Min to Max Total Error vs. Temperature Supply Rejection (± 15 V ± 10%) Nonlinearity, X (X = 20 V pk-pk, Y = 10 V) Nonlinearity, Y (Y = 20 V pk-pk, X = 10 V) Feedthrough, X (Y Nulled, X = 20 V pk-pk 50 Hz) Feedthrough, Y (X Nulled, Y = 20 V pk-pk 50 Hz) Feedthrough vs. Temperature Feedthrough vs. Power Supply DYNAMICS Small Signal BW (VOUT = 0.1 rms) 1% Amplitude Error Slew Rate (VOUT 20 pk-pk) Settling Time (to 2%, ∆VOUT = 20 V) NOISE Wideband Noise f = 5 Hz to 10 kHz Wideband Noise f = 5 Hz to 5 MHz OUTPUT Output Voltage Swing Output Impedance (f ≤ 1 kHz) Output Offset Voltage Output Offset Voltage vs. Temperature Output Offset Voltage vs. Supply INPUT AMPLIFIERS (X, Y and Z) Signal Voltage Range (Diff. or CM Operating Diff) CMRR Input Bias Current X, Y Inputs X, Y Inputs TMIN to TMAX Z Input Z Input T MIN to TMAX Offset Current Differential Resistance DIVIDER PERFORMANCE Transfer Function (Xl > X2 ) Total Error (VX = –10 V, –10 V ≤ VZ ≤ +10 V) (VX = –1 V, –10 V ≤ VZ ≤ +10 V) SQUARE PERFORMANCE (X1 – X 2 )(Y1 – Y 2 ) (X1 – X 2 )(Y1 – Y 2 ) (X1 – X 2 )(Y1 – Y 2 ) 10 V 10 V 10 V ± 10 ± 1.5 ± 2.5 ± 0.04 ± 0.05 ± 0.8 ± 0.3 ⴞ2.0 ± 0.7 ± 1.5 ± 0.03 ± 0.05 ± 0.5 ± 0.2 ⴞ1.0 50 200 30 100 30 2.0 ± 0.25 150 25 1.0 ± 0.25 80 Total Error SQUARE ROOTER PERFORMANCE Transfer Function Total Error (0 V ≤ VZ ≤ 10 V) POWER SUPPLY SPECIFICATIONS Supply Voltage Rated Performance Operating Supply Current Quiescent PACKAGE OPTIONS TO-116 (D-14) TO-100 (H-10A) LCC (E-20A) ⴞ1.0 ⴞ4.0 ⴞ0.04 % % %/°C %/% % % 30 100 mV 25 1.0 ± 0.25 80 mV mV p-p/°C mV/% ± 0.01 ± 0.05 ± 0.5 ± 0.2 1 75 45 1 1 75 45 1 1 75 45 1 MHz kHz V/µs µs 0.6 3.0 0.6 3.0 0.6 3.0 mV (rms) mV (rms) ± 13 1 V Ω mV mV/°C mV/% ± 13 1 ± 40 0.7 ± 2.5 ± 10 ± 13 1 ± 10 ⴞ30 0.7 ± 2.5 ± 10 ± 2.5 ± 10 40 1.5 8 ±5 ± 25 ± 0.1 10 10 V Z/(X1 – X2 ) 10 V Z/(X1 – X2) ±2 ±4 ±1 ±3 4 1.5 8 ±5 ± 25 ± 0.1 10 ⴞ15 2 10 V 10 V 10 V 4 ± 0.4 –√10 V Z ± 1.0 ± 10 ⴞ18 6 ± 15 4 AD532JD AD532JH AD532KD AD532KH Specifications subject to change without notice. µA µA µA µA µA MΩ % % 2 (X1 – X 2 ) ± 15 ⴞ15 ±1 ±3 (X1 – X 2 ) –√10 V Z ± 1.5 4 10 V Z/(X1 – X2 ) (X1 – X 2 ) ± 10 V dB 50 3 10 ± 10 ± 30 ± 0.3 10 ± 0.8 ⴞ30 2.0 ± 10 50 2 Transfer Function ± 0.5 ⴞ18 ± 10 6 ± 0.4 % –√10 V Z ± 1.0 % ± 15 4 ± 22 V V 6 mA AD532SD AD532SH AD532SE/883B Thermal Characteristics Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. –2– H-10A: θ JC = 25°C/W; θJA = 150°C/W E-20A: θ JC = 22°C/W; θJA = 85°C/W D-14: θ JC = 22°C/W; θJA = 85°C/W REV. B AD532 ORDERING GUIDE CHIP DIMENSIONS AND BONDING DIAGRAM Model Temperature Ranges Package Descriptions Package Options AD532JD AD532JD/+ AD532KD AD532KD/+ AD532JH AD532KH AD532J Chip AD532SD AD532SD/883B JM38510/13903BCA AD532SE/883B AD532SH AD532SH/883B JM38510/13903BIA AD532S Chip 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Header Header Chip Side Brazed DIP Side Brazed DIP Side Brazed DIP LCC Header Header Header Chip D-14 D-14 D-14 D-14 H-10A H-10A Contact factory for latest dimensions. Dimensions shown in inches and (mm). D-14 D-14 D-14 E-20A H-10A H-10A H-10A FUNCTIONAL DESCRIPTION The functional block diagram for the AD532 is shown in Figure 1, and the complete schematic in Figure 2. In the multiplying and squaring modes, Z is connected to the output to close the feedback around the output op amp. (In the divide mode, it is used as an input terminal.) The X and Y inputs are fed to high impedance differential amplifiers featuring low distortion and good common-mode rejection. The amplifier voltage offsets are actively laser trimmed to zero during production. The product of the two inputs is resolved in the multiplier cell using Gilbert’s linearized transconductance technique. The cell is laser trimmed to obtain VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used to obtain low output impedance and make possible self-contained operation. The residual output voltage offset can be zeroed at VOS in critical applications . . . otherwise the VOS pin should be grounded. Figure 1. Functional Block Diagram Figure 2. Schematic Diagram REV. B –3– AD532 AD532 PERFORMANCE CHARACTERISTICS AC FEEDTHROUGH Multiplication accuracy is defined in terms of total error at +25°C with the rated power supply. The value specified is in percent of full scale and includes XIN and YIN nonlinearities, feedback and scale factor error. To this must be added such application-dependent error terms as power supply rejection, common-mode rejection and temperature coefficients (although worst case error over temperature is specified for the AD532S). Total expected error is the rms sum of the individual components since they are uncorrelated. AC feedthrough is a measure of the multiplier’s zero suppression. With one input at zero, the multiplier output should be zero regardless of the signal applied to the other input. Feedthrough as a function of frequency for the AD532 is shown in Figure 5. It is measured for the condition VX = 0, VY = 20 V (p-p) and VY = 0, VX = 20 V (p-p) over the given frequency range. It consists primarily of the second harmonic and is measured in millivolts peak-to-peak. Accuracy in the divide mode is only a little more complex. To achieve division, the multiplier cell must be connected in the feedback of the output op amp as shown in Figure 13. In this configuration, the multiplier cell varies the closed loop gain of the op amp in an inverse relationship to the denominator voltage. Thus, as the denominator is reduced, output offset, bandwidth and other multiplier cell errors are adversely affected. The divide error and drift are then ⑀m × 10 V/X1 – X2) where ⑀m represents multiplier full-scale error and drift, and (X1–X2) is the absolute value of the denominator. NONLINEARITY Nonlinearity is easily measured in percent harmonic distortion. The curves of Figures 3 and 4 characterize output distortion as a function of input signal level and frequency respectively, with one input held at plus or minus 10 V dc. In Figure 4 the sine wave amplitude is 20 V (p-p). Figure 5. Feedthrough vs. Frequency COMMON-MODE REJECTION The AD532 features differential X and Y inputs to enhance its flexibility as a computational multiplier/divider. Common-mode rejection for both inputs as a function of frequency is shown in Figure 6. It is measured with X1 = X2 = 20 V (p-p), (Y1 – Y2) = +10 V dc and Y1 = Y2 = 20 V (p-p), (X1 – X2) = +10 V dc. Figure 6. CMRR vs. Frequency Figure 3. Percent Distortion vs. Input Signal Figure 4. Percent Distortion vs. Frequency Figure 7. Frequency Response, Multiplying –4– REV. B AD532 DYNAMIC CHARACTERISTICS NOISE CHARACTERISTICS The closed loop frequency response of the AD532 in the multiplier mode typically exhibits a 3 dB bandwidth of 1 MHz and rolls off at 6 dB/octave thereafter. Response through all inputs is essentially the same as shown in Figure 7. In the divide mode, the closed loop frequency response is a function of the absolute value of the denominator voltage as shown in Figure 8. All AD532s are screened on a sampling basis to assure that output noise will have no appreciable effect on accuracy. Typical spot noise vs. frequency is shown in Figure 10. Stable operation is maintained with capacitive loads to 1000 pF in all modes, except the square root for which 50 pF is a safe upper limit. Higher capacitive loads can be driven if a 100 Ω resistor is connected in series with the output for isolation. Figure 10. Spot Noise vs. Frequency APPLICATIONS CONSIDERATIONS The performance and ease of use of the AD532 is achieved through the laser trimming of thin-film resistors deposited directly on the monolithic chip. This trimming-on-the-chip technique provides a number of significant advantages in terms of cost, reliability and flexibility over conventional in-package trimming of off-the-chip resistors mounted or deposited on a hybrid substrate. Figure 8. Frequency Response, Dividing POWER SUPPLY CONSIDERATIONS Although the AD532 is tested and specified with ± 15 V dc supplies, it may be operated at any supply voltage from ± 10 V to ± 18 V for the J and K versions, and ± 10 V to ± 22 V for the S version. The input and output signals must be reduced proportionately to prevent saturation; however, with supply voltages below ± 15 V, as shown in Figure 9. Since power supply sensitivity is not dependent on external null networks as in the AD530 and other conventionally nulled multipliers, the power supply rejection ratios are improved from 3 to 40 times in the AD532. First and foremost, trimming on the chip eliminates the need for a hybrid substrate and the additional bonding wires that are required between the resistors and the multiplier chip. By trimming more appropriate resistors on the AD532 chip itself, the second input terminals that were once committed to external trimming networks (e.g., AD530) have been freed to allow fully differential operation at both the X and Y inputs. Further, the requirement for an input attenuator to adjust the gain at the Y input has been eliminated, letting the user take full advantage of the high input impedance properties of the input differential amplifiers. Thus, the AD532 offers greater flexibility for both algebraic computation and transducer instrumentation applications. Finally, provision for fine trimming the output voltage offset has been included. This connection is optional, however, as the AD532 has been factory-trimmed for total performance as described in the listed specifications. REPLACING OTHER IC MULTIPLIERS Existing designs using IC multipliers that require external trimming networks (such as the AD530) can be simplified using the pin-for-pin replaceability of the AD532 by merely grounding the X2, Y2 and VOS terminals. (The VOS terminal should always be grounded when unused.) Figure 9. Signal Swing vs. Supply REV. B –5– AD532 single-ended positive inputs (0 V to +10 V), connect the input to X2 and the offset null to X1. For optimum performance, gain (S.F.) and offset (X0) adjustments are recommended as shown and explained in Table I. APPLICATIONS MULTIPLICATION Z X1 X2 AD532 Y1 Y2 VOUT OUT VOS VOUT = (OPTIONAL) (X1 – X2) (Y1 – Y2) 10V For practical reasons, the useful range in denominator input is approximately 500 mV ≤ |(X1 – X2)| ≤ 10 V. The voltage offset adjust (VOS), if used, is trimmed with Z at zero and (X1 – X2) at full scale. 20kV +VS Table I. Adjust Procedure (Divider or Square Rooter) –VS Figure 11. Multiplier Connection For operation as a multiplier, the AD532 should be connected as shown in Figure 11. The inputs can be fed differentially to the X and Y inputs, or single-ended by simply grounding the unused input. Connect the inputs according to the desired polarity in the output. The Z terminal is tied to the output to close the feedback loop around the op amp (see Figure 1). The offset adjust VOS is optional and is adjusted when both inputs are zero volts to obtain zero out, or to buck out other system offsets. DIVIDER With: Adjust Scale Factor X0 (Offset) SQUARE ROOTER Adjust With: for: Adjust for: X Z VOUT –10 V +10 V –10 V –1 V +0.1 V –1 V Z +10 V +0.1 V VOUT –10 V –1 V Repeat if required. SQUARE ROOT SQUARE Z X1 X2 Z AD532 Y1 Y2 +VS VOS –VS VOUT = VIN2 10V 2.2kV 20kV +VS DIVISION Z VOUT = 10VZ X Z AD532 Y1 Y2 +VS +VS OUT VOUT Figure 14. Square Rooter Connection DIFFERENCE OF SQUARES –VS 47kV X1 X2 X 10kV 20kV 20kV (X0) +VS Y –VS 20kV –Y Z AD532 VOUT OUT Y1 Y2 +VS VOS –VS 10kV Figure 13. Divider Connection The AD532 can be configured as a two-quadrant divider by connecting the multiplier cell in the feedback loop of the op amp and using the Z terminal as a signal input, as shown in Figure 13. It should be noted, however, that the output error is given approximately by 10 V ⑀m/(X1 – X2), where ⑀m is the total error specification for the multiply mode; and bandwidth by fm × (X1 – X2)/10 V, where fm is the bandwidth of the multiplier. Further, to avoid positive feedback, the X input is restricted to negative values. Thus for single-ended negative inputs (0 V to –10 V), connect the input to X and the offset null to X2; for –VS The connections for square root mode are shown in Figure 14. Similar to the divide mode, the multiplier cell is connected in the feedback of the op amp by connecting the output back to both the X and Y inputs. The diode D1 is connected as shown to prevent latch-up as ZIN approaches 0 volts. In this case, the VOS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to obtain –1.0 V dc in the output, VOUT = – √10 V Z. For optimum performance, gain (S.F.) and offset (X0) adjustments are recommended as shown and explained in Table I. 1kV (SF) 2.2kV 10kV 20kV (X0) The squaring circuit in Figure 12 is a simple variation of the multiplier. The differential input capability of the AD532, however, can be used to obtain a positive or negative output response to the input . . . a useful feature for control applications, as it might eliminate the need for an additional inverter somewhere else. X1 X2 –VS 47kV –VS Figure 12. Squarer Connection X VOUT OUT 1kV (SF) (OPTIONAL) VIN AD532 Y1 Y2 +VS VOUT OUT VOUT = 10VZ Z X1 X2 VOUT = X2 – Y2 10V (OPTIONAL) 20kV AD741KH +VS –VS Figure 15. Differential of Squares Connection The differential input capability of the AD532 allows for the algebraic solution of several interesting functions, such as the difference of squares, X2 – Y2/10 V. As shown in Figure 15, the AD532 is configured in the square mode, with a simple unity gain inverter connected between one of the signal inputs (Y) and one of the inverting input terminals (–YIN) of the multiplier. The inverter should use precision (0.1%) resistors or be otherwise trimmed for unity gain for best accuracy. –6– REV. B AD532 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.005 (0.13) MIN C136g–0–6/99 Side Brazed DIP (D-14) 0.098 (2.49) MAX 14 8 0.310 (7.87) 0.220 (5.59) 1 7 PIN 1 0.785 (19.94) MAX 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.150 (3.81) MAX 0.023 (0.58) 0.014 (0.36) 0.015 (0.38) 0.008 (0.20) 0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC Leadless Chip Carrier (E-20A) 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.358 (9.09) 0.342 (8.69) SQ 0.095 (2.41) 0.075 (1.90) 0.358 (9.09) MAX SQ TOP VIEW 0.200 (5.08) BSC 0.100 (2.54) BSC 0.015 (0.38) MIN 3 19 18 20 4 0.028 (0.71) 0.022 (0.56) 1 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF BOTTOM VIEW 14 13 0.050 (1.27) BSC 8 9 45° TYP 0.055 (1.40) 0.045 (1.14) 0.088 (2.24) 0.054 (1.37) 0.150 (3.81) BSC Metal Can (H-10A) 0.185 (4.70) 0.165 (4.19) 0.050 (1.27) MAX 0.250 (6.35) MIN 0.160 (4.06) 0.110 (2.79) 6 5 0.335 (8.51) 0.305 (7.75) 0.230 (5.84) BSC 0.370 (9.40) 0.335 (8.51) 7 4 8 3 9 2 0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25) 0.019 (0.48) 0.016 (0.41) 0.115 (2.92) BSC 0.021 (0.53) 0.016 (0.41) BASE & SEATING PLANE REV. B –7– 10 1 0.034 (0.86) 0.027 (0.69) 36 ° BSC 0.045 (1.14) 0.027 (0.69) PRINTED IN U.S.A. REFERENCE PLANE 0.750 (19.05) 0.500 (12.70)

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