AD AD9763-EBZ

FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-/12-/14-bit dual transmit digital-to-analog converters (DACs)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual-port or interleaved data
On-chip 1.2 V reference
5 V or 3.3 V operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
DVDD1/ DCOM1/
DVDD2 DCOM2
WRT1/IQWRT
WRT2/IQSEL
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767 are dual-port, high speed,
2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates
two high quality TxDAC+® cores, a voltage reference, and digital
interface circuitry into a small 48-lead LQFP. The AD9763/
AD9765/AD9767 offer exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9763/AD9765/AD9767 have been optimized for
processing I and Q data in communications applications. The
digital interface consists of two double-buffered latches as well
as control logic. Separate write inputs allow data to be written to
the two DAC ports independent of one another. Separate clocks
control the update rate of the DACs.
A mode control pin allows the AD9763/AD9765/AD9767 to
interface to two separate data ports, or to a single interleaved
high speed data port. In interleaving mode, the input data
stream is demuxed into its original I and Q data and then
latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the
Gain Control Mode section for important date code
information on this feature.
ACOM
1
LATCH
PORT1
DIGITAL
INTERFACE
AD9763/
AD9765/
AD9767
2
LATCH
PORT2
MODE
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
AVDD
CLK1
1
DAC
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
2
DAC
IOUTA2
IOUTB2
CLK2/IQ RESET
00617-001
Data Sheet
10-/12-/14-Bit, 125 MSPS
Dual TxDAC+ Digital-to-Analog Converters
AD9763/AD9765/AD9767
Figure 1.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or
AD9767 can be simultaneously updated and can provide a
nominal full-scale current of 20 mA. The full-scale currents
between each DAC are matched to within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an
advanced, low cost CMOS process. They operate from a single
supply of 3.3 V to 5 V and consume 380 mW of power.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9763/AD9765/AD9767 are members of a pincompatible family of dual TxDACs providing 8-, 10-, 12-,
and 14-bit resolution.
Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high
performance DACs for each part is optimized for low
distortion performance and provides flexible transmission
of I and Q information.
Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
Low Power. Complete CMOS dual DAC function operates on
380 mW from a 3.3 V to 5 V single supply. The DAC full-scale
current can be reduced for lower power operation, and a sleep
mode is provided for low power idle periods.
On-Chip Voltage Reference. The AD9763/AD9765/AD9767
each include a 1.20 V temperature-compensated band gap
voltage reference.
Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767
each feature a flexible dual-port interface, allowing dual or
interleaved input data.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved.
AD9763/AD9765/AD9767
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Digital Inputs .............................................................................. 24 Applications....................................................................................... 1 DAC Timing................................................................................ 24 General Description ......................................................................... 1 Sleep Mode Operation............................................................... 26 Functional Block Diagram .............................................................. 1 Power Dissipation....................................................................... 26 Product Highlights ........................................................................... 1 Applying the AD9763/AD9765/AD9767 .................................... 28 Revision History ............................................................................... 2 Output Configurations .............................................................. 28 Specifications..................................................................................... 5 Differential Coupling Using a Transformer............................ 28 DC Specifications ......................................................................... 5 Differential Coupling Using an Op Amp................................ 28 Dynamic Specifications ............................................................... 6 Single-Ended, Unbuffered Voltage Output............................. 29 Digital Specifications ................................................................... 7 Single-Ended, Buffered Voltage Output Configuration........ 29 Absolute Maximum Ratings............................................................ 8 Power and Grounding Considerations.................................... 29 Thermal Resistance ...................................................................... 8 Applications Information .............................................................. 31 ESD Caution.................................................................................. 8 VDSL Example Applications Using the
AD9765 and AD9767 ................................................................ 31 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 AD9763 ........................................................................................ 11 AD9765 ........................................................................................ 14 AD9767 ........................................................................................ 17 Terminology .................................................................................... 20 Theory of Operation ...................................................................... 21 Functional Description.............................................................. 21 Reference Operation .................................................................. 22 Gain Control Mode .................................................................... 22 Quadrature Amplitude Modulation (QAM) Example Using
the AD9763 ................................................................................. 32 CDMA ......................................................................................... 33 Evaluation Board ............................................................................ 34 General Description................................................................... 34 Schematics................................................................................... 34 Evaluation Board Layout........................................................... 40 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42 Setting the Full-Scale Current................................................... 22 DAC Transfer Function ............................................................. 23 Analog Outputs........................................................................... 23 REVISION HISTORY
Revision History: AD9763/AD9765/AD9767
Revision History: AD9763
8/11—Rev. F to Rev. G
Changes to Gain Control Mode Section and Setting the FullScale Current Section..................................................................... 22
Changes to DAC Transfer Function Section............................... 23
Changes to Power Supply Rejection Section............................... 29
1/08—Rev. D to Rev. E
Combined with AD9765 and AD9767 Data Sheets.......Universal
Changes to Figure 1...........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Added Figure 4 and Figure 5............................................................9
Changes to Table 6.......................................................................... 10
Change to Typical Performance Characteristics Section
Conditions Statement .................................................................... 11
Added Figure 23 to Figure 56 ....................................................... 14
Added Note to Figure 58 ............................................................... 20
Changes to Functional Description Section ............................... 22
Changes to Figure 59 and Figure 60............................................. 22
Changes to Gain Control Mode Section ..................................... 22
6/09—Rev. E to Rev. F
Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91,
Deleted Original Figure 91 to Figure 94...................................... 34
1/08—Revision E: Initial Combined Version
Rev. G | Page 2 of 44
Data Sheet
AD9763/AD9765/AD9767
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section.......................................................22
Changes to DAC Transfer Section ................................................23
Change to Analog Outputs Section ..............................................24
Changes to Dual-Port Mode Timing............................................24
Changes to Interleaved Mode Timing Section ............................25
Added Figure 64 ..............................................................................25
Change to Differential Coupling Using a Transformer Section .....28
Changes to Power and Grounding Considerations Section............30
Added VDSL Example Applications Using the AD9765 and
AD9767 Section...............................................................................31
Added Figure 79 to Figure 82 ........................................................31
Changes to Figure 84 ......................................................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
9/06—Rev. C to Rev. D
Updated Format.................................................................. Universal
Renumbered Figures.......................................................... Universal
Changes to Specifications Section...................................................3
Changes to Applications Section...................................................21
Updated Outline Dimensions........................................................32
Changes to Ordering Guide...........................................................32
10/01—Rev. B to Rev. C
Changes to Figure 29 ......................................................................21
Changes to Interleaved Mode Timing Section............................25
Added Figure 64 ..............................................................................25
Changes to Power and Grounding Considerations Section............30
Added Figure 80 and Figure 82 .....................................................31
Changes to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section.............................................32
Changes to Figure 83 and Figure 84 .............................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
9/06—Rev. B to Rev. C
Updated Format ................................................................. Universal
Changes to Figure 2 ..........................................................................5
Changes to Figure 3 ..........................................................................7
Changes to Functional Description Section................................12
Changes to Figure 25 and Figure 26 .............................................15
Changes to Figure 28 and Figure 29 .............................................16
Changes to Power Dissipation Section.........................................17
Changes to Power and Grounding Considerations Section......19
Changes to Figure 39 ......................................................................19
Changes to Figure 45 ......................................................................22
Changes to Evaluation Board Section ..........................................24
Changes to Figure 47 ......................................................................24
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................30
2/00—Rev. A to Rev. B
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Revision History: AD9765
Revision History: AD9767
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9767 Data Sheets ...... Universal
Changes to Figure 1...........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Change to Absolute Maximum Ratings .........................................8
Added Figure 3 and Figure 5 ...........................................................9
Changes to Table 6 ..........................................................................10
Added Figure 6 to Figure 22 ..........................................................11
Added Figure 40 to Figure 56 ........................................................17
Added Note to Figure 58 ................................................................20
Changes to Functional Description Section ................................22
Changes to Reference Operation Section ....................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section ......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section.......................................................22
Changes to DAC Transfer Section ................................................23
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9765 Data Sheets ...... Universal
Changes to Figure 1 ..........................................................................1
Changes to Features Section ............................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Change to Absolute Maximum Ratings .........................................8
Added Figure 3 and Figure 4 ...........................................................9
Changes to Table 6 ..........................................................................10
Added Figure 6 to Figure 39 ..........................................................11
Added Note to Figure 58 ................................................................20
Changes to Functional Description Section................................22
Changes to Reference Operation Section ....................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section ......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section ......................................................22
Changes to DAC Transfer Section ................................................23
Rev. G | Page 3 of 44
AD9763/AD9765/AD9767
Data Sheet
Changes to Dual-Port Mode Timing ........................................... 24
Changes to Interleaved Mode Timing Section ........................... 25
Added Figure 64.............................................................................. 25
Change to Differential Coupling Using a Transformer Section......28
Changes to Power and Grounding Considerations Section............30
Added Figure 79 and Figure 81..................................................... 31
Added to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section ............................................ 32
Added Figure 83 and Figure 84..................................................... 32
Changes to CDMA Section ........................................................... 33
Changes to Figure 85 Caption....................................................... 33
Changes to Figure 86...................................................................... 34
Changes to Figure 88...................................................................... 36
Changes to Ordering Guide .......................................................... 40
10/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 2...........................................................................5
Changes to Figure 3...........................................................................7
Changes to Functional Description Section ............................... 12
Changes to Figure 25 and Figure 26............................................. 15
Changes to Figure 28 and Figure 29............................................. 16
Changes to Power Dissipation Section ........................................ 18
Changes to Figure 39...................................................................... 19
Changes to Power and Grounding Considerations Section ..... 19
Changes to Figure 45...................................................................... 22
Changes to Figure 47...................................................................... 24
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 28
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Rev. G | Page 4 of 44
Data Sheet
AD9763/AD9765/AD9767
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
AD9763
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
TA = 25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = 25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift Without Internal Reference
Gain Drift with Internal Reference
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Digital Supply Current (IDVDD) 5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation 6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio 7 —AVDD
Power Supply Rejection Ratio7—DVDD
OPERATING RANGE
AD9765
Min
10
Typ
Max
−1
±0.1
+1
−0.5
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.07
±0.25
±1
±0.1
Typ
Max
Min
14
Typ
Max
−1.5
−2.0
±0.4
+1.5
+2.0
−3.5
−4.0
±1.5
+3.5
+4.0
+0.5
−0.75
−1.0
±0.3
+0.75
+1.0
−2.5
−3.0
±1.0
+2.5
+3.0
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
100
5
1.14
1.20
100
0.1
3
2.7
AD9767
Min
12
±0.25
±1
±0.1
100
5
1.26
1.14
1.25
0.1
1.20
100
±0.25
±1
±0.1
1.14
1.25
0.1
1.20
100
LSB
LSB
LSB
LSB
LSB
LSB
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
1.25
100
5
1.26
Unit
Bits
1
0.5
1
0.5
1
0.5
V
MΩ
MHz
0
±50
±100
±50
0
±50
±100
±50
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
5
5
71
5
8
380
5.5
5.5
75
7
15
12.0
410
420
450
3
2.7
450
5
5
71
5
8
380
5.5
5.5
75
7
15
12.0
410
420
450
3
2.7
450
5
5
71
5
8
380
5.5
5.5
75
7
15
12.0
410
420
450
mW
–0.4
–0.025
+0.4
+0.025
–0.4
–0.025
+0.4
+0.025
–0.4
–0.025
+0.4
+0.025
mW
% of FSR/V
% of FSR/V
–40
+85
–40
+85
–40
+85
°C
1
450
V
V
mA
mA
mA
mA
mW
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5
Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6
Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz.
7
±10% power supply variation.
2
3
Rev. G | Page 5 of 44
AD9763/AD9765/AD9767
Data Sheet
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω
doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK)
Output Settling Time (tST) to 0.1% 1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS, fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLK = 65 MSPS, fOUT = 1.00 MHz
fCLK = 65 MSPS, fOUT = 2.51 MHz
fCLK = 65 MSPS, fOUT = 5.02 MHz
fCLK = 65 MSPS, fOUT = 14.02 MHz
fCLK = 65 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Spurious-Free Dynamic Range Within a Window
fCLK = 100 MSPS, fOUT = 1.00 MHz; 2 MHz Span
fCLK = 50 MSPS, fOUT = 5.02 MHz; 10 MHz Span
fCLK = 65 MSPS, fOUT = 5.03 MHz; 10 MHz Span
fCLK = 125 MSPS, fOUT = 5.04 MHz; 10 MHz Span
Total Harmonic Distortion
fCLK = 100 MSPS, fOUT = 1.00 MHz
fCLK = 50 MSPS, fOUT = 2.00 MHz
fCLK = 125 MSPS, fOUT = 4.00 MHz
fCLK = 125 MSPS, fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
Channel Isolation
fCLK = 125 MSPS, fOUT = 10 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
1
Min
AD9763
Typ Max
125
Min
AD9765
Typ Max
125
35
1
5
2.5
2.5
50
30
Min
AD9767
Typ Max
125
35
1
5
2.5
2.5
50
30
Unit
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
69
78
74
69
61
79
78
75
66
55
67
60
70
81
77
72
70
81
79
78
68
55
67
60
71
82
77
73
70
82
80
79
70
55
67
70
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
78
85
80
82
82
80
90
88
88
88
82
91
88
88
88
dBc
dBc
dBc
dBc
−77
−77
−74
−72
−69
−80
−78
−75
−75
–70
−81
−79
−83
−80
−71
dBc
dBc
dBc
dBc
76
74
71
67
80
79
77
75
80
79
78
76
dBc
dBc
dBc
dBc
85
77
85
77
85
77
dBc
dBc
Measured single-ended into 50 Ω load.
Rev. G | Page 6 of 44
Data Sheet
AD9763/AD9765/AD9767
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V
Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulse Width (tLPW, tCPW)
Min
Typ
3.5
2.1
5
3
0
Max
1.3
0.9
+10
+10
0
−10
−10
5
2.0
1.5
3.5
Timing Diagram
See Table 3 and the DAC Timing section for more information about the timing specifications.
tS
tH
DATA IN
(WRT2) (WRT1/IQWRT)
tLPW
(CLK2) (CLK1/IQCLK)
IOUTA
OR
IOUTB
tPD
Figure 2. Timing Diagram for Dual and Interleaved Modes
Rev. G | Page 7 of 44
00617-002
tCPW
Unit
V
V
V
V
μA
μA
pF
ns
ns
ns
AD9763/AD9765/AD9767
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
AVDD
DVDD1, DVDD2
ACOM
AVDD
MODE,
CLK1/IQCLK,
CLK2/IQRESET,
WRT1/IQWRT,
WRT2/IQSEL
Digital Inputs
IOUTA1/IOUTA2,
IOUTB1/IOUTB2
REFIO, FSADJ1,
FSADJ2
GAINCTRL, SLEEP
Junction
Temperature
Storage
Temperature
Range
Lead Temperature
(10 sec)
With
Respect To
ACOM
DCOM1/DCOM2
DCOM1/DCOM2
DVDD1/DVDD2
DCOM1/DCOM2
DCOM1/DCOM2
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +0.3 V
−6.5 V to +6.5 V
−0.3 V to DVDD1/
DVDD2 + 0.3 V
Table 5. Thermal Resistance
Package Type
48-Lead LQFP
ESD CAUTION
ACOM
−0.3 V to DVDD1/
DVDD2 + 0.3 V
−1.0 V to AVDD + 0.3 V
ACOM
−0.3 V to AVDD + 0.3 V
ACOM
−0.3 V to AVDD + 0.3 V
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. G | Page 8 of 44
θJA
91
Unit
°C/W
Data Sheet
AD9763/AD9765/AD9767
SLEEP
ACOM
IOUTA2
IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1
IOUTA1
AVDD
MODE
ACOM
IOUTA2
IOUTB2
SLEEP
48 47 46 45 44 43 42
41 40 39 38 37
41 40 39 38 37
DB13P1 (MSB) 1
36
DB0P2 (LSB)
35
DB1P2
DB11P1 3
34
DB2P2
DB10P1
4
33
DB3P2
32 DB0P2 (LSB)
DB9P1
5
32
DB4P2
31 DB1P2
DB8P1
6
31
DB5P2
30 DB2P2
DB7P1
7
30
DB6P2
8
29 DB3P2
DB6P1
8
29
DB7P2
DB1P1 9
28 DB4P2
DB5P1 9
28
DB8P2
DB0P1 (LSB) 10
27 DB5P2
DB4P1 10
27
DB9P2
NC 11
26 DB6P2
DB3P1 11
26
DB10P2
NC 12
25 DB7P2
DB2P1 12
25
DB11P2
36 NC
DB12P1
DB7P1 3
34 NC
DB6P1
4
33 NC
DB5P1
5
DB4P1
6
DB3P1
7
DB2P1
SLEEP
ACOM
IOUTA2
IOUTB2
GAINCTRL
REFIO
FSADJ1
IOUTB1
IOUTA1
AVDD
MODE
FSADJ2
41 40 39 38 37
DB11P1 (MSB) 1
36
NC
35
NC
DB9P1 3
34
DB0P2 (LSB)
DB8P1
4
33
DB1P2
DB7P1
5
32
DB2P2
DB6P1
6
31
DB3P2
DB5P1
7
30
DB4P2
DB4P1
8
29
DB5P2
DB3P1 9
28
DB6P2
DB2P1 10
27
DB7P2
DB1P1 11
26
DB8P2
DB0P1 (LSB) 12
25
DB9P2
DB10P1
PIN 1
2
AD9765
TOP VIEW
(Not to Scale)
00617-004
DB10P2
DB11P2 (MSB)
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
WRT1/IQWRT
DVDD1
DCOM1
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
DB12P2
DB13P2 (MSB)
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
DB1P1
00617-003
DB9P2 (MSB)
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
WRT1/IQWRT
DVDD1
DCOM1
NC
NC
DB8P2
Figure 5. AD9767 Pin Configuration
Figure 3. AD9763 Pin Configuration
48 47 46 45 44 43 42
TOP VIEW
(Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
AD9767
WRT1/IQWRT
AD9763
TOP VIEW
(Not to Scale)
PIN 1
2
DVDD1
2
DCOM1
PIN 1
35 NC
DB8P1
DB0P1 (LSB)
DB9P1 (MSB) 1
Figure 4. AD9765 Pin Configuration
Rev. G | Page 9 of 44
00617-005
48 47 46 45 44 43 42
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1
IOUTA1
AVDD
MODE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9763/AD9765/AD9767
Data Sheet
Table 6. Pin Function Descriptions
AD9763
1 to 10
11 to 14,
33 to 36
15, 21
16, 22
17
18
19
20
23 to 32
37
38
39, 40
41
42
43
44
45, 46
47
48
Pin No.
AD9765
1 to 12
13, 14,
35, 36
15, 21
16, 22
17
18
19
20
23 to 34
37
38
39, 40
41
42
43
44
45, 46
47
48
AD9767
1 to 14
N/A
Mnemonic
DBxP1
NC
Description
Data Bit Pins (Port 1)
No Connect
15, 21
16, 22
17
18
19
20
23 to 36
37
38
39, 40
41
42
43
44
45, 46
47
48
DCOM1, DCOM2
DVDD1, DVDD2
WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
DBxP2
SLEEP
ACOM
IOUTA2, IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1, IOUTA1
AVDD
MODE
Digital Common
Digital Supply Voltage
Input Write Signal for PORT 1 (IQWRT in Interleaving Mode)
Clock Input for DAC1 (IQCLK in Interleaving Mode)
Clock Input for DAC2 (IQRESET in Interleaving Mode)
Input Write Signal for PORT 2 (IQSEL in Interleaving Mode)
Data Bit Pins (Port 2)
Power-Down Control Input
Analog Common
Port 2 Differential DAC Current Outputs
Full-Scale Current Output Adjust for DAC2
Master/Slave Resistor Control Mode
Reference Input/Output
Full-Scale Current Output Adjust for DAC1
Port 1 Differential DAC Current Outputs
Analog Supply Voltage
Mode Select (1 = dual port, 0 = interleaved)
Rev. G | Page 10 of 44
Data Sheet
AD9763/AD9765/AD9767
TYPICAL PERFORMANCE CHARACTERISTICS
AD9763
AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,
unless otherwise noted.
90
80
0dBFS
75
–6dBFS
fCLK = 5MSPS
70
SFDR (dBc)
SFDR (dBc)
80
fCLK = 25MSPS
70
60
fCLK = 65MSPS
60
–12dBFS
65
55
fCLK = 125MSPS
fOUT (MHz)
0
5
10
15
20
25
30
35
60
70
00617-010
100
30
35
00617-011
10
00617-006
1
00617-009
50
50
fOUT (MHz)
Figure 9. SFDR vs. fOUT @ 65 MSPS
Figure 6. SFDR vs. fOUT @ 0 dBFS
80
80
0dBFS
75
0dBFS
–6dBFS
70
SFDR (dBc)
SFDR (dBc)
75
70
–6dBFS
65
–12dBFS
60
–12dBFS
55
65
0.5
1.0
1.5
2.0
2.5
fOUT (MHz)
50
00617-007
0
0
10
20
30
40
50
fOUT (MHz)
Figure 7. SFDR vs. fOUT @ 5 MSPS
Figure 10. SFDR vs. fOUT @ 125 MSPS
80
80
IOUTFS = 20mA
0dBFS
75
75
SFDR (dBc)
70
–12dBFS
65
IOUTFS = 10mA
60
65
IOUTFS = 5mA
55
50
60
0
2
4
6
8
fOUT (MHz)
10
12
00617-008
SFDR (dBc)
70
–6dBFS
0
5
10
15
20
25
fOUT (MHz)
Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Figure 8. SFDR vs. fOUT @ 25 MSPS
Rev. G | Page 11 of 44
AD9763/AD9765/AD9767
Data Sheet
70
85
910kHz/10MSPS
80
2.27MHz/25MSPS
IOUTFS = 20mA
65
SINAD (dBc)
SFDR (dBc)
75
70
5.91MHz/65MSPS
IOUTFS = 10mA
60
65
11.37MHz/125MSPS
60
–16
–12
–8
AOUT (dBFS)
–4
0
55
20
00617-012
55
–20
80
100
120
140
Figure 15. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
85
0.25
5MHz/25MSPS
80
0.20
0.15
1MHz/5MSPS
0.10
2MHz/10MSPS
INL (LSB)
SFDR (dBc)
60
fCLK (MSPS)
Figure 12. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
75
40
00617-015
IOUTFS = 5mA
70
65
0
–0.05
–0.10
13MHz/65MSPS
–0.15
25MHz/125MSPS
60
0.05
–12
–8
AOUT (dBFS)
–4
0
–0.25
00617-013
–16
0
200
600
800
1000
800
1000
CODE
Figure 16. Typical INL
Figure 13. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
0.30
80
3.38MHz/3.36MHz @ 25MSPS
0.25
0.965MHz/1.035MHz @ 7MSPS
75
0.20
6.75MHz/7.25MHz @ 65MSPS
65
DNL (LSB)
70
16.9MHz/18.1MHz @ 125MSPS
0.15
0.10
0.05
0
60
55
–20
–0.10
–16
–12
–8
AOUT (dBFS)
–4
0
0
200
400
600
CODE
Figure 14. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
Figure 17. Typical DNL
Rev. G | Page 12 of 44
00617-017
–0.05
00617-014
SFDR (dBc)
400
00617-016
–0.20
55
–20
Data Sheet
AD9763/AD9765/AD9767
85
0
80
fOUT = 1MHz
75
fOUT = 10MHz
–10
–20
–30
SFDR (dBm)
fOUT = 25MHz
65
60
fOUT = 40MHz
–40
–50
–60
55
–70
50
–80
fOUT = 60MHz
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
100
–90
00617-018
45
–60
0
Figure 18. SFDR vs. Temperature @ fCLK = 125 MSPS, 0 dBFS
20
FREQUENCY (MHz)
30
40
Figure 21. Dual-Tone SFDR @ fCLK = 125 MSPS
0
1.0
0.05
10
00617-021
SFDR (dBc)
70
GAIN ERROR
–20
0.5
0
0
–0.03
–30
SFDR (dBm)
OFFSET ERROR
GAIN ERROR (%FS)
0.03
–40
–50
–60
–0.5
–70
–0.05
–40
0
20
40
TEMPERATURE (°C)
60
00617-019
–1.0
–20
80
10
0
–10
–20
–30
–40
–50
–60
–70
10
20
FREQUENCY (MHz)
30
40
00617-020
–80
0
0
10
20
FREQUENCY (MHz)
30
Figure 22. Four-Tone SFDR @ fCLK = 125 MSPS
Figure 19. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
–90
–90
Figure 20. Single-Tone SFDR @ fCLK = 125 MSPS
Rev. G | Page 13 of 44
40
00617-022
–80
SFDR (dBm)
OFFSET ERROR (%FS)
–10
AD9763/AD9765/AD9767
Data Sheet
AD9765
AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to
Nyquist, unless otherwise noted.
90
85
fCLK = 5MSPS
fCLK = 25MSPS
80
0dBFS
75
SFDR (dBc)
SFDR (dBc)
80
fCLK = 125MSPS
70
–6dBFS
70
–12dBFS
65
60
60
55
fOUT (MHz)
50
0
5
10
15
20
25
30
35
60
70
30
fOUT (MHz)
Figure 23. SFDR vs. fOUT @ 0 dBFS
00617-026
100
10
00617-027
1
00617-023
50
00617-028
fCLK = 65MSPS
Figure 26. SFDR vs. fOUT @ 65 MSPS
95
85
80
0dBFS
90
75
SFDR (dBc)
SFDR (dBc)
0dBFS
85
–12dBFS
–6dBFS
70
–6dBFS
65
–12dBFS
60
80
55
1.25
1.50
1.75
2.00
2.25
fOUT (MHz)
50
00617-024
75
1.00
0
10
20
30
40
50
fOUT (MHz)
Figure 24. SFDR vs. fOUT @ 5 MSPS
Figure 27. SFDR vs. fOUT @ 125 MSPS
90
85
IOUTFS = 10mA
80
85
0dBFS
IOUTFS = 20mA
75
75
SFDR (dBc)
–6dBFS
–12dBFS
IOUTFS = 5mA
70
65
70
60
65
60
55
0
2
4
6
8
fOUT (MHz)
10
12
00617-025
SFDR (dBc)
80
Figure 25. SFDR vs. fOUT @ 25 MSPS
50
0
5
10
15
20
25
fOUT (MHz)
Figure 28. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Rev. G | Page 14 of 44
Data Sheet
AD9763/AD9765/AD9767
90
75
0.91MHz/10MSPS
85
IOUTFS = 20mA
2.27MHz/25MSPS
70
IOUTFS = 10mA
SINAD (dBc)
SFDR (dBc)
80
75
65
70
60
11.37MHz/125MSPS
IOUTFS = 5mA
65
–10
–5
0
AOUT (dBFS)
55
20
00617-029
–15
60
80
100
120
140
fCLK (MSPS)
Figure 32. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
Figure 29. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
0.6
90
1MHz/5MSPS
85
5MHz/25MSPS
0.5
2MHz/10MSPS
0.4
80
0.3
INL (LSB)
75
70
13MHz/65MSPS
0.2
0.1
0
–0.1
65
–0.2
25MHz/125MSPS
60
–0.3
–15
–10
–5
0
AOUT (dBFS)
–0.4
00617-030
55
–20
0
1000
2000
3000
4000
CODE
00617-033
SFDR (dBc)
40
00617-032
5.91MHz/65MSPS
60
–20
Figure 33. Typical INL
Figure 30. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
0.05
80
[email protected]
0
[email protected]
75
DNL (LSB)
70
65
[email protected]
60
–0.10
–0.15
–0.20
–0.25
[email protected]
55
–20
–15
–10
–5
AOUT (dBFS)
0
Figure 31. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
–0.35
0
500
1000
1500
2000
2500
CODE
Figure 34. Typical DNL
Rev. G | Page 15 of 44
3000
3500
4000
00617-034
–0.30
00617-031
SFDR (dBc)
–0.05
AD9763/AD9765/AD9767
Data Sheet
85
0
fOUT = 1MHz
–10
80
fOUT = 10MHz
75
–20
–30
SFDR (dBm)
fOUT = 25MHz
65
fOUT = 40MHz
60
55
–40
–50
–60
–70
fOUT = 60MHz
50
–80
–40
–20
0
20
40
60
80
–90
00617-035
45
–60
100
TEMPERATURE (°C)
0
20
30
40
FREQUENCY (MHz)
Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS
0.05
10
00617-038
SFDR (dBc)
70
Figure 38. Dual-Tone SFDR @ fCLK = 125 MSPS
0
1.0
0.03
–20
0.5
0
–0.03
–30
SFDR (dBm)
0
GAIN ERROR (%FS)
GAIN ERROR
OFFSET ERROR
–40
–50
–60
–0.5
–70
–20
0
20
40
60
80
–1.0
00617-036
–0.05
–40
TEMPERATURE (°C)
Figure 36. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
0
–10
–20
–30
–40
–50
–60
–70
10
20
30
FREQUENCY (MHz)
40
00617-037
–80
0
0
10
20
30
FREQUENCY (MHz)
Figure 39. Four-Tone SFDR @ fCLK = 125 MSPS
10
–90
–90
Figure 37. Single-Tone SFDR @ fCLK = 125 MSPS
Rev. G | Page 16 of 44
40
00617-039
–80
SFDR (dBm)
OFFSET ERROR (%FS)
–10
Data Sheet
AD9763/AD9765/AD9767
AD9767
AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to
Nyquist, unless otherwise noted.
85
90
fCLK = 5MSPS
80
fCLK = 25MSPS
fCLK = 125MSPS
70
–6dBFS
70
–12dBFS
65
60
60
fOUT (MHz)
50
0
5
10
15
20
25
30
35
60
70
30
35
fOUT (MHz)
Figure 40. SFDR vs. fOUT @ 0 dBFS
00617-043
100
00617-044
10
00617-040
1
00617-045
55
fCLK = 65MSPS
50
0dBFS
75
SFDR (dBc)
SFDR (dBc)
80
Figure 43. SFDR vs. fOUT @ 65 MSPS
90
85
80
0dBFS
0dBFS
75
SFDR (dBc)
SFDR (dBc)
85
–6dBFS
–12dBFS
70
–6dBFS
–12dBFS
65
80
60
55
0
0.5
1.0
1.5
2.0
2.5
fOUT (MHz)
50
00617-041
75
0
10
20
30
40
50
fOUT (MHz)
Figure 41. SFDR vs. fOUT @ 5 MSPS
Figure 44. SFDR vs. fOUT @ 125 MSPS
90
90
0dBFS
85
85
IOUTFS = 5mA
80
–12dBFS
SFDR (dBc)
75
70
–6dBFS
60
IOUTFS = 10mA
75
70
65
60
IOUTFS = 20mA
65
55
0
2
4
6
8
fOUT (MHz)
10
12
00617-042
SFDR (dBc)
80
Figure 42. SFDR vs. fOUT @ 25 MSPS
50
0
5
10
15
20
25
fOUT (MHz)
Figure 45. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Rev. G | Page 17 of 44
AD9763/AD9765/AD9767
Data Sheet
75
90
910kHz/10MSPS
85
2.27MHz/25MSPS
70
IOUTFS = 20mA
SINAD (dBc)
SFDR (dBc)
80
75
IOUTFS = 10mA
65
IOUTFS = 5mA
70
60
11.37MHz/125MSPS
65
–10
–5
0
AOUT (dBFS)
55
20
00617-046
–15
60
80
100
120
140
fCLK (MSPS)
Figure 49. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
Figure 46. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
90
2.5
1MHz/5MSPS
85
2.0
2MHz/10MSPS
80
1.5
75
1.0
5MHz/25MSPS
INL (LSB)
SFDR (dBc)
40
00617-049
5.91MHz/65MSPS
60
–20
70
65
0.5
0
13MHz/65MSPS
60
–0.5
25MHz/125MSPS
55
–15
–10
–5
0
AOUT (dBFS)
–1.5
00617-047
50
–20
0
4000
8000
12000
16000
CODE
Figure 47. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
00617-050
–1.0
Figure 50. Typical INL
85
0.4
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80
0.2
[email protected]
0
75
DNL (LSB)
70
65
[email protected]
[email protected]
–0.6
–1.0
55
–1.2
–20
–15
–10
–5
AOUT (dBFS)
0
–1.4
0
200
400
600
CODE
Figure 51. Typical DNL
Figure 48. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
Rev. G | Page 18 of 44
800
1000
00617-051
50
–25
–0.4
–0.8
60
00617-048
SFDR (dBc)
–0.2
Data Sheet
AD9763/AD9765/AD9767
85
0
fOUT = 1MHz
–10
80
fOUT = 10MHz
75
–20
–30
SFDR (dBm)
fOUT = 25MHz
65
fOUT = 40MHz
60
–40
–50
–60
55
–70
fOUT = 60MHz
50
–80
–40
–20
0
20
40
60
80
–90
00617-052
45
–60
100
TEMPERATURE (°C)
0
20
30
40
FREQUENCY (MHz)
Figure 52. SFDR vs. Temperature @ 125 MSPS, 0 dBFS
0.05
10
00617-055
SFDR (dBc)
70
Figure 55. Dual-Tone SFDR @ fCLK = 125 MSPS
0
1.0
0.03
–20
0.5
0
–0.03
–30
SFDR (dBm)
0
GAIN ERROR (%FS)
GAIN ERROR
OFFSET ERROR
–40
–50
–60
–0.5
–70
–20
0
20
40
60
80
–1.0
00617-053
–0.05
–40
TEMPERATURE (°C)
Figure 53. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
0
–10
–20
–30
–40
–50
–60
–70
10
20
30
FREQUENCY (MHz)
40
00617-054
–80
0
0
10
20
30
FREQUENCY (MHz)
Figure 56. Four-Tone SFDR @ fCLK = 125 MSPS
10
–90
–90
Figure 54. Single-Tone SFDR @ fCLK = 125 MSPS
Rev. G | Page 19 of 44
40
00617-056
–80
SFDR (dBm)
OFFSET ERROR (%FS)
–10
AD9763/AD9765/AD9767
Data Sheet
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in part per million (ppm)
of full-scale range (FSR) per degree Celsius. For reference drift,
the drift is reported in ppm per degree Celsius (ppm/°C).
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTA, 0 mA output is expected when the inputs are all 0s.
For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
Gain Error
Gain error is the difference between the actual and ideal output
spans. The actual span is determined by the output when all inputs
are set to 1s minus the output when all inputs are set to 0s.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolts per second (pV-s).
Output Compliance Range
The output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear performance.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage or in decibels (dB).
Rev. G | Page 20 of 44
Data Sheet
AD9763/AD9765/AD9767
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
RSET1
2kΩ
REFIO
PMOS
CURRENT
SOURCE
ARRAY
FSADJ2
PMOS
CURRENT
SOURCE
ARRAY
0.1µF
RSET 2
2kΩ
GAINCTRL
DVDD1/DVDD2
DCOM1/DCOM2
RETIMED CLOCK OUTPUT*
WRT1/
IQWRT
IOUTA1
SEGMENTED
LSB
IOUTB1
SWITCHES FOR SWITCH
DAC1
DAC1
LATCH
AD9763/
AD9765/
AD9767
1.2V REF
Mini-Circuits
T1-1T
CLK
DIVIDER
IOUTA2
SEGMENTED
LSB
SWITCHES FOR
SWITCH IOUTB2
DAC2
DAC2
LATCH
50Ω
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
50Ω
MODE
MULTIPLEXING LOGIC
CHANNEL 1 LATCH
CHANNEL 2 LATCH
PORT 1
PORT 2
50Ω
DVDD1/
DVDD2
5V
DCOM1/
DCOM2 ACOM
WRT2/
IQSEL
DIGITAL
DATA
LECROY 9210
PULSE
GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
TEKTRONIX
AWG2021
w/OPTION 4
00617-057
FSADJ1
SLEEP
Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,
Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
5V
CLK2/IQRESET
RSET 1
2kΩ
IREF 1
0.1µF
RSET 2
2kΩ
FSADJ1
REFIO
PMOS
CURRENT
SOURCE
ARRAY
FSADJ2
PMOS
CURRENT
SOURCE
ARRAY
IREF 2
1.2V REF
SLEEP
ACOM
CLK
DIVIDER
DAC2
LATCH
WRT1/
IQWRT
IOUTA2
SEGMENTED
LSB
SWITCHES FOR
I
SWITCH OUTB2
DAC2
VOUT1B
VOUT2A
VOUT2B
RL2B
50Ω
MODE
MULTIPLEXING LOGIC
CHANNEL 1 LATCH
GAINCTRL
VOUT1A
IOUTA1
SEGMENTED
LSB
SWITCHES FOR
I
SWITCH OUTB1
DAC1
DAC1
LATCH
AD9763/
AD9765/
AD9767
VDIFF = VOUTA – VOUTB
CHANNEL 2 LATCH
PORT 1
PORT 2
DIGITAL DATA INPUTS
DVDD1/
DCOM1/ DVDD2
DCOM2
WRT2/
IQSEL
RL1B
50Ω
RL1A
50Ω
RL2A
50Ω
5V
00617-058
CLK1/IQCLK
AVDD
NOTES
1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE RSET = 2kΩ.
Figure 58. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 58 shows a simplified block diagram of the AD9763/
AD9765/AD9767. The AD9763/AD9765/AD9767 consist of
two DACs, each one with its own independent digital control
logic and full-scale output current control. Each DAC contains
a PMOS current source array capable of providing up to 20 mA
of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
Rev. G | Page 21 of 44
AD9763/AD9765/AD9767
Data Sheet
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from
2 mA to 20 mA via an external network connected to the full
scale adjust (FSADJ) pin. The external network, in combination
with both the reference control amplifier and voltage reference
(VREFIO) sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current (IOUTFS) is 32 × IREF.
REFERENCE OPERATION
The AD9763/AD9765/AD9767 contain an internal 1.20 V band
gap reference. This can easily be overridden by a low noise external
reference with no effect on performance. REFIO serves as either
an input or output, depending on whether the internal or an
external reference is used. To use the internal reference, simply
decouple the REFIO pin to ACOM with a 0.1 μF capacitor. The
internal reference voltage is present at REFIO. If the voltage at
REFIO is used elsewhere in the circuit, an external buffer amplifier
with an input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure 59.
GAINCTRL
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
REFIO
ADDITIONAL
EXTERNAL
LOAD
RSET
FSADJ1/
FSADJ2
ACOM
22nF
An external reference can be applied to REFIO as shown in
Figure 60. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. The 0.1 μF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
GAINCTRL
REFIO
EXTERNAL
REFERENCE
256Ω
IREF
22nF
FSADJ1/
FSADJ2
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and
625 μA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of the
AD9763/AD9765/AD9767, which is proportional to IOUTFS (refer to
the Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.
To ensure that the AD9763/AD9765/AD9767 performs properly,
connect a 22 nF capacitor and 256 Ω resistor network (shown in
Figure 59 and Figure 60) from the FSADJ1 terminal to ground
and from the FSADJ2 terminal to ground.
AVDD
AD9763/
AD9765/
AD9767
REFERENCE
SECTION
CURRENT
SOURCE
ARRAY
ACOM
RSET
00617-060
1.2V
REF
IREF = VREFIO/RSET
IOUTFS = 32 × IREF
CURRENT
SOURCE
ARRAY
Figure 59. Internal Reference Configuration
AVDD
Both of the DACs in the AD9763/AD9765/AD9767 contain a
control amplifier that is used to regulate the full-scale output
current (IOUTFS). The control amplifier is configured as a V-I
converter, as shown in Figure 59, so that its current output (IREF)
is determined by the ratio of the VREFIO and an external resistor,
RSET.
The DAC full-scale current, IOUTFS, is an output current 32 times
larger than the reference current, IREF.
00617-059
IREF
SETTING THE FULL-SCALE CURRENT
REFERENCE
SECTION
0.1µF
256Ω
The AD9763/AD9765/AD9767 has two gain control modes,
independent and master/slave. If the GAINCTRL terminal is low
(connected to ground), the full-scale currents of DAC1 and DAC2
are set separately using two different RSET resistors. One resistor
is connected to the FSADJ1 terminal, and the other resistor is
connected to the FSADJ2 terminal. This is independent mode.
If the GAINCTRL terminal is set high (connected to AVDD),
the full-scale currents of DAC1 and DAC2 are set to the same value
using one RSET resistor. In master/slave mode, full-scale current
for both DAC1 and DAC2 is set via the FSADJ1 terminal.
AVDD
AD9763/
AD9765/
AD9767
1.2V
REF
GAIN CONTROL MODE
Figure 60. External Reference Configuration Gain Control Mode
Rev. G | Page 22 of 44
Data Sheet
AD9763/AD9765/AD9767
DAC TRANSFER FUNCTION
Both DACs in the AD9763/AD9765/AD9767 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near
full-scale current output (IOUTFS) when all bits are high (that is,
DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/
AD9767, respectively), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA and
IOUTB is a function of both the input code and IOUTFS. IOUTA for the
AD9763, AD9765, and AD9767, respectively, can be expressed as
IOUTA = (DAC CODE/1024) × IOUTFS
(1)
IOUTA = (DAC CODE/4096) × IOUTFS
IOUTA = (DAC CODE/16,384) × IOUTFS
IOUTB for the AD9763, AD9765, and AD9767, respectively, can be
expressed as
IOUTB = ((1023 − DAC CODE)/1024) × IOUTFS
(2)
IOUTB = ((4095 − DAC CODE)/4096) × IOUTFS
IOUTB = ((16,383 − DAC CODE)/16,384) × IOUTFS
where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal
representation).
IOUTFS is a function of the reference current (IREF). This is nominally
set by a reference voltage (VREFIO) and an external resistor (RSET).
It can be expressed as
IOUTFS = 32 × IREF
(3)
where IREF is set as discussed in the Setting the Full-Scale
Current section.
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be directly connected to matching resistive loads (RLOAD)
that are tied to the analog common (ACOM). Note that RLOAD
can represent the equivalent load resistance seen by IOUTA or IOUTB,
as is the case in a doubly terminated 50 Ω or 75 Ω cable. The singleended voltage output appearing at the IOUTA and IOUTB nodes is
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note that the full-scale value of VOUTA and VOUTB must not
exceed the specified output compliance range to maintain the
specified distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
Equation 7 highlights some of the advantages of operating the
AD9763/AD9765/AD9767 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (that is, VOUTA or VOUTB), thus providing twice the signal
power to the load.
The gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the
AD9763/AD9765/AD9767 can be enhanced by selecting
temperature tracking resistors for RLOAD and RSET due to their
ratiometric relationship.
ANALOG OUTPUTS
The complementary current outputs, IOUTA and IOUTB, in each
DAC can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor (RLOAD) as described in Equation 5 through Equation 7.
The differential voltage (VDIFF) existing between VOUTA and VOUTB
can be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9763/AD9765/AD9767 is optimum and specified using a
differential transformer-coupled output in which the voltage
swing at IOUTA and IOUTB is limited to ±0.5 V. If a single-ended
unipolar output is desired, select IOUTA.
The distortion and noise performance of the AD9763/AD9765/
AD9767 can be enhanced when it is configured for differential
operation. The common-mode error sources of both IOUTA and
IOUTB can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform
increases. This is due to the first-order cancellation of various
dynamic common-mode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed
signal power to the load, assuming no source termination. Because
the output currents of IOUTA and IOUTB are complementary, they
become additive when processed differentially. A properly selected
transformer allows the AD9763/AD9765/AD9767 to provide the
required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated
with the current sources and is typically 100 kΩ in parallel with
5 pF. It is also slightly dependent on the output voltage (that is,
VOUTA and VOUTB) due to the nature of a PMOS device. As a result,
maintaining IOUTA and/or IOUTB at a virtual ground via an I-V
op amp configuration results in the optimum dc linearity. Note that
the INL/DNL specifications for the AD9763/AD9765/AD9767 are
measured with IOUTA maintained at a virtual ground via an op amp.
Rev. G | Page 23 of 44
AD9763/AD9765/AD9767
Data Sheet
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9763/
AD9765/AD9767 output (that is, VOUTA and/or VOUTB) to extend its
output compliance range must size RLOAD accordingly. Operation
beyond this compliance range adversely affects the linearity
performance of the AD9763/AD9765/AD9767 and
subsequently degrades its distortion performance.
DIGITAL INPUTS
The digital inputs of the AD9763/AD9765/AD9767 consist of
two independent channels. For the dual-port mode, each DAC has
its own dedicated 10-/12-/14-bit data port: WRT line and CLK line.
In the interleaved timing mode, the function of the digital control
pins changes as described in the Interleaved Mode Timing
section. The 10-/12-/14-bit parallel data inputs follow straight
binary coding, where the most significant bits (MSBs) are DB9P1
and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765,
and DB13P1 and DB13P2 for the AD9767, and the least significant
bits (LSBs) are DB0P1 and DB0P2 for all three parts. IOUTA produces
a full-scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
PORT 1
INPUT
LATCH
INTERLEAVED
DATA IN, PORT 1
DAC1
LATCH
DAC1
DEINTERLEAVED
DATA OUT
PORT 2
INPUT
LATCH
IQCLK
IQRESET
DAC2
LATCH
00617-061
IQWRT
IQSEL
DAC2
÷2
Figure 61. Latch Structure in Interleaved Mode
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767
operates in dual-port mode (refer to Figure 57). The AD9763/
AD9765/AD9767 functions as two distinct DACs. Each DAC
has its own completely independent digital input and control lines.
The AD9763/AD9765/AD9767 features a double-buffered data
path. Data enters the device through the channel input latches.
This data is then transferred to the DAC latch in each signal
path. After the data is loaded into the DAC latch, the analog
output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK must occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns must be
maintained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 62
and Figure 63.
tS
tH
DATA IN
WRT1/WRT2
tLPW
CLK1/CLK2
tCPW
IOUTA
OR
IOUTB
00617-062
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the
AD9763/AD9765/AD9767.
tPD
Figure 62. Dual-Port Mode Timing
DATA IN
D1
D2
D3
D4
D5
WRT1/WRT2
CLK1/CLK2
The AD9763/AD9765/AD9767 can operate in two timing modes,
dual and interleaved, which are described in the following
sections. The block diagram in Figure 61 represents the latch
architecture in the interleaved timing mode.
Rev. G | Page 24 of 44
IOUTA
OR
IOUTB
XX
D1
D2
Figure 63. Dual-Port Mode Timing
D3
D4
00617-063
DAC TIMING
Data Sheet
AD9763/AD9765/AD9767
tS
Interleaved Mode Timing
DATA IN
IQSEL
Data enters the device on the rising edge of IQWRT. The logic level
of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or
to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL
must change state only when IQWRT and IQCLK are low.
tLPW
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
IQCLK
tPD
IOUTA
OR
IOUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
Figure 65. 5 V Only Interleaved Mode Timing
Similar to the order of CLK and WRT in dual-port mode,
IQCLK must occur before or simultaneously with IQWRT.
INTERLEAVED
DATA
Timing specifications for interleaved mode are shown in Figure 64
and Figure 66.
xx
D1
D2
D3
D4
D5
IQSEL
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDDx), or
IQWRT
IQCLK
VTHRESHOLD = DVDDx/2(±20%)
IQRESET
tH
DAC OUTPUT
PORT 1
DATA IN
xx
xx
DAC OUTPUT
PORT 2
500 ps
D3
D1
D4
D2
00617-066
tS
tH*
IQWRT
00617-065
When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767
operate in interleaved mode (refer to Figure 61). In addition,
WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
tH
Figure 66. Interleaved Mode Timing
IQSEL
IQWRT
tH*
tLPW
IQCLK
500 ps
tPD
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
00617-064
IOUTA
OR
IOUTB
The internal digital circuitry of the AD9763/AD9765/AD9767
is capable of operating at a digital supply of 3.3 V or 5 V. As a
result, the digital inputs can also accommodate TTL levels when
DVDD1/DVDD2 is set to accommodate the maximum high
level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD2
of 3.3 V typically ensures proper compatibility with bipolar TTL
logic families. Figure 67 shows the equivalent digital input
circuit for the data and clock inputs. The sleep mode input is
similar, with the exception that it contains an active pull-down
circuit, thus ensuring that the AD9763/AD9765/AD9767
remains enabled if this input is left disconnected.
DVDD1
Figure 64. 5 V or 3.3 V Interleaved Mode Timing
DIGITAL
INPUT
00617-067
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 65, but at 3.3 V the interleaved data transfer is
not reliable.
Figure 67. Equivalent Digital Input
Rev. G | Page 25 of 44
AD9763/AD9765/AD9767
Data Sheet
80
Because the AD9763/AD9765/AD9767 is capable of being clocked
up to 125 MSPS, the quality of the clock and data input signals
are important in achieving the optimum performance. Operating
the AD9763/AD9765/AD9767 with reduced logic swings and a
corresponding digital supply (DVDD1/DVDD2) results in the
lowest data feedthrough and on-chip digital noise. The drivers of
the digital data interface circuitry should be specified to meet the
minimum setup and hold times of the AD9763/AD9765/AD9767
as well as its required minimum and maximum input logic level
thresholds.
The external clock driver circuitry provides the AD9763/AD9765/
AD9767 with a low-jitter clock input meeting the minimum
and maximum logic levels while providing fast edges. Fast clock
edges help minimize jitter manifesting itself as phase noise on a
reconstructed waveform. Therefore, the clock input should be
driven by the fastest logic family suitable for the application.
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This
typically results in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. In addition, at higher sampling rates, the 20%
tolerance of the digital logic threshold should be considered,
because it affects the effective clock duty cycle and,
subsequently, cuts into the required data setup and hold times.
Input Clock and Data Timing Relationship
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9763/AD9765/AD9767 are rising
edge triggered and therefore exhibit SNR sensitivity when the
data transition is close to this edge. The goal when applying the
AD9763/AD9765/AD9767 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 68 shows the relationship of SNR
to clock placement with different sample rates. Note that at the
lower sample rates, much more tolerance is allowed in clock
placement; much more care must be taken at higher rates.
AD9763
AD9765
AD9767
SNR (dBc)
60
50
40
30
20
10
0
–4
–3
–2
–1
0
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
3
4
00617-068
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion
of a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9763/AD9765/AD9767 digital inputs and driver outputs
can be helpful in reducing any overshooting and ringing at the
digital inputs that contribute to digital feedthrough. For longer
board traces and high data update rates, stripline techniques
with proper impedance and termination resistors should be
considered to maintain “clean” digital inputs.
70
Figure 68. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
SLEEP MODE OPERATION
The AD9763/AD9765/AD9767 has a power-down function that
turns off the output current and reduces the supply current to less
than 8.5 mA over the specified supply range of 3.3 V to 5 V and
over the full operating temperature range. This mode can be
activated by applying a Logic Level 1 to the SLEEP pin. The
SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital
input also contains an active pull-down circuit that ensures the
AD9763/AD9765/AD9767 remains enabled if this input is left
disconnected. The AD9763/AD9765/AD9767 require less than
50 ns to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation (PD) of the AD9763/AD9765/AD9767 is
dependent on several factors, including
•
•
•
•
the power supply voltages (AVDD and DVDD1/DVDD2)
the full-scale current output (IOUTFS)
the update rate (fCLK)
the reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current (IAVDD) and the digital supply current (IDVDD).
IAVDD is directly proportional to IOUTFS, as shown in Figure 69,
and is insensitive to fCLK.
Conversely, IDVDD is dependent on the digital input waveform,
the fCLK, and the digital supply (DVDD1/DVDD2). Figure 70
and Figure 71 show IDVDD as a function of full-scale sine wave
output ratios (fOUT/fCLK) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note
that IDVDD is reduced by more than a factor of 2 when
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
Rev. G | Page 26 of 44
Data Sheet
AD9763/AD9765/AD9767
18
80
125MSPS
16
70
14
100MSPS
90
IDVDD (mA)
IAVDD (mA)
12
50
40
10
65MSPS
8
6
30
25MSPS
4
0
5
10
15
20
25
IOUTFS
00617-069
10
Figure 69. IAVDD vs. IOUTFS
30
125MSPS
25
65MSPS
15
25MSPS
5
5MSPS
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
0.5
00617-070
IDVDD (mA)
100MSPS
20
10
0
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
Figure 71. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V
35
0
5MSPS
2
Figure 70. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 5 V
Rev. G | Page 27 of 44
0.5
00617-071
20
AD9763/AD9765/AD9767
Data Sheet
APPLYING THE AD9763/AD9765/AD9767
The following sections illustrate some typical output configurations
for the AD9763/AD9765/AD9767, with IOUTFS set to a nominal
20 mA, unless otherwise noted. For applications requiring the
optimum dynamic performance, a differential output configuration
is suggested. A differential output configuration can consist of
either an RF transformer or a differential op amp configuration.
The transformer configuration provides the optimum high
frequency performance and is recommended for any application
allowing for ac coupling. The differential op amp configuration
is suitable for applications requiring dc coupling, bipolar
output, signal gain, and/or level shifting within the bandwidth
of the chosen op amp.
A single-ended output is suitable for applications requiring
a unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor (RLOAD) referred to as ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc-coupled, ground-referred output voltage. Alternatively, an
amplifier can be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity because IOUTA or IOUTB is
maintained at a virtual ground. Note that IOUTA provides slightly
better performance than IOUTB.
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around ACOM and must be maintained with the output compliance range of the AD9763/AD9765/AD9767 to achieve the
specified performance. A differential resistor (RDIFF) can be
inserted in applications where the output of the transformer is
connected to the load (RLOAD) via a passive reconstruction filter
or cable. RDIFF is determined by the transformer’s impedance
ratio and provides the proper source termination that results in a
low VSWR. Approximately half the signal power will be dissipated
across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used as shown in Figure 73 to perform a
differential-to-single-ended conversion. The AD9763/AD9765/
AD9767 is configured with two equal load resistors (RLOAD) of
25 Ω each. The differential voltage developed across IOUTA and
IOUTB is converted to a single-ended signal via the differential
op amp configuration. An optional capacitor can be installed
across IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor often enhances the op amp’s
distortion performance by preventing the DAC’s high-slewing
output from overloading the op amp’s input.
500Ω
IOUTA
Mini-Circuits
T1-1T
AD9763/
AD9765/
AD9767
225Ω
IOUTB
An RF transformer can be used as shown in Figure 72 to
perform a differential-to-single-ended signal conversion. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the pass band of the transformer. An RF transformer
such as the Mini-Circuits® T1-1T provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
RLOAD
IOUTB
OPTIONAL
RDIFF
00617-072
IOUTA
225Ω
AD9763/
AD9765/
AD9767
DIFFERENTIAL COUPLING USING A
TRANSFORMER
Figure 72. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
AD8047
COPT
500Ω
25Ω
25Ω
00617-073
OUTPUT CONFIGURATIONS
Figure 73. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
from a dual supply because its output is approximately ±1.0 V.
Select a high speed amplifier capable of preserving the
differential performance of the AD9763/AD9765/AD9767
while meeting other system level objectives (that is, cost or
power). Consider the op amp’s differential gain, gain setting
resistor values, and full-scale output swing capabilities when
optimizing this circuit.
The differential circuit shown in Figure 74 provides the
necessary level shifting required in a single-supply system.
In this case, AVDD, which is the positive analog supply for both
the AD9763/AD9765/AD9767 and the op amp, is used to level
shift the differential output of the AD9763/AD9765/AD9767 to
midsupply (that is, AVDD/2). The AD8055 is a suitable op amp
for this application.
Rev. G | Page 28 of 44
Data Sheet
AD9763/AD9765/AD9767
COPT
500Ω
IOUTA
225Ω
COPT
25Ω
1kΩ
25Ω
IOUTFS = 10mA
IOUTA
AVDD
500Ω
AD9763/
AD9765/
AD9767
U1
VOUT = IOUTFS × RFB
200Ω
IOUTB
00617-076
225Ω
IOUTB
RFB
200Ω
AD8055
00617-074
AD9763/
AD9765/
AD9767
Figure 74. Single-Supply DC Differential-Coupled Circuit
Figure 76. Unipolar Buffered Voltage Output
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
VOUTA = 0V TO 0.5V
AD9763/
AD9765/
AD9767
50Ω
50Ω
25Ω
00617-075
IOUTB
Figure 75. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 76 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9763/AD9765/AD9767 output current. U1 maintains IOUTA
(or IOUTB) at a virtual ground, thus minimizing the nonlinear
output impedance effect on the INL performance of the DAC,
as described in the Analog Outputs section. Although this singleended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC update
rates may be limited by the slewing capabilities of U1. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of RFB and IOUTFS. Set the
full-scale output within U1’s voltage output swing capabilities
by scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result with a reduced IOUTFS because the signal
current U1 has to sink will be subsequently reduced.
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 92 to Figure 93 illustrate recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9763/AD9765/AD9767
evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum of tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9763/AD9765/AD9767 AVDD supply over this frequency
range is shown in Figure 77.
90
85
80
75
70
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (MHz)
Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency
Rev. G | Page 29 of 44
00617-077
IOUTFS = 20mA
IOUTA
POWER AND GROUNDING CONSIDERATIONS
PSRR (dB)
Figure 75 shows the AD9763/AD9765/AD9767 configured to
provide a unipolar output range of approximately 0 V to 0.5 V
for a doubly terminated 50 Ω cable, because the nominal fullscale current (IOUTFS) of 20 mA flows through the equivalent
RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load
resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected directly to ACOM or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long as the
positive compliance range is adhered to. One additional
consideration in this mode is the INL (see the Analog Outputs
section). For optimum INL performance, the single-ended,
buffered voltage output configuration is suggested.
AD9763/AD9765/AD9767
Data Sheet
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
current, IOUTFS, one must determine the PSRR in decibels using
Figure 77 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 77 by the scaling factor 20 × log(RLOAD).
For example, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB (that
is, the PSRR of the DAC at 250 kHz, which is 85 dB in Figure 77,
becomes 51 dB VOUT/VIN).
Proper grounding and decoupling are primary objectives in any
high speed, high resolution system. The AD9763/AD9765/AD9767
features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, decouple the analog supply (AVDD) to
the analog common (ACOM) as close to the chip as physically
possible. Similarly, decouple the digital supply (DVDD1/DVDD2)
to the digital common (DCOM1/DCOM2) as close to the chip
as possible.
For those applications that require a single 5 V or 3.3 V supply
for both the analog and digital supplies, a clean analog supply
can be generated using the circuit shown in Figure 78. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained by using
low-ESR type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
Rev. G | Page 30 of 44
ELECTROLYTIC
100µF
CERAMIC
10µF
TO
22µF
AVDD
0.1µF
ACOM
TANTALUM
5V
POWER SUPPLY
Figure 78. Differential LC Filter for Single 5 V and 3.3 V Applications
00617-078
Note that the data in Figure 77 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 77 represents a worstcase condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
Data Sheet
AD9763/AD9765/AD9767
APPLICATIONS INFORMATION
–20
VDSL EXAMPLE APPLICATIONS USING THE
AD9765 AND AD9767
–30
–50
(dBm)
–60
–70
–80
–90
–100
–120
0.665
0.685
0.705
0.725
0.745
0.765
0.785
0.805
0.825
FREQUENCY (MHz)
00617-080
–110
Figure 80. AD9767 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
4.85
4.90
4.95
5.00
5.05
5.10
5.15
FREQUENCY (MHz)
–20
00617-081
As with other multitone applications, each VDSL tone is
capable of transmitting a given number of bits, depending on
the signal-to-noise ratio (SNR) in a narrow band around that
tone. For a typical VDSL application, the tones are evenly
spaced over the range of several kHz to 10 MHz. At the high
frequency end of this range, performance is generally limited by
cable characteristics and environmental factors such as external
interferers. Performance at the lower frequencies is much more
dependent on the performance of the components in the signal
chain. In addition to in-band noise, intermodulation from other
tones can also potentially interfere with the data recovery for
a given tone. The two graphs in Figure 79 and Figure 81
represent a 500-tone missing bin test vector, with frequencies
evenly spaced from 400 Hz to 10 MHz. This test is very
commonly done to determine if distortion limits the number of
bits that can be transmitted in a tone. The test vector has a
series of missing tones around 750 kHz, which is represented in
Figure 79, and a series of missing tones around 5 MHz, which is
represented in Figure 81. In both cases, the spurious-free
dynamic range (SFDR) between the transmitted tones and the
empty bins is greater than 60 dB.
–40
(dBm)
Very high frequency digital subscriber line (VDSL) technology is
growing rapidly in applications requiring data transfer over
relatively short distances. By using quadrature amplitude
modulation (QAM) and transmitting the data in discrete multiple
tones (DMT), high data rates can be achieved.
Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–30
–40
–20
–50
(dBm)
–60
–40
–70
–80
(dBm)
–60
–90
–100
–80
0.685
0.705
0.725
0.745
0.765
FREQUENCY (MHz)
0.785
0.805
0.825
Figure 79. AD9765 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–100
–120
4.85
4.90
4.95
5.00
5.05
5.10
5.15
FREQUENCY (MHz)
Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
Rev. G | Page 31 of 44
00617-082
–120
0.665
00617-079
–110
AD9763/AD9765/AD9767
Data Sheet
between the two baseband channels. A quadrature mixer
modulates the I and Q components with the in-phase and
quadrature carrier frequency and then sums the two outputs
to provide the QAM signal.
QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of
identical frequency but with a 90° phase difference. This results
in an in-phase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier frequency.
10
DAC
DSP
OR
ASIC
0°
CARRIER
FREQUENCY
10
TO
MIXER
Σ
90°
DAC
NYQUIST
FILTERS
00617-083
QUADRATURE AMPLITUDE MODULATION (QAM)
EXAMPLE USING THE AD9763
QUADRATURE
MODULATOR
Figure 83. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 84 helps improve the
matching between the I and Q channels, and it shows a path for
upconversion using the AD8346 quadrature modulator. The
AD9763 provides both I and Q DACs a common reference that
improves the gain matching and stability. RCAL can be used to
compensate for any mismatch in gain between the two channels.
The mismatch can be attributed to the mismatch between RSET1
and RSET2, the effective load resistance of each channel, and/or
the voltage offset of the control amplifier in each DAC. The
differential voltage outputs of both DACs in the AD9763 are
fed into the respective differential inputs of the AD8346 via
matching networks.
A common and traditional implementation of a QAM modulator
is shown in Figure 83. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components. Each component is then typically
applied to a Nyquist filter before being applied to a quadrature
mixer. The matching Nyquist filters shape and limit each
component’s spectral envelope while minimizing intersymbol
interference. The DAC is typically updated at the QAM symbol
rate, or at a multiple of the QAM symbol rate if an interpolating
filter precedes the DAC. The use of an interpolating filter typically
eases the implementation and complexity of the analog filter, which
can be a significant contributor to mismatches in gain and phase
AVDD
ROHDE & SCHWARZ
FSEA30B
OR EQUIVALENT
SPECTRUM ANALYZER
0.1µF
PORT Q
CLK1/IQCLK
ACOM AVDD
RL
LA
IOUTA
I DAC
LATCH
I
DAC
AD9763/
AD9765/
AD9767
Q DAC
LATCH
RL
CB
CA
RL LA
IOUTA
RL LA RL
IOUTB
WRT2/IQSEL
RL
LA
BBIP
VOUT
RB
RA
256Ω
22nF
MODE
FSADJ1
2kΩ
20kΩ
FSADJ2
256Ω
22nF
NOTES
1. DAC FULL-SCALE OUTPUT CURRENT = IOUTFS.
2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.
2kΩ
20kΩ
+
RB
LOIP
RA
BBQP
RB
PHASE
SPLITTER
LOIN
CFILTER
BBQN
RL
VDIFF = 1.82V p-p
SLEEP
VPBF
RL
CB
CA
RA
BBIN
IOUTB
Q
DAC
RA
RB
AD8346
REFIO
DIFFERENTIAL
RLC FILTER
0.1µF RL = 200Ω
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
IOUTFS = 11mA
AVDD = 5.0V
VCM = 1.2V
ROHDE & SCHWARZ
SIGNAL GENERATOR
AVDD
AD976x
RB
0 TO IOUTFS
Figure 84. Baseband QAM Implementation Using an AD9763 and an AD8346
Rev. G | Page 32 of 44
RL
VDAC
RA
AD8346
VMOD
00617-084
WRT1/IQWRT
DIGITAL INTERFACE
TEKTRONIX
AWG2021
WITH
OPTION 4
PORT I
DCOM1/ DVDD1/
DCOM2 DVDD2
Data Sheet
AD9763/AD9765/AD9767
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference with
other signals being transmitted by air. Regulatory bodies define a
spectral mask outside of the transmit band, and the ACP must fall
under this mask. If distortion in the transmit path causes the
ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
Figure 85 shows the results of using the AD9763/AD9765/
AD9767 with the AD8346 to reconstruct a wideband CDMA
signal centered at 2.4 GHz. The baseband signal is sampled at
65 MSPS and has a chip rate of 8 MHz.
CDMA
–30
Code division multiple access (CDMA) is an air transmit/receive
scheme in which the signal in the transmit path is modulated
with a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum. Similar to a discrete multitone
(DMT) waveform, a CDMA waveform containing multiple
subscribers can be characterized as having a high peak to average
ratio (that is, crest factor), thus demanding highly linear
components in the transmit signal path. The bandwidth of the
spectrum is defined by the CDMA standard being used, and in
operation it is implemented by using a spreading code with
particular characteristics.
–40
–50
–60
==
(dB)
–70
–80
–90
–100
–110
c11
c11
cu1
–120
cu1
C0
C0
–130
CENTER 2.4GHz
3MHz
FREQUENCY
SPAN 30MHz
00617-085
I and Q digital data can be fed into the AD9763 in two ways. In
dual-port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9763. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9763 can be synchronized to
the I and Q data streams. The internal timing of the AD9763 routes
the selected I and Q data to the correct DAC output. In interleaved
mode, if no interpolation filter precedes the AD9763, the symbol
rate is half that of the system clock driving the digital data stream
and the IQWRT and IQCLK pins on the AD9763.
Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at
2.4 GHz, Adjacent Channel Power >60 dBm
Rev. G | Page 33 of 44
AD9763/AD9765/AD9767
Data Sheet
EVALUATION BOARD
This board allows the user the flexibility to operate the AD9763/
AD9765/AD9767 in various configurations. Possible output
configurations include transformer coupled, resistor terminated,
and single-ended and differential outputs. The digital inputs can be
used in dual-port or interleaved mode and are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. When
operating the AD9763/AD9765/AD9767, best performance is
obtained by running the digital supply (DVDD1/DVDD2) at
3.3 V and the analog supply (AVDD) at 5 V.
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767-EBZ is an evaluation board
for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC.
Careful attention to layout and circuit design, combined with a
prototyping area, allow the user to easily and effectively evaluate
the AD9763/AD9765/AD9767 in any application where a high
resolution, high speed conversion is required.
SCHEMATICS
RED
RED
L2
L1
TB1 1
AVDDIN
DVDD
BEAD
TB1 3
DCASE
AVDD
BEAD
C9
VAL
VOLT
C10
VAL
VOLT
DCASE
BLK
BLK
BLK
BLK
TB1 2
BLK
BLK
TB1 4
BLK
BLK
DGND
1
R1
3
R2
4
R3
5
R4
6
R5
INP36
7
R6
8
R7
INCK2
9
R8
10
R9
INP32
INP33
INP34
INP35
1
RCO M
2 22
INP31
RP15
INP23
INP24
INP25
INP26
INP27
INP28
INP29
INP30
AGND
1
RCO M
2 22
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
INP9
INP10
INP11
INP12
INP13
INP14
INCK1
RP10
1
RCO M
2 22
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP9
INP1
INP2
INP3
INP4
INP5
INP6
INP7
INP8
RCO M
2 22
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP16
Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1)
Rev. G | Page 34 of 44
00617-086
DVDDIN
Rev. G | Page 35 of 44
SLEEP
DGND;3,4,5
SMA200UP
DGND;3,4,5
SMA200UP
DGND;3,4,5
SMA200UP
DGND;3,4,5
WHT
WHT
WHT
WHT
R6 3
1K
50
3
4
JP14
RC0603
2
5
T3
1
6
T1-1TCUP
RC0603
R1
50
C18
C19
R1 8
.1
1K
R13
50
R2
50
.1
RC0603
R3
50
2
1
-IN
SO16
OUT
15
JP3
JP4
JP17
DS90LV048B
R4
50
U2
+IN
DCLKIN1
JP5
JP16
JP9
4
3
6
5
8
7
9
11
14
SO16
U2
GND
VCC
.1UF
C33
DS90LV048B
EN
EN
DVDD
DS90LV048B
SO16
OUT
DS90LV048B
SO16
OUT
R30
VAL
16
-IN
U2
+IN
-IN
10
SO16
OUT
DS90LV048B
U2
U2
+IN
-IN
+IN
CC0805
DVDD
DCLKIN2
12
13
DVDD
.01UF
C34
CC0805
4
CLK
J
U6
PRE
DVDD
WRT1
SLEEP
WRT2
CLK2
CLK1
Q
5
DVDD
SW2
K
6
Q_
CLR
15
SN74F112
DGND;8
DVDD;16
2
1
3
SW1
/2 CLOCK DIVIDER
DVDD
JP1
JP2
1
WRT2IN S4
IQSEL
CLK2IN S3
RESET
CLK1IN S2
1QCLK
WRT1IN S1
IQWRT
SMA200UP
WHT
JP13
R17
RC0805
DVDD
1K
RC0603
R19
CC0805
1K
B
RC0603
2 C
R16
A
3
DVDD
CC0805
C
2
RC0805
A
RC0805
3
RC0603
1
B
RC0805
CC0805
DVDD
13
11
C8
10
CLK
J
U6
PRE
.01UF
CC0805
Q
7
9
DGND;8
DVDD;16
12
K
Q_
CLR
SN74F112 14
.1UF
C7
Data Sheet
AD9763/AD9765/AD9767
Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2)
00617-091
RC0805
AD9763/AD9765/AD9767
R23
DNP
O2N
51
DNP
C24
DNP
CC0805
CC0805
L5
O2P
C31
RC0603
LC0805
DNP
DNP
CC0603
L6
Data Sheet
JP19
C23
R21
51
R22
DNP
RC0603
LC0805
RC0603
MODULATED OUTPUT
J1
10
9
G2
AVDD2
RC0603
AD834 9
2
TP6
RED
R28
1K
ENBL
VPS1
7
AVDD2
AGND2
TP5
BLK
8
11
12
2
JP18
.1UF
LOCAL OSC INPUT
2
CC0603
C30
CC0603
3
ETC1-1-13
AGND2;3,4,5
R29
4
0
SMAEDGE
J2
C26
100PF
C25
100PF
1
S
P
T4
5
RC0603
RC0603
R20
50
2
CC0603
2
SMAEDGE
RC0603
100PF
G3
VOUT
LOIP
LOIN
5
G1B
4
3
IBBP
1
2
G1A
AGND2;17
2
6
14
13
U3
VPS2
G4A
100PF
G4B
16
CC0603
C27
QBBN
CC0603
QBBP
C20
10UF
10V
IBBN
BCASE
.1UF
C29
15
AVDD2
AGND2;3,4,5
0
CC0603
C28
R27
JP21
2
JP22
O1P
DNP
CC0805
CC0805
L3
DNP
LC0805
C32
RC0603
LC0805
DNP
C22
51
C 21
DNP
JP20
R25
51
R24
RC0603
DNP
RC0603
Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board
Rev. G | Page 36 of 44
00617-092
O1N
R26
DNP
CC0603
2
L4
Rev. G | Page 37 of 44
Figure 89. Digital Input Signaling (1)
P1
35
37
39
36
38
40
HDR040RA
33
29
27
25
23
21
19
34
HDR040RA
SPARES
10
10
RP6
7
INP8
15
INCK1
INP14
INP13
INP12
INP11
INP10
INP9
INP7
13
17
INP6
INP4
7
INP5
INP3
5
9
INP2
3
11
INP1
1
31
RIBBON RA
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
8
5
3
1
7
RC0603
RP5
RP5
RP5
RP6
RP6
RP6
RP6
RP5
5
3
1
10
10
10
10
10
9
12
14
16
10
10
10
10
12
14
16
6
4
2
8
RP5
RP5
RP5
RP6
RP6
RP6
RP5
6
4
2
RC0603
R62
470
RC0603
10
10
10
10
11
13
15
9
10
10
10
11
13
15
R61
470
RC0603
R60
470
RC0603
R59
470
RC0603
R58
470
RC0603
R57
470
RC0603
R56
470
RC0603
R55
470
RC0603
R54
470
RC0603
R53
470
RC0603
R52
470
RC0603
R51
470
RC0603
R50
470
RC0603
R33
470
DCLKIN1
DUTP14
DUTP13
DUTP12
DUTP11
DUTP10
DUTP9
DUTP8
DUTP7
DUTP6
DUTP5
DUTP4
DUTP3
DUTP2
DUTP1
R49
470
Data Sheet
AD9763/AD9765/AD9767
00617-093
Rev. G | Page 38 of 44
Figure 90. Digital Input Signaling (2)
P2
37
39
38
40
HDR040RA
35
36
HDR040RA
33
34
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
31
RIBBON RA
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1010
RP87
SPARES
INCK2
8 RP8 10 9
INP36
6 RP7 1011
6 RP8 1011
4 RP8 1013
RC0603
7 RP7 1010
5 RP7 1012
1 RP7 1016
2 RP7 1015
3 RP7 1014
4 RP7 1013
5 RP8 1012
8 RP7 10 9
1 RP8 1016
2 RP8 1015
3 RP8 1014
INP31
INP34
INP35
INP28
INP27
INP30
INP33
INP25
INP26
INP29
INP32
INP23
INP24
RC0603
R34
470
RC0603
R35
470
RC0603
R48
470
RC0603
R36
470
RC0603
R37
470
RC0603
R47
470
RC0603
R38
470
RC0603
R39
470
RC0603
R46
470
RC0603
R45
470
RC0603
R44
470
RC0603
R43
470
RC0603
R40
470
RC0603
R42
470
DCLKIN2
DUTP36
DUTP35
DUTP34
DUTP33
DUTP32
DUTP31
DUTP30
DUTP29
DUTP28
DUTP27
DUTP26
DUTP25
DUTP24
DUTP23
R41
470
AD9763/AD9765/AD9767
Data Sheet
00617-087
Rev. G | Page 39 of 44
DUTP23
DUTP24
WRT1
CLK1
CLK2
WRT2
DUTP1
DUTP2
DUTP3
DUTP4
DUTP5
DUTP6
DUTP7
DUTP8
DUTP9
DUTP10
DUTP11
DUTP12
DUTP13
DUTP14
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VAL
CC0805
C2
C3
.1UF
CC0805
DVDD
DB13P1MSB
MODE
DB12P1
AVDD
DB11P1
IA1
DB10P1
IB1
DB9P1
FSADJ1
DB8P1
REFIO
DB7P1
ACOM1
DB6P1
FSADJ2
DB5P1
IB2
DB4P1
IA2
DB3P1
ACOM
DB2P1
SLEEP
U1
DB1P1AD9763/65/67 DB0P2
DB1P2
DB0P1
DB2P2
DCOM1
DB3P2
DVDD1
DB4P2
WRT1
DB5P2
CLK1
CLK2
DB6P2
DB7P2
WRT2
DB8P2
DCOM2
DB9P2
DVDD2
DB13P2MSB
DB10P2
DB12P2
DB11P2
.01UF
CC0805
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 91. Device Under Test/Analog Output Signal Conditioning
C11
VAL
CC0805
SLEEP
DUTP36
DUTP35
DUTP34
DUTP33
DUTP32
DUTP31
DUTP30
DUTP29
DUTP28
DUTP27
DUTP26
DUTP25
MODEJP8
1 A B 3
2
CC0805
R32
O2P
C12
.01UF
CC0805
10PF
CC0805
C15
10PF
C4
CC0805
C13
.1UF
RC0805
10
O2N
JP11
JP7
JP24
JP12
JP6
O1N
O1P
JP23
RC0805
RC0805
RC0805
10
AVDD
R7
50
R5
50
10PF
CC0805
C6
10PF
CC0805
C5
RC0805
RC0805
R31
R8
50
R6
50
C16
C17
R12
VAL
WHT
R10
RC0805
1.92K
22NF
22NF
RC0805
R9 1.92K
R11
VAL
WHT
RC07CUP
CC0805
CC0805
ACOM JP15
1 A B 3
2
AVDD
3
2
1
6
5
4
T6
RC0805
256
RC0805
256
4
6
5
BL4
BL3
BL2
T1-1TCUP
T5
T1-1TCUP
JP10
R14
R15
3
2
1
BL1
WHT
WHT
OUT1
S11
SMA200UP
OUT2
AGND;3,4,5
.1UF
CC0805
C14
WHT
REFIO
S6
SMA200UP
AGND;3,4,5
00617-088
DVDD
Data Sheet
AD9763/AD9765/AD9767
RC07CUP
AD9763/AD9765/AD9767
Data Sheet
00617-089
EVALUATION BOARD LAYOUT
Figure 92. Assembly, Top Side
Rev. G | Page 40 of 44
AD9763/AD9765/AD9767
00617-090
Data Sheet
Figure 93. Assembly, Bottom Side
Rev. G | Page 41 of 44
AD9763/AD9765/AD9767
Data Sheet
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 94. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9763ASTZ
AD9763ASTZRL
AD9763-EBZ
AD9765AST
AD9765ASTRL
AD9765ASTZ
AD9765ASTZRL
AD9765-EBZ
AD9767ASTZ
AD9767ASTZRL
AD9767-EBZ
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. G | Page 42 of 44
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
Data Sheet
AD9763/AD9765/AD9767
NOTES
Rev. G | Page 43 of 44
AD9763/AD9765/AD9767
Data Sheet
NOTES
©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00617-0-8/11(G)
Rev. G | Page 44 of 44