AD ADSP-2184NKSTZ-320

a
DSP Microcomputer
ADSP-218xN Series
PERFORMANCE FEATURES
SYSTEM INTERFACE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sustained performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down
condition
Low power dissipation in idle mode
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
All inputs tolerate up to 3.6 V regardless of mode
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and program overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Programmable wait state generation
Two double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from bytewide external memory, for example, EPROM, or through
internal DMA Port
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final
systems
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 256K byte of on-chip RAM, configured
Up to 48K words program memory RAM
Up to 56K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
Two independent data address generators
Powerful program sequencer provides zero overhead looping conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
PO W E R-DO WN
C ONTR O L
FU L L M EM O R Y M O D E
M EM OR Y
D A T A A D D RES S
G ENERAT OR S
D A G1
D AG2
PROG RAM
SEQ U ENCER
PRO GRA M
ME M ORY
UP TO
48K ⴛ 24-B IT
PROG RA MM ABL E
I/O
AND
F LA GS
D A TA
ME M ORY
UP TO
56K ⴛ 16-B IT
P R O GR A M M EM O R Y AD D R ES S
EX TE RNAL
D A TA
BUS
D ATA M EM O RY A D D R ES S
BY TE DM A
C ON T R OLL ER
PR O GRAM M EMO R Y DATA
OR
DA TA M E M OR Y DA TA
A R ITH M ETIC UN ITS
A LU
MAC
S H IFTE R
EX TE RNAL
AD D R ES S
BUS
EX TE RNAL
D A TA
BUS
S ER IAL PO R TS
S POR T0
T IM ER
SPOR T 1
A DS P-2100 B AS E
A RC H IT EC T UR E
INTER NA L
DMA
P ORT
H OS T M OD E
Figure 1. Functional Block Diagram
ICE-Port is a trademark of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
ADSP-218xN
TABLE OF CONTENTS
General Description ................................................. 3
REVISION HISTORY
Architecture Overview ........................................... 3
8/06—Rev. 0 to Rev. A
Modes Of Operation .............................................. 5
Miscellaneous Format Updates.......................... Universal
Interrupts ........................................................... 5
Applied Corrections or Additional Information to:
Low-power Operation ............................................ 6
Clock Signals ....................................................... 8
System Interface ................................................... 7
External Crystal Connections .................................. 8
Reset .................................................................. 8
ADSP-2185 Memory Architecture ............................ 9
Power Supplies ..................................................... 8
Electrical Characteristics ....................................... 22
Memory Architecture ............................................ 9
Absolute Maximum Ratings ................................... 23
Bus Request and Bus Grant ................................... 14
ESD Diode Protection .......................................... 24
Flag I/O Pins ..................................................... 15
Memory Read ..................................................... 31
Instruction Set Description ................................... 15
Memory Write .................................................... 32
Development System ........................................... 15
Serial Ports ........................................................ 33
Additional Information ........................................ 17
Outline Dimensions ............................................. 45
Pin Descriptions .................................................... 18
Ordering Guide .................................................. 47
Memory Interface Pins ......................................... 19
Terminating Unused Pins ..................................... 19
Specifications ........................................................ 22
Recommended Operating Conditions ...................... 22
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings .................................. 23
ESD Sensitivity ................................................... 23
ESD Diode Protection .......................................... 24
Power Dissipation ............................................... 24
Environmental Conditions .................................... 25
Test Conditions .................................................. 25
Timing Specifications .......................................... 26
LQFP Package Pinout .......................................... 40
BGA Package Pinout ........................................... 42
Outline Dimensions ............................................... 45
Surface Mount Design .......................................... 46
Ordering Guide ..................................................... 47
Rev. A |
Page 2 of 48 |
August 2006
ADSP-218xN
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. The
high-level block diagram for the ADSP-218xN series members
appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip
SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.
Specific family members are shown in Table 1.
Table 1. ADSP-218xN DSP Microcomputer Family
Device
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
Program Memory
(K words)
4
16
8
32
48
32
Data Memory
(K words)
4
16
8
32
56
48
ADSP-218xN series members combine the ADSP-2100 family
base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
ADSP-218xN series members integrate up to 256K bytes of onchip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of
battery-operated portable equipment. The ADSP-218xN is
available in a 100-lead LQFP package and 144-ball BGA.
Fabricated in a high-speed, low-power, 0.18 μm CMOS process,
ADSP-218xN series members operate with a 12.5 ns instruction
cycle time. Every instruction can execute in a single processor cycle.
The ADSP-218xN’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xN series
members can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Receive and/or transmit data through the byte DMA port
• Decrement timer
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible data
moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-218xN assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram is an overall block diagram of the
ADSP-218xN series. The processor contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, ADSP-218xN series members
execute looped code with zero overhead; no explicit jump
instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for
circular buffers.
Five internal buses provide efficient data transfer:
• Update one or two data address pointers
• Program Memory Address (PMA) Bus
• Perform a computational operation
• Program Memory Data (PMD) Bus
This takes place while the processor continues to:
• Data Memory Address (DMA) Bus
• Receive and transmit data through the two serial ports
• Data Memory Data (DMD) Bus
• Receive and/or transmit data through the internal
DMA port
Rev. A |
• Result (R) Bus
Page 3 of 48 |
August 2006
ADSP-218xN
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting ADSP-218xN series members to fetch two operands in a
single cycle, one from program memory and one from data
memory. ADSP-218xN series members can fetch an operand
from program memory and the next instruction in the
same cycle.
Serial Ports
ADSP-218xN series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-218xN
SPORTs. For additional information on Serial Ports, refer to the
ADSP-218x DSP Hardware Reference.
In lieu of the address and data bus for external memory connection, ADSP-218xN series members may be configured for 16-bit
Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSP’s on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
ADSP-218xN to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses
are granted.
ADSP-218xN series members can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORT), the
BDMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit
and receive modes of operation.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with
either of two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 bits to
16 bits and provide optional A-law and μ-law companding,
according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 word or 32-word, time-division multiplexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this
configuration.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
ADSP-218xN series members provide up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Rev. A |
Page 4 of 48 |
August 2006
ADSP-218xN
MODES OF OPERATION
The ADSP-218xN series modes of operation appear in Table 2.
Table 2. Modes of Operation
1
Mode D
X
Mode C
0
Mode B
0
Mode A
0
X
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
Booting Method
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Full Memory Mode.1
No automatic boot operations occur. Program execution starts at external memory
location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the
processor does not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode. IACK has active pull-down. (Requires additonal hardware.)
IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK has active pull-down.1
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode; IACK requires external pull-down. (Requires additonal
hardware.)
IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK requires external pull-down.1
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
Setting Memory Mode
Memory Mode selection for the ADSP-218xN series is made
during chip reset through the use of the Mode C pin. This pin is
multiplexed with the DSP’s PF2 pin, so care must be taken in
how the mode selection is made. The two methods for selecting
the value of Mode C are active and passive.
Passive Configuration
Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down resistance, on the
order of 10 kΩ, can be used. This value should be sufficient to
pull the pin to the desired level and still allow the pin to operate
as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the pullup or pull-down resistance will hold the pin in a known state,
and will not switch.
Active Configuration
Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should be three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
Rev. A |
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IDMA ACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven signal
and cannot be “wire-OR’ed.” Mode D = 1 and in host mode:
IACK is an open drain and requires an external pull-down, but
multiple IACK pins can be “wire-OR’ed” together.
INTERRUPTS
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
ADSP-218xN series members provide four dedicated external
interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared
with the PF7–4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI, and FO, for a total of six external
interrupts. The ADSP-218xN also supports internal interrupts
from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins
can be programmed to be either level- or edge-sensitive. IRQL0
and IRQL1 are level-sensitive and IRQE is edge-sensitive. The
priorities and vector addresses of all interrupts are shown in
Table 3.
Page 5 of 48 |
August 2006
ADSP-218xN
Table 3. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
Reset (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Interrupt Vector Address
(Hex)
0x0000 (Highest Priority)
0x002C
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028 (Lowest Priority)
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
ADSP-218xN series members have a low-power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-218x DSP Hardware Reference, “System Interface” chapter, for detailed information about
the power-down feature.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits
approximately 4096 CLKIN cycles for the crystal oscillator
to start or stabilize), and letting the oscillator run to allow
200 CLKIN cycle start-up.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt.
ADSP-218xN series members mask all interrupts for one
instruction cycle following the execution of an instruction that
modifies the IMASK register. This does not affect serial port
autobuffering or DMA transfers.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving
the power-down state.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are 12 levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power-down), regardless
of the state of IMASK:
ENA INTS;
DIS INTS;
Disabling the interrupts does not affect serial port autobuffering
or DMA. When the processor is reset, interrupt servicing
is enabled.
LOW-POWER OPERATION
ADSP-218xN series members have three low-power modes that
significantly reduce the power dissipation when the device operates under standby conditions. These modes are:
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin (PWDACK) indicates when
the processor has entered power-down.
Idle
When the ADSP-218xN is in the Idle Mode, the processor waits
indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA, and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on ADSP-218xN series members to let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
• Power-Down
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
• Idle
• Slow Idle
Rev. A |
Page 6 of 48 |
August 2006
ADSP-218xN
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xN series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming normal operation.
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xN series members also provide four external interrupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
FULL MEMORY MODE
1/2 ⴛ CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
HOST MEMORY MODE
ADSP-218xN
ADSP-218xN
1/2 ⴛ CLOCK
OR
CRYSTAL
CLKIN
XTAL
ADDR13–0 14
A13–0
FL0–2
D23–16
24
IRQ2/PF7
IRQE/PF4 DATA23–0
IRQL0/PF5
BMS
IRQL1/PF6
WR
MODE D/PF3
RD
MODE C/PF2
MODE A/PF0
MODE B/PF1
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
PMS
DR1 OR FI
ert
DMSIns
CMS
SPORT0
SCLK0
BR
RFS0
BG
TFS0
BGH
DT0
PWD
DR0
PWDACK
D15–8
CLKIN
XTAL
A0–A21
FL0–2
BYTE
MEMORY
DATA
IRQ2/PF7
IRQE/PF4 DATA23–8
IRQL0/PF5
IRQL1/PF6
BMS
MODE D/PF3
WR
MODE C/PF2
RD
MODE A/PF0
CS
A10–0
ADDR
D23–8
DATA
CS
re
I/O SPACE
he
(PERIPHERALS)
m
2048
gra LOCATIONS
MODE B/PF1
dia
ce
rfa
e
t
in ADDR
D23–0
em
t
s
DATA
sy
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
A13–0
SERIAL
DEVICE
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
µCONTROLLER
16
Figure 2. Basic System Interface
Rev. A |
Page 7 of 48 |
A0
August 2006
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
IDMA PORT
PWDACK
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
1
16
ADSP-218xN
Clock Signals
ADSP-218xN series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to the ADSP-218x
DSP Hardware Reference, for detailed information on this
power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xN series members use an input clock with a frequency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xN series members include an on-chip oscillator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulse-width specification (tRSP).
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from onchip program memory location 0x0000 once boot loading
completes.
POWER SUPPLIES
ADSP-218xN series members have separate power supply connections for the internal (VDDINT) and external (VDDEXT) power
supplies. The internal supply must meet the 1.8 V requirement.
The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up to
3.6 V, regardless of the external supply voltage. This feature provides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V
components.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
1M ⍀
X TAL
C L K IN
CLKO UT
DSP
Figure 3. External Crystal Connections
RESET
The RESET signal initiates a master reset of the ADSP-218xN.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
Rev. A |
Page 8 of 48 |
August 2006
ADSP-218xN
MEMORY ARCHITECTURE
The ADSP-218xN series provides a variety of memory and
peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to
PROGRAM MEMORY
MODEB = 1
0x3FFF
Figure 4 through Figure 9, Table 4 on Page 11, and Table 5 on
Page 11 for PM and DM memory allocations in the ADSP218xN series.
PROGRAM MEMORY
MODEB = 0
0x3FFF
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
PM OVERLAY 0
(RESERVED)
0x2000
0x1FFF
0x2000
0x1FFF
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
0x3000
0x2FFF
0x2000
0x1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
0x1000
0x0FFF
DM OVERLAY 0
(RESERVED)
INTERNAL PM
0x0000
0x0000
4064 RESERVED
WORDS
INTERNAL DM
RESERVED
EXTERNAL PM
DATA MEMORY
0x0000
Figure 4. ADSP-2184 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
DATA MEMORY
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY 0
(INTERNAL PM)
0x2000
0x1FFF
0x2000
0x1FFF
EXTERNAL PM
INTERNAL DM
0x2000
0x1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0
(INTERNAL DM)
0x0000
0x0000
0x0000
Figure 5. ADSP-2185 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
DATA MEMORY
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY 0
(RESERVED)
0x2000
0x1FFF
0x2000
0x1FFF
EXTERNAL PM
INTERNAL DM
0x2000
0x1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0
(RESERVED)
0x0000
0x0000
0x0000
Figure 6. ADSP-2186 Memory Architecture
Rev. A |
Page 9 of 48 |
August 2006
ADSP-218xN
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
DATA MEMORY
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY 0,4,5
(INTERNAL PM)
0x2000
0x1FFF
0x2000
0x1FFF
INTERNAL DM
0x2000
0x1FFF
EXTERNAL PM
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0,4,5
(INTERNAL DM)
0x0000
0x0000
0x0000
Figure 7. ADSP-2187 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
DATA MEMORY
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY
0,4,5,6,7
(INTERNAL PM)
0x2000
0x1FFF
0x2000
0x1FFF
0x2000
0x1FFF
EXTERNAL PM
INTERNAL PM
0x0000
0x0000
INTERNAL DM
0x0000
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY
0,4,5,6,7,8
(INTERNAL DM)
Figure 8. ADSP-2188 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
DATA MEMORY
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY 0,4,5
(INTERNAL PM)
0x2000
0x1FFF
0x2000
0x1FFF
0x2000
0x1FFF
EXTERNAL PM
0x0000
INTERNAL DM
INTERNAL PM
0x0000
0x0000
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY
0,4,5,6,7
(INTERNAL DM)
Figure 9. ADSP-2189 Memory Architecture
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The member
Rev. A |
DSPs of this series have up to 48K words of Program Memory
RAM on chip, and the capability of accessing up to two 8K
external memory overlay spaces, using the external data bus.
Page 10 of 48 |
August 2006
ADSP-218xN
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is only 16 bits wide.
Table 4. PMOVLAY Bits
Processor
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
All Processors
PMOVLAY
No Internal Overlay
Region
0
No Internal Overlay
Region
0, 4, 5
0, 4, 5, 6, 7
0, 4, 5
1
2
Memory
Not Applicable
A13
Not Applicable
A12–0
Not Applicable
Internal Overlay
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Internal Overlay
Internal Overlay
Internal Overlay
External Overlay 1
External Overlay 2
Not Applicable
Not Applicable
Not Applicable
0
1
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control registers. The ADSP-218xN series has up to 56K words of
Data Memory RAM on-chip. Part of this space is used by 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register and the wait state mode bit.
Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external
address line (A0).
Table 5. DMOVLAY Bits
Processor
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
DMOVLAY
No Internal Overlay Region
0
No Internal Overlay Region
0, 4, 5
0, 4, 5, 6, 7, 8
0, 4, 5, 6, 7
1
Memory
Not Applicable
Internal Overlay
Not Applicable
Internal Overlay
Internal Overlay
Internal Overlay
External Overlay 1
A13
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
0
All Processors
2
External Overlay 2
1
Memory-Mapped Registers (New to the ADSP-218xM and
N series)
ADSP-218xN series members have three memory-mapped registers that differ from other ADSP-21xx Family DSPs. The slight
modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control, and System Control)
provide the ADSP-218xN’s wait state and BMS control features.
Default bit values at reset are shown; if no value is shown, the bit
is undefined at reset. Reserved bits are shown on a grey field.
These bits should always be written with zeros.
Rev. A |
A12–0
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address
Between 0x0000 and
0x1FFF
13 LSBs of Address
Between 0x0000 and
0x1FFF
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional external
memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
I/O space supports 2048 locations of 16-bit wide data. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
Page 11 of 48 |
August 2006
ADSP-218xN
IOWAIT0–3 as shown in Figure 10, which in combination with
the wait state mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act
on address ranges, as shown in Table 6.
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
15 14 13 12 11 10 9
1
Note: In Full Memory Mode, all 2048 locations of I/O space are
directly addressable. In Host Memory Mode, only address pin
A0 is available; therefore, additional logic is required externally
to achieve complete addressability of the 2048 I/O
space locations.
1
1
1
1
0
B MW AIT
1
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
CM S SEL
0 = DIS ABLE CMS
1 = E NABLE CMS
DM(0x3FE6)
PF TY P E
0 = IN PUT
1 = O UTP UT
( WH ERE BIT : 11- IOM , 10-B M, 9-DM , 8-PM )
Figure 11. Programmable Flag and Composite Control Register
Table 6. Wait States
SYSTEM CONTROL
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Wait State Register
IOWAIT0 and Wait State Mode Select Bit
IOWAIT1 and Wait State Mode Select Bit
IOWAIT2 and Wait State Mode Select Bit
IOWAIT3 and Wait State Mode Select Bit
1
1
1
1
1
9
8
7
6
5
4
1
1
1
1
1
1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
RESERVED,ALW AYS
SET TO 0
SPO RT0 ENABL E
0 = DISABL E
1 = ENABL E
SPORT 1 ENABLE
0 = DISABLE
1 = ENABLE
3 2 te1r 0
is
DM(0x3FFE)
1 eg1 1 1
R
l
o
r
t
on
DWAIT
IOWAIT3
IOWAIT2 IOWAIT1
IOWAIT0
eC
t
a
t
S
WAIT STATE MODE SELECT
ait IOWAIT0–3 = N WAIT STATES,
0 = NORMAL MODE (PWAIT, DWAIT,
rt W
RANGING FROM 0 TOse7)
In DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
1 = 2N + 1 MODE (PWAIT,
1
8
0
R ESERVED
SET T O 0
WAIT STATE CONTROL
15 14 13 12 11 10
15 14 13 12 11 10 9
DM(0x3F FF)
PWAIT
PROGRAM MEMOR Y
W AIT ST ATES
DISABLE BMS
0 = ENABL E BMS
1 = DISAB LE BMS
SPO RT1 C ONF IGURE
0 = FI, FO , IRQ0, IRQ1, SCLK
1 = SPO RT1
N OTE: RESERVED BITS ARE SHO WN O N A G RAY FIELD . THESE B ITS
SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS.
Figure 12. System Control Register
RANGING FROM 0 TO 15)
select, and a flash memory could be connected to CMS. Because
at reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the flash memory.
Figure 10. Wait State Control Register
Composite Memory Select
ADSP-218xN series members have a programmable memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal
is generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when
set, causes the CMS signal to be asserted when the selected
memory select is asserted. For example, to use a 32K word
memory to act as both program and data memory, set the PMS
and DMS bits in the CMSSEL register and use the CMS pin to
drive the chip select of the memory, and use either DMS or PMS
as the additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
See Figure 11 and Figure 12 for illustration of the programmable flag and composite control register and the system
control register.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data. Byte
memory is accessed using the BDMA feature. The byte memory
space consists of 256 pages, each of which is 16K ⴛ 8 bits.
The byte memory space on the ADSP-218xN series supports
read and write operations as well as four different data formats.
The byte memory uses data bits 15–8 for data. The byte memory uses data bits 23–16 and address bits 13–0 to create a 22-bit
address. This allows up to a 4 megabit ⴛ 8 (32 megabit) ROM
or RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller (Figure 13) allows loading
and storing of program instructions and data using the byte
memory space. The BDMA circuit is able to access the byte
memory space while the processor is operating normally and
steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
Byte Memory Select
The ADSP-218xN’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
Rev. A |
Page 12 of 48 |
August 2006
ADSP-218xN
BDMA CONTROL
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
BMPAGE
BDMA
OVERLAY
BITS
(SEE TABLE 12)
DM (0x3FE3)
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Figure 13. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number of
8-bit accesses are done from the byte memory space to build the
word size selected. Table 7 shows the data formats supported by
the BDMA circuit.
Internal Memory
Space
Program Memory
Data Memory
Data Memory
Data Memory
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. Set these bits as indicated in
Figure 13.
Note: BDMA cannot access external overlay memory regions 1
and 2.
The BMWAIT field, which has four bits on ADSP-218xN series
members, allows selection up to 15 wait states for BDMA
transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
Table 7. Data Formats
BTYPE
00
01
10
11
The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
The IDMA Port provides an efficient means of communication
between a host system and ADSP-218xN series members. The
port is used to access the on-chip program memory and data
memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the
DSP’s memory-mapped control registers. A typical IDMA
transfer process is shown as follows:
1. Host starts IDMA transfer.
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1,
the values of Bits 7–0 represent the IDMA overlay; Bits
14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13–0
represent the starting address of internal memory to be
accessed and Bit 14 reflects PM or DM for access. Set
IDDMOVLAY and IDPMOVLAY bits in the IDMA overlay register as indicted in Table 8.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
4. Host uses IS and IRD (or IWR) to read (or write) DSP
internal memory (PM or DM).
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be onchip program or data memory.
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
Table 8. IDMA/BDMA Overlay Bits
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory accesses.
Rev. A |
Page 13 of 48 |
Processor
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
August 2006
IDMA/BDMA
PMOVLAY
0
0
0
0, 4, 5
0, 4, 5, 6, 7
0, 4, 5
IDMA/BDMA
DMOVLAY
0
0
0
0, 4, 5
0, 4, 5, 6, 7, 8
0, 4, 5, 6, 7
ADSP-218xN
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-218xN
is operating at full speed.
IDMA OVERLAY
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESERVED SET TO 0
DM (0x3FE7)
IDDMOVLAY
IDPMOVLAY
(SEE TABLE 12)
SHORT READ
ONLY
0 = DISABLE
1 = ENABLE
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10 9
0
IDMA port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or PM
access. The falling edge of the IDMA address latch signal (IAL)
or the missing edge of the IDMA select signal (IS) latches this
value into the IDMAA register.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
9
0
RESERVED SET TO 0
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This
increases throughput as the address does not have to be sent for
each memory access.
Once the address is stored, data can be read from, or written to,
the ADSP-218xN’s on-chip memory. Asserting the select line
(IS) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-218xN that a particular transaction is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
15 14 13 12 11 10
U
U
U
U
U
U
8
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
DM (0x3FE0)
IDMAA ADDRESS
IDMAD DESTINATION MEMORY
TYPE
0 = PM
1 = DM
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE
BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
RESERVED SET TO 0
Figure 14. IDMA OVLAY/Control Registers
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is set
to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch enable
(IAL) directs the ADSP-218xN to write the address onto the
IAD14–0 bus into the IDMA Control Register (Figure 14). If Bit
15 is set to 0, IDMA latches the address. If Bit 15 is set to 1,
IDMA latches into the OVLAY register. This register, also
shown in Figure 14, is memory-mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) cannot be
read back by the host.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space-compatible boot code.
When Bit 14 in 0x3FE7 is set to zero, short reads use the timing
shown in Figure 36 on Page 38. When Bit 14 in 0x3FE7 is set to
1, timing in Figure 37 on Page 39 applies for short reads in short
read only mode. Set IDDMOVLAY and IDPMOVLAY bits in
the IDMA overlay register as indicated in Table 8. Refer to the
ADSP-218x DSP Hardware Reference for additional details.
IDMA Port Booting
Note: In full memory mode all locations of 4M-byte memory
space are directly addressable. In host memory mode, only
address pin A0 is available, requiring additional external logic to
provide address information for the byte.
Bootstrap Loading (Booting)
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the
ADSP-218xN. The only memory address bit provided by the
processor is A0.
ADSP-218xN series members can also boot programs through
its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A
= 1, the ADSP-218xN boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execution is held off until the host writes to on-chip program memory
location 0.
BUS REQUEST AND BUS GRANT
ADSP-218xN series members can relinquish control of the data
and address buses to an external device. When the external
device requires access to memory, it asserts the Bus Request
ADSP-218xN series members have two mechanisms to allow
automatic loading of the internal program memory after reset.
The method for booting is controlled by the Mode A, B, and C
configuration bits.
When the mode pins specify BDMA booting, the ADSP-218xN
initiates a BDMA boot sequence when reset is released.
Rev. A |
Page 14 of 48 |
August 2006
ADSP-218xN
(BR) signal. If the ADSP-218xN is not performing an external
memory access, it responds to the active BR input in the following processor cycle by:
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
INSTRUCTION SET DESCRIPTION
The ADSP-218xN series assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles
a simple equation.
• Halting program execution.
If Go Mode is enabled, the ADSP-218xN will not halt program
execution until it encounters an instruction that requires an
external memory access.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
If an ADSP-218xN series member is performing an external
memory access when the external device asserts the BR signal, it
will not three-state the memory interfaces nor assert the BG signal until the processor cycle after the access completes. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be
relocated to utilize on-chip memory and conform to the
ADSP-218xN’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the condition
can be checked and the operation executed in the same
instruction cycle.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when an ADSP-218xN series member
requires the external bus for a memory or BDMA access, but is
stopped. The other device can release the bus by deasserting bus
request. Once the bus is released, the ADSP-218xN deasserts BG
and BGH and executes the external memory access.
FLAG I/O PINS
ADSP-218xN series members have eight general-purpose programmable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the
ADSP-218xN’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.
FL0 to FL2 are dedicated output flags. FI and FO are available as
an alternate configuration of SPORT1.
• Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruction cycle.
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The DSP
tools include an integrated development environment, an evaluation kit, and a serial port emulator.
VisualDSP++®† is an integrated development environment,
allowing for fast and easy development, debug, and deployment.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder); a linker; a
PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP
and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset.
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
†
Rev. A |
Page 15 of 48 |
VisualDSP++ is a registered trademark of Analog Devices, Inc.
August 2006
ADSP-218xN
• Fill and dump memory
• Complete assembly and disassembly of instructions
• Source level debugging
• C source-level debugging
The VisualDSP++ IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the ADSP218xN development tools, including the syntax highlighting in
the VisualDSP++ editor. This capability controls how the development tools process inputs and generate outputs.
The ADSP-2189M EZ-KIT Lite®† provides developers with a
cost-effective method for initial evaluation of the powerful
ADSP-218xN DSP family architecture. The ADSP-2189M EZKIT Lite includes a stand-alone ADSP-2189M DSP board supported by an evaluation suite of VisualDSP++. With this EZKIT Lite, users can learn about DSP hardware and software
development and evaluate potential applications of the ADSP218xN series. The ADSP-2189M EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development environment with
the C compiler, assembler, and linker. The size of the DSP executable that can be built using the EZ-KIT Lite tools is limited to
8K words.
The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demonstration Programs
• Evaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE®‡ Emulator provides an easier and
more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for
faster time-to-market. ADSP-218xN series members integrate
on-chip emulation support with a 14-pin ICE-Port interface.
This interface provides a simpler target board connection that
requires fewer mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. ADSP-218xN series members
need not be removed from the target system when using the EZICE, nor are any adapters needed. Due to the small footprint of
the EZ-ICE connector, emulation can be supported in final
board designs.The EZ-ICE performs a full range of functions,
including:
Designing an EZ-ICE-Compatible System
ADSP-218xN series members have on-chip emulation support
and an ICE-Port, a special set of pins that interface to the EZICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s incircuit probe, a 14-pin plug.
Note: The EZ-ICE uses the same VDD voltage as the VDD voltage
used for VDDEXT. Because the input pins of the ADSP-218xN
series members are tolerant to input voltages up to 3.6 V,
regardless of the value of VDDEXT, the voltage setting for the EZICE must not exceed 3.3 V.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information
is being used (as discussed in Setting Memory Mode on Page 5),
it does not matter that the mode information is latched by an
emulator reset. However, if the RESET pin is being used as a
method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 15. This circuit forces the value located on the Mode A
pin to logic high, regardless of whether it is latched via the
RESET or ERESET pin.
ERESET
RESET
ADSP-218xN
1k⍀
MODE A/PF0
PROGRAMMABLE I/O
Figure 15. Mode A Pin/EZ-ICE Circuit
• In-target operation
The ICE-Port interface consists of the following ADSP-218xN
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and
ELOUT.
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting
and execution
These ADSP-218xN pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the
ADSP-218xN and the connector must be kept as short as possible, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG, RESET,
and GND.
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
‡
EZ-ICE is a registered trademark of Analog Devices, Inc.
Rev. A |
Page 16 of 48 |
August 2006
ADSP-218xN
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-218xN in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET,
BR, and BG pins. The BG output is three-stated. These signals
do not need to be jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable and
a 14-pin female plug. The female plug is plugged onto the 14pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 16. This connector must be added to the target board
design to use the EZ-ICE. Be sure to allow enough room in the
system to fit the EZ-ICE probe onto the 14-pin connector.
1
2
3
4
BG
GND
EBG
Restriction: All memory strobe signals on the ADSP-218xN
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed
when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design the system to be compatible with
the following system interface signal changes introduced by the
EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.
BR
5
6
7
ⴛ
8
9
10
11
12
13
14
EBR
KEY (NO PIN)
difficult to manufacture, as DSP components statistically vary in
switching characteristic and timing requirements, within published limits.
EINT
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.
ELIN
ELOUT
ECLK
• EZ-ICE emulation ignores RESET and BR, when
single-stepping.
EMS
EE
RESET
ERESET
• EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).
TOP VIEW
Figure 16. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1ⴛ0.1 inch. The pin strip header must have at least
0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
ADDITIONAL INFORMATION
This data sheet provides a general overview of ADSP-218xN
series functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x
DSP Hardware Reference and the ADSP-218x DSP Instruction
Set Reference.
For the target system to be compatible with the EZ-ICE emulator, it must comply with the following memory interface
guidelines:
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case device
timing requirements and switching characteristics as specified
in this data sheet. The performance of the EZ-ICE may
approach published worst-case specification for some memory
access timing requirements and switching characteristics.
Note: If the target does not meet the worst-case chip specification for memory access parameters, the circuitry may not be
able to be emulated at the desired CLKIN frequency. Depending
on the severity of the specification violation, the system may be
Rev. A |
Page 17 of 48 |
August 2006
ADSP-218xN
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead LQFP
package and a 144-ball BGA package. In order to maintain maximum functionality and reduce package size and pin count,
some serial port, programmable flag, interrupt and external bus
pins have dual, multiplexed functionality. The external bus pins
are configured during RESET only, while serial port pins are
software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed
pins. In cases where pin functionality is reconfigurable, the
default state is shown in plain text in Table 9, while alternate
functionality is shown in italics.
Table 9. Common-Mode Pins
Pin Name
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1–0, FI, FO
PWD
PWDACK
FL0, FL1, FL2
VDDINT
VDDEXT
GND
No. of Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
I/O
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
O
I/O
I/O
1
1
3
2
4
10
I
O
O
I
I
I
1
1
1
1
1
1
1
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Clock Input
Quartz Crystal Output
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO2
Power-Down Control Input
Power-Down Acknowledge Control Output
Output Flags
Internal VDD (1.8 V) Power (LQFP)
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
Ground (LQFP)
Rev. A |
Page 18 of 48 |
August 2006
ADSP-218xN
Table 9. Common-Mode Pins (Continued)
Pin Name
VDDINT
VDDEXT
GND
EZ-Port
No. of Pins
4
7
20
9
I/O
I
I
I
I/O
Function
Internal VDD (1.8 V) Power (BGA)
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (BGA)
Ground (BGA)
For Emulation Use
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
MEMORY INTERFACE PINS
ADSP-218xN series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. Table 10 and Table 11 list the active signals at specific
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on
Page 41 and Table 28 on Page 43.
Table 10. Full Memory Mode Pins (Mode C = 0)
Pin Name
A13–0
D23–0
No. of Pins
14
24
I/O
O
I/O
Function
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Table 11. Host Mode Pins (Mode C = 1)
Pin Name
IAD15–0
A0
D23–8
IWR
IRD
IAL
IS
IACK
1
No. of Pins
16
1
16
1
1
1
1
1
I/O
I/O
O
I/O
I
I
I
I
O
Function
IDMA Port Address/Data Bus
Address Pin for External I/O, Program, Data, or Byte Access1
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
TERMINATING UNUSED PINS
Table 12 shows the recommendations for terminating unused
pins.
Table 12. Unused Pin Terminations
Pin Name1
XTAL
CLKOUT
A13–1 or
IAD12–0
A0
I/O
3-State
(Z)2
O
O
O (Z)
I/O (Z)
O (Z)
Reset
State
O
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z3 Caused By
BR, EBR
IS
BR, EBR
Rev. A |
Page 19 of 48 |
Unused Configuration
Float
Float4
Float
Float
Float
August 2006
ADSP-218xN
Table 12. Unused Pin Terminations (Continued)
I/O
3-State
(Z)2
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
Reset
State
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
IRQL1/PF6
I/O (Z)
I
IRQL0/PF5
I/O (Z)
I
IRQE/PF4
I/O (Z)
I
PWD
SCLK0
RFS0
DR0
TFS0
DT0
SCLK1
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EE
EBR
EBG
I
I/O
I/O
I
I/O
O
I/O
I/O
I
I/O
O
I
I
O
I
I
I
I
I
O
I
I
I
I
O
I
I
O
Pin Name1
D23–8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2–0 or
IAD15–13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
Hi-Z3 Caused By
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
EE
Rev. A |
Page 20 of 48 |
Unused Configuration
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive) or Program as Output, Set to
1, Let Float5
Input = High (Inactive) or Program as Output, Set to
1, Let Float5
Input = High (Inactive) or Program as Output, Set to
1, Let Float5
Input = High (Inactive) or Program as Output, Set to
1, Let Float5
High
Input = High or Low, Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low, Output = Float
High or Low
High or Low
High or Low
Float
Float
Float
Float
August 2006
ADSP-218xN
Table 12. Unused Pin Terminations (Continued)
Pin Name1
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
3-State
(Z)2
I
O
I
I
I
O
Reset
State
I
O
I
I
I
O
Hi-Z3 Caused By
Unused Configuration
Float
Float
Float
Float
Float
Float
1
CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.
All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
3
Hi-Z = High Impedance.
4
If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
5
If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts
and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.
2
Rev. A |
Page 21 of 48 |
August 2006
ADSP-218xN
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade (Commercial)
Min
Max
1.71
1.89
1.71
3.6
VIL = – 0.3
VIH = + 3.6
0
70
Parameter1
VDDINT
VDDEXT
VINPUT2
TAMB
1
2
B Grade (Industrial)
Min
Max
1.8
2.0
1.8
3.6
VIL = – 0.3
VIH = + 3.6
–40
+85
Unit
V
V
V
°C
Specifications subject to change without notice.
The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (max)
approximately equals VDDEXT (max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–A1, PF7–PF0) and inputonly pins (CLKIN, RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
Parameter1
VIH
VIL
VOH
Description
Hi-Level Input Voltage2, 3
Lo-Level Input Voltage2, 3
Hi-Level Output Voltage2, 4, 5
VOL
Lo-Level Output Voltage2, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
Supply Current (Idle)9
IDD
Supply Current (Dynamic)10
Test Conditions
@ VDDEXT = 1.71 V to 2.0 V,
VDDINT = max
@ VDDEXT = 2.1 V to 3.6 V,
VDDINT = max
@ VDDEXT ≤ 2.0 V,
VDDINT = min
@ VDDEXT ≥ 2.0 V,
VDDINT = min
@ VDDEXT = 1.71 V to 2.0 V,
IOH = – 0.5 mA
@ VDDEXT = 2.1 V to 2.9 V,
IOH = – 0.5 mA
@ VDDEXT = 3.0 V to 3.6 V,
IOH = – 0.5 mA
@ VDDEXT = 1.71 V to 3.6 V,
IOH = – 100 μA6
@ VDDEXT = 1.71 V to 3.6 V,
IOL = 2.0 mA
@ VDDINT = max,
VIN = 3.6 V
@ VDDINT = max,
VIN = 0 V
@ VDDEXT = max,
VIN = 3.6 V8
@ VDDEXT = max,
VIN = 0 V8
@ VDDINT = 1.8 V,
tCK = 12.5 ns,
TAMB = 25°C
@ VDDINT = 1.8 V,
tCK = 12.5 ns11,
TAMB = 25°C
Rev. A |
Page 22 of 48 |
August 2006
Min
1.25
Typ
Max
1.7
Unit
V
V
0.6
V
0.7
V
1.35
V
2.0
V
2.4
V
VDDEXT – 0.3
V
0.4
V
10
μA
10
μA
10
μA
10
μA
6
mA
25
mA
ADSP-218xN
Parameter1
IDD
Description
Supply Current (Idle)9
IDD
Supply Current (Dynamic)10
IDD
Supply Current (Power-Down)12
CI
Input Pin Capacitance3, 6
CO
Output Pin Capacitance6, 7, 12, 13
Test Conditions
@ VDDINT = 1.9 V,
tCK = 12.5 ns,
TAMB = 25°C
@ VDDINT = 1.9 V,
tCK = 12.5 ns11,
TAMB = 25°C
@ VDDINT = 1.8 V,
TAMB = 25°C
in Lowest Power Mode
@ VIN = 1.8 V,
fIN = 1.0 MHz,
TAMB = 25°C
@ VIN = 1.8 V,
fIN = 1.0 MHz,
TAMB = 25°C
Min
1
Typ
6.5
Max
Unit
mA
26
mA
100
μA
8
pF
8
pF
Specifications subject to change without notice.
Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.
5
Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.
8
0 V on BR.
9
Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type
6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.
12
See ADSP-218x DSP Hardware Reference for details.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
2
ABSOLUTE MAXIMUM RATINGS
Parameter
Internal Supply Voltage (VDDINT)1
External Supply Voltage (VDDEXT)
Input Voltage2
Output Voltage Swing3
Operating Temperature Range
Storage Temperature Range
Rating
–0.3 V to +2.2 V
–0.3 V to +4.0 V
–0.5 V to +4.0 V
–0.5 V to VDDEXT +0.5 V
–40°C to +85°C
–65°C to +150°C
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1,
A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2–0, BGH).
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-218xN features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. A |
Page 23 of 48 |
August 2006
ADSP-218xN
ESD DIODE PROTECTION
POWER DISSIPATION
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
To determine total power dissipation in a specific application,
the following equation should be applied for each output: C ⴛ
VDD2 ⴛ f
The bootstrap Schottky diode is connected between the core
and I/O power supplies, as shown in Figure 17. It protects the
ADSP-218xN processor from partially powering the I/O supply.
Including a Schottky diode will shorten the delay between the
supply ramps and thus prevent damage to the ESD diode protection circuitry. With this technique, if the core rail rises ahead
of the I/O rail, the Schottky diode pulls the I/O rail along with
the core rail.
DC INPUT
SOURCE
I/O VOLTAGE
REGULATOR
where:
C = load capacitance.
f = output switching frequency.
Example: In an application where external data memory is used
and no other outputs are active, power dissipation is calculated
as follows:
Assumptions:
• External data memory is accessed every cycle with 50% of
the address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
VDDEXT
• Each address and data pin has a 10 pF total load at the pin.
ADSP-218xN
CORE
VOLTAGE
REGULATOR
• Application operates at VDDEXT = 3.3 V and tCK = 30 ns.
VDDINT
Total Power Dissipation = PINT + (C ⴛVDDEXT2 ⴛ f)
P INT = internal power dissipation from Figure 22 on Page 27.
Figure 17. Dual Voltage Schottky Diode
(C ⴛ VDDEXT2 ⴛ f) is calculated for each output, as in the example in Table 13.
Table 13. Example Power Dissipation Calculation1
Parameters
Address
Data Output, WR
RD
CLKOUT, DMS
1
No. of Pins
7
9
1
2
× C (pF)
10
10
10
10
× VDDEXT2 (V)
3.32
3.32
3.32
3.32
Total power dissipation for this example is PINT + 45.72 mW.
Rev. A |
Page 24 of 48 |
August 2006
× f (MHz)
20.0
20.0
20.0
40.0
PD (mW)
15.25
19.59
2.18
8.70
45.72
ADSP-218xN
ENVIRONMENTAL CONDITIONS
REFERENCE
SIGNAL
Table 14. Thermal Resistance
Rating Description1
Thermal Resistance (Caseto-Ambient)
Thermal Resistance
(Junction-to-Ambient)
Thermal Resistance
(Junction-to-Case)
1
tMEASURED
Symbol
θCA
LQFP
(°C/W)
48
tENA
BGA
(°C/W)
63.3
θJA
50
70.7
θJC
2
7.4
VOH
(MEASURED)
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) + 0.5V
1.0V
OUTPUT
VOL
(MEASURED)
VOL
(MEASURED)
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Where the Ambient Temperature Rating (TAMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
Figure 20. Output Enable/Disable
Output Disable Time
TEST CONDITIONS
INPUT
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in Figure 20. The time is the interval from when a reference signal reaches a high or low voltage level to when the
output voltages have changed by 0.5 V from the measured output high or low voltage.
1.5V
2.0V
1.5V
0.8V
OUTPUT
Figure 18. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
The decay time, tDECAY, is dependent on the capacitive load, CL,
and the current load, iL, on the output pin. It can be approximated by the following equation:
IOL
TO
OUTPUT
PIN
tDIS
C L × 0.5V
t DECAY = -----------------------iL
from which
1.5V
t DIS = t MEASURED – t DECAY
50pF
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
IOH
Figure 19. Equivalent Loading for AC Measurements (Including All Fixtures)
Rev. A |
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 20. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Page 25 of 48 |
August 2006
ADSP-218xN
TIMING SPECIFICATIONS
80
V D D E X T = 3. 6 V @ – 4 0 ⴗ C
This section contains timing information for the DSP’s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently,
parameters cannot be added up meaningfully to derive
longer times.
Timing Notes
SOURCE CURRENT – mA
60
40
VDDEXT = 2.5V @ +85ⴗC
20
VDDEXT = 1.8V @ +85ⴗC
0
VDDEXT = 3.6V @ –40ⴗC
–20
V OL
–40
VDDEXT = 3.3V @ +25ⴗC
0
0.5
Frequency Dependency For Timing Specifications
tCK is defined as 0.5 tCKI. The ADSP-218xN uses an input clock
with a frequency equal to half the instruction rate. For example,
a 40 MHz input clock (which is equivalent to 25 ns) yields a
12.5 ns processor cycle (equivalent to 80 MHz). tCK values
within the range of 0.5 tCKI period should be substituted for all
relevant timing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25 ns
Output Drive Currents
Figure 21 shows typical I-V characteristics for the output drivers on the ADSP-218xN series.The curves represent the current
drive capability of the output drivers as a function of
output voltage.
Figure 23 shows the typical power-down supply current.
Capacitive Loading
Figure 24 and Figure 25 show the capacitive loading characteristics of the ADSP-218xN.
Page 26 of 48 |
1.0
1.5
2.0
2.5
SOURCE VOLTAGE – V
3.0
3.5
Figure 21. Typical Output Driver Characteristics
for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Rev. A |
1.8/[email protected]
@+85ⴗC
+85ⴗC
VVDDEXT
DDEXT==1.8/2.5V
–60
–80
Switching characteristics specify how the processor changes its
signals. Designers have no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics tell
what the processor will do in a given circumstance. Switching
characteristics can also be used to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
VDDEXT = 3.3V @ +25ⴗC
VOH
August 2006
4.0
ADSP-218xN
1000
POWER, INTERNAL 1, 2, 3
60
50
VD D I N
45
0V
= 2.
T
VD D I N
4 2 mW
40
35
34 m W
30
30 m W
=
V DD INT
38m W
VD D
= 1 .9
T
IN T
5 0 mW
V
45m W
1 .8 V
= 1 .7
CURRENT (LOG SCALE) – µA
55m W
55
PO WER (PIN T ) – mW
V DD = 2.0V
V DD = 1.9V
V DD = 1.8V
V DD = 1.7V
4 0 mW
1V
25
20
55
60
65
70
75
80
100
10
0
85
1 /tC K – MHz
1 4. 0
13.5m W
POWER (PID LE) – mW
1 3. 0
0V
= 2.
T
1 2. 0
V D D IN
11 .0
V D D I NT
10. 5 m W
10 .0
V DD IN T
9.5m W
9 .0
8 .5 mW
V DD
1 2 mW
9V
= 1.
10.5m W
= 1.8V
= 1.71 V
IN T
9m W
T = 85ⴗC
VDD = 0V TO 2.0V
7 .5 mW
7 .0
25
60
65
70
75
80
RISE TIME (0.4V–2.4V) – ns
6 .0
5 .0
55
85
1 /tC K – MHz
POWER, IDLE n MO DE S2
1 2.0
1 2. 0mW
10 .5mW
1 0.0
POWER (PID LEn ) – mW
9 .5 mW
8 .5m W
8.0
6.0
4 .2 mW
3 .8m W
3 .4m W
4.0
5.2 mW
4 .9 mW
4 .7 mW
4.3 mW
60
65
70
75
80
100
150
CL – pF
200
250
300
18
16
VALID OUTPUT DELAY OR HOLD – ns
4
50
0
85
NOTES
VALID FOR ALL TEM PERATURE GRADES.
1
POW ER REFLECTS DE VI CE OPE RATING WITH NO OUTPUT
LOADS.
3
10
Figure 24. Typical Output Rise Time vs. Load Capacitance (at Maximum
Ambient Operating Temperature)
1 /tC K – MHz
2
15
0
2.0
55
20
5
V D D C O RE = 1 . 9 V
V D D C OR E = 1 . 8 V
0.0
85
Figure 23. Typical Power-Down Current
30
8 .0
25
55
TEMPERATURE – °C
NOTES
1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER
MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE
ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO
INPUT LOADS.
POW ER, IDLE1 , 2, 4
1 5. 0
0
TYP ICAL P OW ER DI SS IPATION AT 1. 8V OR 1. 9V VD D INT AND
25 °C, EX CEPT WHERE SPE CI FI ED.
ID D M EASUREM ENT TAKE N WITH ALL INS TRUCTIONS
EXE CUTING FRO M I NT ERNAL M EM ORY. 50 % OF THE
INSTRUCTIO NS ARE M ULT IFUNCTION (TYP ES 1 , 4 , 5 , 1 2, 13,
14 ), 30 % ARE TY PE 2 AND TY PE 6, AND 2 0% ARE IDLE
INSTRUCTIO NS.
IDLE RE FE RS TO S TATE OF OP ERATION DURI NG EX ECUTI ON
OF I DLE INSTRUCTION. DE ASSE RTE D PINS ARE DRI VEN TO
EI THE R VDD O R GND.
Figure 22. Power vs. Frequency
14
12
10
8
6
4
2
NOMINAL
–2
–4
–6
0
50
100
150
200
250
CL – pF
Figure 25. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at
Maximum Ambient Operating Temperature)
Rev. A |
Page 27 of 48 |
August 2006
ADSP-218xN
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter
Timing Requirements:
CLKIN Period
tCKI
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
Switching Characteristics:
tCKL
CLKOUT Width Low
tCKH
CLKOUT Width High
CLKIN High to CLKOUT High
tCKOH
Control Signals Timing Requirements:
tRSP
RESET Width Low
tMS
Mode Setup before RESET High
tMH
Mode Hold after RESET High
1
Min
Max
Unit
25
8
8
40
ns
ns
ns
0.5tCK – 3
0.5tCK – 3
0
5tCK1
7
5
8
ns
ns
ns
ns
ns
ns
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator
start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
MODE A D
tMS
tMH
RESET
tRSP
Figure 26. Clock Signals and Reset
Rev. A |
Page 28 of 48 |
August 2006
ADSP-218xN
Interrupts and Flags
Table 16. Interrupts and Flags
Parameter
Timing Requirements:
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
tIFS
tIFH
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
Min
Max
0.25tCK + 10
0.25tCK
ns
ns
0.5tCK – 5
ns
ns
0.5tCK + 4
1
Unit
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on
interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 27. Interrupts and Flags
Rev. A |
Page 29 of 48 |
August 2006
ADSP-218xN
Bus Request–Bus Grant
Table 17. Bus Request–Bus Grant
Parameter
Timing Requirements:
BR Hold after CLKOUT High1
tBH
tBS
BR Setup before CLKOUT Low1
Switching Characteristics:
tSD
CLKOUT High to xMS, RD, WR Disable2
tSDB
xMS, RD, WR Disable to BG Low
tSE
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
tSEC
tSDBH
xMS, RD, WR Disable to BGH Low3
tSEH
BGH High to xMS, RD, WR Enable3
Min
Max
0.25tCK + 2
0.25tCK + 8
ns
ns
0.25tCK + 8
0
0
0.25tCK – 3
0
0
1
Unit
ns
ns
ns
ns
ns
ns
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
xMS = PMS, DMS, CMS, IOMS, BMS.
3
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
2
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
CMS, WR,
IOMS
tSD
tSEC
BG
tSDB
BGH
tSE
tSDBH
tSEH
Figure 28. Bus Request–Bus Grant
Rev. A |
Page 30 of 48 |
August 2006
ADSP-218xN
Memory Read
Table 18. Memory Read
Parameter
Timing Requirements:
RD Low to Data Valid1
tRDD
tAA
A13–0, xMS to Data Valid2
tRDH
Data Hold from RD High
Switching Characteristics:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
A13–0, xMS Setup before RD Low
tASR
tRDA
A13–0, xMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
1
2
Min
Max
Unit
0.5tCK – 5 + w
0.75tCK – 6 + w
ns
ns
ns
0
0.5tCK – 3 + w
0.25tCK – 2
0.25tCK – 3
0.25tCK – 3
0.5tCK – 3
w = wait states 3 tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
DATA LINES2
tAA
tRDD
tRDH
WR
1ADDRESS LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)
I/O SPACE: A10–0
EXTERNAL PM AND DM: A13–0
2DATA LINES FOR ACCESSES ARE:
BDMA: D15–8
I/O SPACE: D23–8
EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
Figure 29. Memory Read
Rev. A |
Page 31 of 48 |
August 2006
0.25tCK + 4
ns
ns
ns
ns
ns
ADSP-218xN
Memory Write
Table 19. Memory Write
Parameter
Switching Characteristics:
Data Setup before WR High1
tDW
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A13–0, xMS Setup before WR Low2
tDDR
Data Disable before WR or RD Low
CLKOUT High to WR Low
tCWR
tAW
A13–0, xMS Setup before WR Deasserted
tWRA
A13–0, xMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
1
2
Min
Max
0.5tCK– 4 + w
0.25tCK – 1
0.5tCK – 3 + w
0
0.25tCK – 3
0.25tCK – 3
0.25tCK – 2
0.75tCK – 5 + w
0.25tCK – 1
0.5tCK – 3
w = wait states 3 tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
DATA LINES2
tDW
tWDE
RD
1ADDRESS LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)
I/O SPACE: A10–0
EXTERNAL PM AND DM: A13–0
2DATA LINES FOR ACCESSES ARE:
BDMA: D15–8
I/O SPACE: D23–8
EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
Figure 30. Memory Write
Rev. A |
Page 32 of 48 |
August 2006
tDDR
0.25tCK + 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-218xN
Serial Ports
Table 20. Serial Ports
Parameter
Timing Requirements:
SCLK Period
tSCK
tSCS
DR/TFS/RFS Setup Before SCLK Low
tSCH
DR/TFS/RFS Hold After SCLK Low
tSCP
SCLKIN Width
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
tSCDE
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
tTDV
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
t CC
Min
30
4
7
12
7
7
0
0
7
7
7
tS C K
tS CP
t SC S
DR
TFSIN
RFSIN
tSC H
tSC P
tRD
tR H
RFSO UT
TFSO UT
tS C DD
t SC D V
tSC D H
tS CD E
DT
tTD E
t TD V
TFSO UT
A LTER N A TE
FRA M E
M OD E
tR DV
RFS OU T
MU LTIC H A NN E L
M ODE ,
( MFD = 0 )
TFSIN
tTD E
tTD V
ALTE R NA TE
FR A ME
MO DE
0.25tCK + 6
0
tCC
tR DV
RFSIN
MU LTIC H A NN E L
M ODE ,
FR A ME DE LA Y 0
( MFD = 0 )
Figure 31. Serial Ports
Rev. A |
Page 33 of 48 |
August 2006
Unit
ns
ns
ns
ns
0.25tCK
0
SCLK
FR A ME DE LA Y 0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-218xN
IDMA Address Latch
Table 21. IDMA Address Latch
Parameter
Timing Requirements:
Duration of Address Latch1, 2
tIALP
tIASU
IAD15–0 Address Setup Before Address Latch End2
tIAH
IAD15–0 Address Hold After Address Latch End2
tIKA
IACK Low before Start of Address Latch2, 3
tIALS
Start of Write or Read After Address Latch End2, 3
tIALD
Address Latch Start After Address Latch End1, 2
Min
10
5
3
0
3
2
1
Start of Address Latch = IS Low and IAL High.
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
2
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIASU
tIAH
IRD OR IWR
Figure 32. IDMA Address Latch
Rev. A |
Page 34 of 48 |
August 2006
tIAH
tIALS
Max
Unit
ns
ns
ns
ns
ns
ns
ADSP-218xN
IDMA Write, Short Write Cycle
Table 22. IDMA Write, Short Write Cycle
Parameter
Timing Requirements:
IACK Low Before Start of Write1
tIKW
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup Before End of Write2, 3, 4
tIDH
IAD15–0 Data Hold After End of Write2, 3, 4
Switching Characteristic:
tIKHW
Start of Write to IACK High
Min
0
10
3
2
Start of Write = IS Low and IWR Low.
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
2
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
tIDH
DATA
Figure 33. IDMA Write, Short Write Cycle
Rev. A |
Page 35 of 48 |
August 2006
Unit
ns
ns
ns
ns
10
1
IAD15–0
Max
ns
ADSP-218xN
IDMA Write, Long Write Cycle
Table 23. IDMA Write, Long Write Cycle
Parameter
Timing Requirements:
IACK Low Before Start of Write1
tIKW
tIKSU
IAD15–0 Data Setup Before End of Write2, 3, 4
tIKH
IAD15–0 Data Hold After End of Write2, 3, 4
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW
Start of Write to IACK High
Min
Max
0
0.5tCK + 5
0
ns
ns
ns
1.5tCK
10
1
Start of Write = IS Low and IWR Low.
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
2
tIK W
IACK
tIKH W
tIK LW
IS
IWR
tIKSU
tIK H
DATA
IAD15–0
Figure 34. IDMA Write, Long Write Cycle
Rev. A |
Page 36 of 48 |
August 2006
Unit
ns
ns
ADSP-218xN
IDMA Read, Long Read Cycle
Table 24. IDMA Read, Long Read Cycle
Parameter
Timing Requirements:
IACK Low Before Start of Read1
tIKR
tIRK
End of read After IACK Low2
Switching Characteristics:
tIKHR
IACK High After Start of Read1
tIKDS
IAD15–0 Data Setup Before IACK Low
tIKDH
IAD15 –0 Data Hold After End of Read2
IAD15–0 Data Disabled After End of Read2
tIKDD
tIRDE
IAD15–0 Previous Data Enabled After Start of Read
tIRDV
IAD15–0 Previous Data Valid After Start of Read
tIRDH1
IAD15–0 Previous Data Hold After Start of Read (DM/PM1)3
tIRDH2
IAD15–0 Previous Data Hold After Start of Read (PM2)4
Min
Max
0
2
ns
ns
10
0.5tCK – 3
0
10
0
11
2tCK – 5
tCK – 5
1
Start of Read = IS Low and IRD Low.
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
2
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
READ
DATA
tIRDV
tIKDD
tIRDH1 OR tIRDH2
Figure 35. IDMA Read, Long Read Cycle
Rev. A |
Page 37 of 48 |
August 2006
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-218xN
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter1, 2
Timing Requirements:
IACK Low Before Start of Read3
tIKR
tIRP1
Duration of Read (DM/PM1)4
tIRP2
Duration of Read (PM2)5
Switching Characteristics:
tIKHR
IACK High After Start of Read3
tIKDH
IAD15–0 Data Hold After End of Read6
IAD15–0 Data Disabled After End of Read6
tIKDD
tIRDE
IAD15–0 Previous Data Enabled After Start of Read
tIRDV
IAD15–0 Previous Data Valid After Start of Read
Min
Max
Unit
0
10
10
2tCK – 5
tCK – 5
ns
ns
ns
10
0
10
0
10
1
ns
ns
ns
ns
ns
Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is
disabled by default upon reset.
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
Second half of PM Read.
6
End of Read = IS High or IRD High.
2
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tIRDV
tIKDD
Figure 36. IDMA Read, Short Read Cycle
Rev. A |
Page 38 of 48 |
August 2006
ADSP-218xN
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter1
Timing Requirements:
IACK Low Before Start of Read2
tIKR
tIRP
Duration of Read3
Switching Characteristics:
tIKHR
IACK High After Start of Read2
tIKDH
IAD15–0 Previous Data Hold After End of Read3
tIKDD
IAD15–0 Previous Data Disabled After End of Read3
IAD15–0 Previous Data Enabled After Start of Read
tIRDE
tIRDV
IAD15–0 Previous Data Valid After Start of Read
Min
Max
0
10
ns
ns
10
0
10
0
10
1
Unit
ns
ns
ns
ns
ns
Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register
or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
IA CK
t IK R
t IK H R
IS
tIR P
IRD
t IK D H
t IR D E
PR E V IO U S
D A TA
IA D 15–0
t IR D V
tIK D D
L EG EN D :
IM PL IES TH A T IS A N D IR D C A N B E
HE LD IN D E FIN ITE LY B Y H O S T
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
Rev. A |
Page 39 of 48 |
August 2006
ADSP-218xN
LQFP PACKAGE PINOUT
77 D17
76 D16
78 D18
79 D19
80 GND
81 D20
83 D22
82 D21
84 D23
87 FL0
86 FL1
88 PF3 [MODE D]
89 PF2 [MODE C]
90 VDDEXT
92 GND
91 PWD
94 PF0 [MODE A]
93 PF1 [MODE B]
95 BGH
96 PWDACK
97 A0
98 A1/IAD0
99 A2/IAD1
100 A3/IAD2
The LQFP package pinout is shown Figure 38 and in Table 27.
Pin names in bold text in the table replace the plain-text-named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
85 FL2
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default, upon reset.
75 D15
A4/IAD3
1
A5/IAD4
2
GND
3
73 D13
A6/IAD5
4
72 D12
A7/IAD6
5
71 GND
A8/IAD7
6
70 D11
A9/IAD8
7
69 D10
A10/IAD9
8
68 D9
A11/IAD10
9
67 VDDEXT
PIN 1
IDENTIFIER
74 D14
66 GND
A12/IAD11 10
65 D8
A13/IAD12 11
GND 12
64 D7/IWR
ADSP-218xN
CLKIN 13
63 D6/IRD
TOP VIEW
(Not to Scale)
XTAL 14
62 D5/IAL
61 D4/IS
VDDEXT 15
60 GND
59 VDD INT
CLKOUT 16
GND 17
58 D3/IACK
VDDINT 18
Figure 38. 100-Lead LQFP Pin Configuration
Rev. A |
Page 40 of 48 |
August 2006
EINT 50
ELIN 49
ELOUT 48
ECLK 47
EE 46
EMS 45
RESET 44
ERESET 43
GND 41
SCLK1 42
DR1/FI 40
RFS1/IRQ0 39
VDDEXT 36
DT1/FO 37
TFS1/IRQ1 38
DR0 34
SCLK0 35
51 EBR
RFS0 33
CMS 25
TFS0 32
53 EBG
52 BR
DT0 31
IOMS 24
IRQ2+PF7 30
54 BG
PMS 23
IRQL1+PF6 29
55 D0/IAD13
DMS 22
GND 28
56 D1/IAD14
BMS 21
IRQE+PF4 26
57 D2/IAD15
RD 20
IRQL0+PF5 27
WR 19
ADSP-218xN
Table 27. LQFP Package Pinout
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Table 27. LQFP Package Pinout (Continued)
Pin Name
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDDEXT
CLKOUT
GND
VDDINT
WR
RD
BMS
DMS
PMS
IOMS
CMS
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
VDDEXT
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Rev. A |
Page 41 of 48 |
August 2006
Pin Name
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
VDDINT
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDDEXT
D9
D10
D11
GND
D12
D13
D14
D15
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [Mode D]
PF2 [Mode C]
VDDEXT
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
ADSP-218xN
BGA PACKAGE PINOUT
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default upon reset.
The BGA package pinout is shown in Figure 39 and in Table 28.
Pin names in bold text in the table replace the plain text named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
1
12
11
10
9
8
7
6
5
4
3
2
G ND
G ND
D22
NC
NC
NC
G ND
NC
A0
G ND
A1/IAD0
A 2/IAD1
A
D16
D17
D18
D20
D23
VDDEXT
G ND
NC
NC
G ND
A3/IAD2
A 4/IAD3
B
D14
NC
D15
D19
D21
VDDEXT
PWD
PW DACK
C
G ND
NC
D12
D13
NC
PF 2
[MO DE C]
D10
G ND
G ND
G ND
PF 3
[MO DE D]
D9
NC
D8
D11
D7/IW R
NC
NC
FL1
A 11/IAD10
D4/IS
NC
NC
D5/IAL
D6/IR D
NC
NC
NC
A10/IAD9
G ND
NC
G ND
NC
G ND
D3/IACK
D 2/IAD15
T FS0
DT 0
V D D IN T
G ND
G ND
G ND
V D D IN T
V D D IN T
D1/IAD14
BG
RFS 1/IRQ 0
D 0/IAD13
SCL K0
VDDEXT
VDDEXT
NC
EB G
BR
E BR
ERES E T
SCL K1
TF S 1/IRQ1
RF S 0
DMS
BMS
NC
E LIN
RES ET
G ND
DR 0
P MS
G ND
IOMS
E MS
NC
G ND
DR1/FI
DT 1/FO
G ND
CMS
EINT
EC LK
E LO UT
EE
VDDEXT
PF 1
[MO DE B]
FL 2
A7/IAD6
A5/IAD4
A9/IAD8
BG H
PF 0
[MO DE A]
FL 0
Figure 39. 144-Ball BGA Package Pinout (Bottom View)
Rev. A |
Page 42 of 48 |
August 2006
RD
NC
A8/IAD7
A 12/IAD11
IRQ L1 + P F6
NC
A 6/IAD5
WR
VDDEXT
NC
VDDINT
NC
NC
NC
D
VDDEXT
E
A13/IAD12
F
X TA L
G
CLKIN
H
CLK OUT
J
NC
IR QE + PF 4
IRQ 2 + PF7 IRQ L0 + P F5
K
L
M
ADSP-218xN
Table 28. BGA Package Pinout
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
E01
Table 28. BGA Package Pinout
(Continued)
Pin Name
A2/IAD1
A1/IAD0
GND
A0
NC
GND
NC
NC
NC
D22
GND
GND
A4/IAD3
A3/IAD2
GND
NC
NC
GND
VDDEXT
D23
D20
D18
D17
D16
PWDACK
A6/IAD5
RD
A5/IAD4
A7/IAD6
PWD
VDDEXT
D21
D19
D15
NC
D14
NC
WR
NC
BGH
A9/IAD8
PF1 [MODE B]
PF2 [MODE C]
NC
D13
D12
NC
GND
VDDEXT
Ball No.
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
J01
J02
Rev. A |
Page 43 of 48 |
August 2006
Pin Name
VDDEXT
A8/IAD7
FL0
PF0 [MODE A]
FL2
PF3 [MODE D]
GND
GND
VDDEXT
GND
D10
A13/IAD12
NC
A12/IAD11
A11/IAD10
FL1
NC
NC
D7/IWR
D11
D8
NC
D9
XTAL
NC
GND
A10/IAD9
NC
NC
NC
D6/IRD
D5/IAL
NC
NC
D4/IS
CLKIN
GND
GND
GND
VDDINT
DT0
TFS0
D2/IAD15
D3/IACK
GND
NC
GND
CLKOUT
VDDINT
ADSP-218xN
Table 28. BGA Package Pinout
(Continued)
Ball No.
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
Pin Name
NC
VDDEXT
VDDEXT
SCLK0
D0/IAD13
RFS1/IRQ0
BG
D1/IAD14
VDDINT
VDDINT
NC
NC
NC
BMS
DMS
RFS0
TFS1/IRQ1
SCLK1
ERESET
EBR
BR
EBG
IRQE + PF4
NC
IRQL1 + PF6
IOMS
GND
PMS
DR0
GND
RESET
ELIN
ELOUT
EINT
IRQL0 + PF5
IRQL2 + PF7
NC
CMS
GND
DT1/FO
DR1/FI
GND
NC
EMS
EE
ECLK
Rev. A |
Page 44 of 48 |
August 2006
ADSP-218xN
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
10.10
10.00 SQ
9.90
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
BALL A1
INDICATOR
8.80
BSC
SQ
0.80
BSC
(BALL
PITCH)
BOTTOM VIEW
TOP VIEW
DETAIL A
1.40
MAX
DETAIL A
1.11
0.85
0.25
MIN
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY
WITH JEDEC STANDARD MO-205-AC.
2. ACTUAL POSTION OF THE BALL GRID IS WITHIN
0.15 OF ITS IDEAL POSTION RELATIVE TO THE
PACKAGE EDGES.
3. CENTER DIMENSIONS ARE NOMINAL.
4. DIMENSION IN DRAWING IS FOR PB-FREE BALL.
PB-BEARING BALL DIMENSION IS 0.45/0.50/0.55.
0.50
0.45
0.40
(BALL DIAMETER,
SEE NOTE 4)
SEATING
PLANE
0.12 MAX (BALL
COPLANARITY)
Figure 40. 144-Ball BGA [CSP_BGA] (BC-144-6)
16.00 BSC SQ
1.60 MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
12°
TYP
76
75
SEATING
PLANE
12.00
REF
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
0.08
MAX LEAD
COPLANARITY
VIEW A
51
50
25
26
0.27
0.22
0.17
0.50 BSC
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
Figure 41. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1)
Rev. A |
Page 45 of 48 |
August 2006
ADSP-218xN
SURFACE MOUNT DESIGN
Table 29 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 29. BGA Data for Use with Surface Mount Design
Ball Attach
Package
Type
144-Ball BGA Solder Mask
(BC-144-6)
Defined
Solder Mask
Opening
0.40 mm
diameter
Ball Pad Size
0.50 mm
diameter
Rev. A |
Page 46 of 48 |
August 2006
ADSP-218xN
ORDERING GUIDE
Model
ADSP-2184NBCA-320
ADSP-2184NBST-320
ADSP-2184NKCA-320
ADSP-2184NKST-320
ADSP-2184NKSTZ-3202
ADSP-2185NBCA-320
ADSP-2185NBST-320
ADSP-2185NBSTZ-3202
ADSP-2185NKCA-320
ADSP-2185NKST-320
ADSP-2185NKSTZ-3202
ADSP-2186NBCA-320
ADSP-2186NBST-320
ADSP-2186NBSTZ-3202
ADSP-2186NKCA-320
ADSP-2186NKST-320
ADSP-2186NKSTZ-3202
ADSP-2187NBCA-320
ADSP-2187NBST-320
ADSP-2187NBSTZ-3202
ADSP-2187NKCA-320
ADSP-2187NKST-320
ADSP-2187NKSTZ-3202
ADSP-2188NBCA-320
ADSP-2188NBST-320
ADSP-2188NBSTZ-3202
ADSP-2188NKCA-320
ADSP-2188NKCAZ-3202
ADSP-2188NKST-320
ADSP-2188NKSTZ-3202
ADSP-2189NBCA-320
ADSP-2189NBCAZ-3202
ADSP-2189NBST-320
ADSP-2189NBSTZ-3202
ADSP-2189NKCA-320
ADSP-2189NKCAZ-3202
ADSP-2189NKST-320
ADSP-2189NKSTZ-3202
1
2
Temperature
Range1
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Instruction
Rate (MHz)
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
Package
Description
144-Ball CSP_BGA
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
144-Ball CSP_BGA
144-Ball CSP_BGA
100-Lead LQFP
100-Lead LQFP
Ranges shown represent ambient temperature.
Z = Pb-free part.
Rev. A |
Page 47 of 48 |
August 2006
Package
Option
BC-144-6
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
ST-100-1
ST-100-1
BC-144-6
BC-144-6
ST-100-1
ST-100-1
BC-144-6
BC-144-6
ST-100-1
ST-100-1
BC-144-6
BC-144-6
ST-100-1
ST-100-1
ADSP-218xN
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02666-0-8/06(A)
Rev. A |
Page 48 of 48 |
August 2006