YMF753 AC’97 Revision2.2 Audio CODEC with Digital Audio I/F OVERVIEW YMF753 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio CODEC ’97” component specification (Revision 2.2). Different from former AC’97, YMF753 supports new features like SPDIF OUT and Zoomed Video Port. Without using a digital controller, these new features can be enhanced in the AC’97 sound system that has an ICH controller built-in chipset. Low power consumption is supported not only in the normal mode but can be controlled in the power-down mode. FEATURES • AC’97 Revision 2.2 Compliant • Exceeds PC99 / PC2001 Analog Performance Requirement (Mobile PC Audio Performance Compliant when analog low power supply is used.) • Analog Inputs : - 4 Stereo Inputs: LINE, CD, VIDEO, AUX - 2 Monaural Inputs: Speakerphone and PC BEEP Inputs - 2 Independent Microphone Inputs • PC BEEP can directly output to Line Out • Internal +20dB amplifier circuitry for microphone • Analog Outputs : Stereo LINE Output, True LINE Level and Monaural Output • Supports Zoomed Video Port • Supports Consumer IEC958 Output Port (SPDIF OUT) • SPDIF Output for AC’97 Revision 1.0 Compliant • Different audio data from AC-Link can be output to SPDIF and Line Out • Supports 3D Enhancement (Wide Stereo), and Bass / Treble control • Multiple CODEC Capability • Programmable Power Down Mode • Supports EAPD (External Amplifier Power Down) • Power Supplies : Analog 4.3V to 5.0V, Digital 3.3V or 5.0V • 48-Pin SQFP Package (YMF753-S) YAMAHA CORPORATION YMF753 CATALOG Decembe 3, 1998 CATALOG No.:LSI-4MF753A2 March 6, 2001 18 19 20 21 22 23 24 CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R 16 VIDEO_L CD_L 15 AUX_R 17 14 AUX_L VIDEO_R 13 PHONE ZV_BCK / DIT EAPD (DIT) EXT24M / ID1# Reserved / ID0# ZV_SIN / Reserved ZV_LR / DIT AVss2 LNLVL_OUT_R MSEL LNLVL_OUT_L AVdd2 MONO_OUT 48 47 46 45 44 43 42 41 40 39 38 37 YMF753 PIN CONFIGURATION DVdd1 1 36 LINE_OUT_R XTL_IN 2 35 LINE_OUT_L XTL_OUT 3 34 CAP6 DVss1 4 33 CAP5 SDATA_OUT 5 32 CAP4 BIT_CLK 6 31 CAP3 DVss2 7 30 CAP2 SDATA_IN 8 29 CAP1 DVdd2 9 28 Vrefout SYNC 10 27 Vref RESET# 11 26 AVss1 PC_BEEP 12 25 AVdd1 48-Pin SQFP Top View 2 March 6, 2001 YMF753 PIN DESCRIPTION No. Name I/O Function Digital power supply (Typ. +3.3V / +5.0V) 1 DVdd1 - Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd2. 2 XTL_IN I 24.576MHz Clock Input 3 XTL_OUT O 24.576MHz Clock Output 4 DVss1 - Digital ground. Connect this pin to DVss2. 5 SDATA_OUT I AC’97 Serial Input Stream 6 BIT_CLK I/O 7 DVss2 - Digital ground. Connect this pin to DVss1. 8 SDATA_IN O AC’97 Serial Output Stream 9 DVdd2 - AC’97 Bit Clock As an output pin at the primary codec where CODEC ID=00. As an input pin at the secondary codec where CODEC ID=01,10,11. Digital power supply (Typ. +3.3V / +5.0V) Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd1. 10 SYNC I SYNC Input (Fixed at 48kHz) 11 RESET# I Hardware Reset 12 PC_BEEP AI 13 PHONE AI Telephony Input 14 AUX_L AI AUX Input Left Channel 15 AUX_R AI AUX Input Right Channel 16 VIDEO_L AI Video Audio Input Left Channel 17 VIDEO_R AI Video Audio Input Right Channel 18 CD_L AI CD Audio Input Left Channel 19 CD_GND AI 20 CD_R AI CD Audio Input Right Channel 21 MIC1 AI Microphone Input 1 22 MIC2 AI Microphone Input 2 23 LINE_IN_L AI Line Input Left Channel 24 LINE_IN_R AI PC Speaker Beep CD Audio Analog Ground Connect this pin to CD Ground or Analog Ground. Line Input Right Channel Analog Power Supply (Typ. +4.3V to +5.0V) 25 AVdd1 - Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd2. 26 AVss1 - 27 Vref AO Analog ground. Connect this pin to AVss2. Analog Reference Voltage Connect to the analog ground with 0.1mF and 22mF capacitors. Analog Reference Voltage Output 28 Vrefout AO Connect to the analog ground with 0.1mF and 22mF capacitors when it is used to the external circuit. 3 March 6, 2001 YMF753 No. Name I/O Function 29 CAP1 A Connect to the analog ground with a 2200pF capacitor. 30 CAP2 A Connect to the analog ground with a 0.015mF capacitor. 31 CAP3 A Connect to the analog ground with a 0.01mF capacitor. 32 CAP4 A Connect to the analog ground with a 2200pF capacitor. 33 CAP5 A Connect to the analog ground with a 0.015mF capacitor. 34 CAP6 A Connect to the analog ground with a 0.01mF capacitor. 35 LINE_OUT_L AO Line Output Left Channel 36 LINE_OUT_R AO Line Output Right Channel 37 MONO_OUT AO Monaural Output 38 AVdd2 - Analog power supply (Typ. +4.3V to +5.0V) Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd1. 39 LNLVL_OUT_L AO 40 MSEL I 41 LNLVL_OUT_R AO 42 AVss2 - True LINE Level Output Left Channel Mode Select, which changes the pin function of No.43 – 46, 48. True LINE Level Output Right Channel Analog ground. Connect to AVss1. The function is selected at 62h TX-7 bit. 47 EAPD (DIT) O TX-7=“0”, External Amplifier Power Down TX-7=“1”, Digital Audio Interface Output (48kHz) 1. MSEL= “High” (Connect to analog power supply.) No. Name I/O Function 43 ZV_LR I- Zoomed Video Port L/R clock 44 ZV_SIN I- Zoomed Video Port serial data 45 Reserved - Do not connect externally. 46 EXT24M O 24.576MHz clock output 48 ZV_BCK I- Zoomed Video Port bit clock 2. MSEL= “Low” (Connect to analog ground.) No. Name I/O Function 43 DIT O Digital Audio Interface Output (48kHz) 44 Reserved - Do not connect externally. 45 CODEC ID0# I+ CODEC ID 46 CODEC ID1# I+ CODEC ID 48 DIT O Digital Audio Interface Output (48kHz) Note) AI: Analog Input Pin, AO: Analog Output Pin, I+: Input Pin with a Pull-up resistor, I-: Input Pin with a Pull-down resistor 4 March 6, 2001 YMF753 AVdd(2) AVss(2) CAP1 CAP2 CAP3 CAP4 CAP5 CAP6 Vrefout Vref DVss(2) DVdd(2) BLOCK DIAGRAM MS A/D RESET# A/D digital PCM L 32step PCM R 32step I/F Volume Control SDATA_IN ZV L 32step ZV R 32step UDS TX-7 PHONE 32step AUX 32step VIDEO 32step CD 32step LINE 32step MIC 32step PC Beep 16step ID0# Reserved / ID0# MUX ID1# ZV_LR / DIT BUF CD Left DIT EAPD (DIT) EXT24M / ID1# ZV_SIN / Reserved DIT ZV_LR ZV_SIN ZV_BCK ZV Port EXT24M ZV_BCK / DIT Monaural 32step PC_BEEP RESET# Timing Generator XTL_OUT MONO_OUT MIX MSEL XTL_IN LINE_IN_R LINE_IN_L CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE CD Right LPBK SPSA SDATA_OUT MIC1 MIC2 D/A BIT_CLK Record R 16step Record L 16step D/A AC’97 ID0/1# SYNC 0dB/ +20dB MUX Power down Control VREF Left 3D tone Right Master L 32step Master R 32step LINE_OUT_L LINE_OUT_R LNLVL_OUT_L POP LNLVL_OUT_R 5 March 6, 2001 YMF753 MIXER REGISTERS NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset “0” “0” “0” “0” “0” “1” “0” “0” “0” “0” “0” “0” 02h Master vol. Mute - - - 04h LNLVL vol. - - - - - - - - - - - - - - - - - - - - - - 06h Master vol. Mono Mute “0” “0” “0” “0” ML5-0 - - - 8000h - - - MM5-0 8000h Master tone - - - - - 0Ah PC_BEEP vol. Mute - - - - - - - - - - 0Ch Phone vol. Mute - - - - - - - - - - GN4-0 8008h 0Eh Mic vol. Mute - - - - - - - - 20dB - GN4-0 8008h 10h Line in vol. Mute - - GL4-0 - - - GR4-0 8808h 12h CD vol. Mute - - GL4-0 - - - GR4-0 8808h 14h Video vol. Mute - - GL4-0 - - - GR4-0 8808h 16h Aux vol. Mute - - GL4-0 - - - GR4-0 8808h 18h PCM out vol. Mute - - GL4-0 - - - GR4-0 8808h 1Ah Record Select - - - - - - - - 1Ch Record Gain Mute - - - - - - - 20h General Purpose POP - 3D - - - - - - - - 0000h 22h 3D Control - - - - - - - - - - - - 0000h 26h Power Down EAPD - - - - - - - - SL2-0 GL3-0 - - MIX WD3-1 MS LPBK - PR5 PR4 PR3 PR2 PR1 PR0 ID0 - - REV1-0 - - - AMAP LDAC SDAC CDAC - 0000h 08h 28h Extended Audio ID ID1 BA2-0 MR5-0 0040h - TR2-0 PV3-0 SR2-0 SPDIF - - xxx4h - SPDIF - - 0400h DIT Control 1 V - 62h Vendor Function * * 64h ZV vol. 66h DIT Control 2 - - - - - - - * * * TX-3 * 68h 3D Mode Select - - - - WM1-0 - - - - - - - - 7Ch Vendor ID 1 “0” “1” “0” “1” “1” “0” “0” “1” “0” “1” “0” “0” “1” 7Eh Vendor ID 2 “0” “1” “0” “0” “1” “0” “0” “0” “0” “0” “0” “0” “0” Mute MSEL SPSR1-0 * * SPSA1-0 - 3Ah - - 8000h REF ANL DAC ADC 000xh - - 0000h 0000h GR3-0 - - - - 2Ah Ext Audio Stat/Ctrl SPCV 0707h GL CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD# PRO 2000h * - * * * GL4-0 * * * ZEN ZAC * TX-7 EXEN - * * GR4-0 0224h x808h TX-8 DMU UDS 3AWE 0040h - - 0C00h “1” “0” “1” 594Dh “0” “1” “1” 4803h Note) The * bits of 62h and 66h should not be changed from the default value. Do not access to 5Ah and 60h because they are LSI test registers. 00h : Reset (Read/Write reset, Default: 0040h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 “0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “0” “0” “0” “0” “0” “0” When any value is written to this register, all registers except for the lower 4 bits of 26h:Power Down are reset to the default value. 6 March 6, 2001 YMF753 02h : Master Volume (Read/Write, Default: 8000h) D15 D14 Mute - D13 D12 D11 D10 D9 D8 D7 D6 - - ML5-0 D5 D4 D3 D2 D1 D0 MR5-0 Mute..............Setting this bit to “1” mutes both left and right channels of the line output. ML5-0...........These bits determine the volume level of the line output left channel by 1.5dB step. The volume range is from 0dB to -46.5dB. When all bits are set to “0”, volume is maximum (0dB) and when they are set to “011111b”, volume is minimum (-46.5dB). And when ML5 bit is set to “1”, the volume level is minimum (-46.5dB), then their status become “011111b”. MR5-0...........These bits determine the volume level of the line output right channel by 1.5dB step. Setting to them is the same as the upper ML5-0 bits. 04h : LNLVL Volume (Read/Write, Default: 0000h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - - - - - - - D5 D4 D3 D2 D1 D0 Though the register can be written any value, it does not function. 0000h is always read out. 06h : Master Volume Mono (Read/Write, Default: 8000h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Mute - - - - - - - - - MM5-0 Mute..............Setting this bit to “1” mutes the monaural output. MM5-0..........These bits determine the volume level of the monaural output by 1.5dB step. The volume range is from 0dB to -46.5dB. When all bits are set to “0”, volume is maximum (0dB) and when they are set to “011111b”, volume is minimum (-46.5dB). And when MM5 bit is set to “1”, the volume level is minimum (-46.5dB), then their status become “011111b” 08h : Master Tone (Read/Write, Default: 0707h) D15 D14 D13 D12 D11 - - - - - D10 D9 BA2-0 D8 D7 D6 D5 D4 D3 - - - - - D2 D1 D0 TR2-0 BA2-0 ...........These bits determine the bass level by 1.5dB step. The tone range is from 0dB to +10.5dB. When all bits are set to “0”, tone is maximum (+10.5dB) and when all bits are set to “1”, tone is minimum (0dB) TR2-0............These bits determine the treble level by 1.5dB step. Setting to them is the same as the upper BA2-0. 7 March 6, 2001 YMF753 0Ah : PC_BEEP Volume (Read/Write, Default: 0000h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Mute - - - - - - - - - - D4 D3 D2 D1 PV3-0 D0 - Mute..............Setting this bit to “1” mutes the PC_BEEP. PV3-0............These bits determine the volume level of the PC_BEEP by 3.0dB step. The volume range is from 0dB to -45dB. When all bits are set to “0”, volume is maximum (0dB) and when all bits are set to “1”, volume is minimum (-45dB). 0Ch : Phone Volume (Read/Write, Default: 8008h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Mute - - - - - - - - - - D4 D3 D2 D1 D0 GN4-0 Mute..............Setting this bit to “1” mutes the Phone. GN4-0 ...........These bits determine the volume level of the Phone by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all bits are set to “1”, volume is minimum (-34.5dB). 0Eh : Mic Volume (Read/Write, Default: 8008h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Mute - - - - - - - - 20dB - D4 D3 D2 D1 D0 GN4-0 Mute..............Setting this bit to “1” mutes the Microphone. 20dB .............Setting this bit to “1” increases +20dB for the microphone volume, which is set to GN4-0 bits. GN4-0 ...........These bits determine the volume level of the microphone by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all bits are set to “1”, volume is minimum (-34.5dB). 10h : Line in Volume (Read/Write, Default: 8808h) 12h : CD Volume (Read/Write, Default: 8808h) 14h : Video Volume (Read/Write, Default: 8808h) 16h : Aux Volume (Read/Write, Default: 8808h) 18h : PCM out Volume (Read/Write, Default: 8808h) D15 D14 D13 Mute - - D12 D11 D10 GL4-0 D9 D8 D7 D6 D5 - - - D4 D3 D2 D1 D0 GR4-0 Mute..............Setting this bit to “1” mutes both left and right channels of the each source. GL4-0 ...........These bits determine the volume level of the left channel by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all bits are set to “1”, volume is minimum (-34.5dB). GR4-0 ...........These bits determine the volume level of the right channel by 1.5dB step. Setting to them is the same as the upper GL4-0 bits. 8 March 6, 2001 YMF753 1Ah : Record Select (Read/Write, Default: 0000h) D15 D14 D13 D12 D11 - - - - - D10 D9 D8 D7 D6 D5 D4 D3 - - - - - SL2-0 D2 D1 D0 SR2-0 SL2-0 ............These bits select the left channel source for A/D converter. SR2-0............These bits select the right channel source for A/D converter. SL2 SL1 SL0 Left Source SR2 SR1 SR0 Right Source 0 0 0 Mic 0 0 0 Mic 0 0 1 CD L-ch 0 0 1 CD R-ch 0 1 0 Video L-ch 0 1 0 Video R-ch 0 1 1 Aux L-ch 0 1 1 Aux R-ch 1 0 0 Line in L-ch 1 0 0 Line in R-ch 1 0 1 Stereo Mix L-ch 1 0 1 Stereo Mix R-ch 1 1 0 Mono Mix 1 1 0 Mono Mix 1 1 1 Phone 1 1 1 Phone D7 D6 D5 D4 - - - - 1Ch : Record Gain (Read/Write, Default: 8000h) D15 D14 D13 D12 Mute - - - D11 D10 D9 GL3-0 D8 D3 D2 D1 D0 GR3-0 Mute..............Setting this bit to “1” mutes the source which is selected at 1Ah:Record Select. GL3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SL2-0 bits, by 1.5dB step. The volume range is from 0dB to +22.5dB. When all bits are set to “0”, volume is minimum (0dB) and when all bits are set to “1”, volume is maximum (+22.5dB). GR3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SR2-0 bits, by 1.5dB step. Setting to them is the same as the upper GL3-0 bits. 9 March 6, 2001 YMF753 20h : General Purpose (Read/Write, Default: 0000h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POP - 3D - - - MIX MS LPBK - - - - - - - POP...............This bit selects whether PCM (DAC) output is gone through the 3D and Tone (Bass / Treble) or not. “0” : PCM (DAC) output is gone through the 3D and Tone. “1” : PCM (DAC) output is bypassed the 3D and Tone. 3D .................This bit selects whether 3D enhancement is used or not. “0” : Off “1” : On MIX ..............This bit selects the output to MONO_OUT(No.37). “0” : All mixing sources are output to MONO_OUT. “1” : The microphone input is output to MONO_OUT. MS ................This bit selects either MIC1 or MIC2 for the microphone input. “0” : MIC1 (No.21) “1” : MIC2 (No.22) LPBK............This bit selects data to the D/A converter. “0” : Data from the AC-Link “1” : Loopback from A/D converted data 22h : 3D Control (Read/Write, Default: 0000h) D15 D14 D13 D12 - - - - D11 D10 WD3-1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - WD3-1 ..........These bits determine the wide level of 3D enhancement (wide stereo). The wide range is from 0% to 100%. When all bits are set to “0”, wide level is 0% and when all bits are set to “1”, wide level is 100%. 10 March 6, 2001 YMF753 26h : Power Down (Read/Write, Default: 000xh) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EAPD - PR5 PR4 PR3 PR2 PR1 PR0 - - - - REF ANL DAC ADC EAPD............This bit controls the state of EAPD (No.47) pin. “0” : Low “1” : High PR5 ...............This bit controls the power state of the clock oscillation circuit. “0” : Normal “1” : Power down PR4 ...............This bit controls the power state of the AC-Link. “0” : Normal “1” : Power down PR3 ...............This bit controls the power state of the analog mixer. “0” : Normal “1” : Power down (Vref off) PR2 ...............This bit controls the power state of the analog mixer. “0” : Normal “1” : Power down (Vref still on) PR1 ...............This bit controls the power state of the D/A converter. “0” : Normal “1” : Power down PR0 ...............This bit controls the power state of the A/D converter. “0” : Normal “1” : Power down REF...............This bit is Read Only, and indicates the state of Vref. “0” : Ground level “1” : Reference voltage ANL..............This bit is Read Only, and indicates the state of the analog mixer. “0” : The analog mixer does not work. “1” : The analog mixer works normally. DAC..............This bit is Read Only, and indicates the state of the D/A converter. “0” : The D/A converter does not work. “1” : The D/A converter works normally. ADC..............This bit is Read Only, and indicates the state of the A/D converter. “0” : The A/D converter does not work. “1” : The A/D converter works normally. Note) When YMF753 is the Secondary CODEC, and both PR5 and PR4 are set to “1”, these bits are not cleared by Warm Reset. 11 March 6, 2001 YMF753 28h : Extended Audio ID (Read Only, Default: xxx4h) D15 D14 D13 D12 ID1 ID0 - - D11 D10 D9 REV1-0 D8 D7 D6 AMAP LDAC SDAC CDAC D5 D4 D3 D2 D1 D0 - - - SPDIF - - ID1,ID0.........These bits indicate CODEC ID. The states are determined by setting both No.46 and 45 pins. When MSEL is high, they are fixed to “Primary ID00”. ID1# (No.46) CODEC ID ID0# (No.45) Configuration Pin Status Logic Value Pin Status Logic Value OPEN (“H”) “0” OPEN (“H”) “0” Primary ID00 OPEN (“H”) “0” GND (“L”) “1” Secondary ID01 GND (“L”) “1” OPEN (“H”) “0” Secondary ID10 GND (“L”) “1” GND (“L”) “1” Secondary ID11 REV1-0.........These bits are hardwired to “01b”, which indicates AC’97 Revision 2.2 Compliant. AMAP...........This bit is hardwired to “1”. It indicates that the PCM DAC uses data of the standard slot into twelve slots, as the following table. CODEC Slot Number ID PCM Left DAC PCM Right DAC 00 Slot 3 Slot 4 Original definition (master) 01 Slot 3 Slot 4 Original definition (docking) 10 Slot 7 Slot 8 Left / Right surround channels 11 Slot 6 Slot 9 Center / LFE channels LDAC ...........When PCM DAC uses the LFE channel, this bit is set to “1”. SDAC ...........When PCM DAC uses the surround channels, this bit is set to “1”. CDAC ...........When PCM DAC uses the center channel, this bit is set to “1”. SPDIF ...........This bit is hardwired to “1”, which indicates that SPDIF output is compliant with AC’97 Revision 2.2. 2Ah : Ext Audio Stat/Ctrl (Read/Write, Default: 0400h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 - - - - - SPCV - - - - D5 D4 D3 D2 D1 D0 - SPDIF - - SPSA1-0 SPCV ............This bit is hardwired to “1”, which indicates that SPDIF output configuration is valid. SPSA1-0 .......These bits select DIT output slot. SPSA1 SPSA0 L-ch Slot Number R-ch Slot Number 0 0 Slot 3 Slot 4 0 1 Slot 7 Slot 8 1 0 Slot 6 Slot 9 1 1 Slot 10 Slot 11 SPDIF ...........This bit selects whether the SPDIF signal is output from DIT or not. “0” : DIT is power down state, and outputs low level. “1” : SPDIF signal is output from DIT. 12 March 6, 2001 YMF753 3Ah : DIT Control 1 (Read/Write, Default: 2000h) D15 D14 V - D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 GL CC6 CC5 CC4 CC3 CC2 CC1 CC0 SPSR1-0 D3 D2 D1 D0 PRE COPY AUD# PRO V ...................This bit determines V-bit (Validity flag) output from DIT. “0” : The Validity flag is “0” (Valid). “1” : The Validity flag is “1” (Invalid). SPSR1-0 .......These bits determine sampling frequency of channel status output from DIT. These bits are hardwired to “10b”, because SPDIF output of YMF753 is fixed to 48kHz. GL.................This bit determines bit15: L-bit (Generation status) of channel status output from DIT. The sense of Generation status is different by Category Code. CC6-0 ...........These bits determine bit14-8: Category Code of channel status output from DIT. PRE...............This bit determines bit3: Pre-emphasis of channel status output from DIT. “0” : without Pre-emphasis “1” : with Pre-emphasis of 50/15µs COPY ...........This bit determines bit2: Copy protection of channel status output from DIT. “0” : Copyright “1” : No Copyright AUD# ...........This bit determines bit1 of channel status output from DIT. If AC-3 or DTS is output, set to “1”. “0” : PCM format “1” : Non-PCM format PRO ..............This bit determines bit0 of channel status output from DIT. It should be set to “0” as Consumer use. 62h : Vendor Function (Read/Write, Default: 0224h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 * * * * * * * * * * * * D3 D2 TX-7 EXEN D1 D0 * * TX-7 .............This bit selects the pin function of No.47. “0” : EAPD “1” : DIT EXEN ...........This bit selects whether EXT24M pin outputs clock or not. “0” : EXT24M is power down state, and outputs low level. “1” : EXT24M outputs the clock. The bits except TX-7 and EXEN should not be changed from the default value. 13 March 6, 2001 YMF753 64h : ZV Port Volume (Read/Write, Default: 8808h or C808h) D15 D14 Mute MSEL D13 D12 D11 - D10 D9 D8 GL4-0 D7 D6 D5 ZEN ZAC - D4 D3 D2 D1 D0 GR4-0 Mute..............Setting this bit to “1” mutes both left and right channels of the ZV port. MSEL ...........This bit is read only, and indicates the status of No.40 MSEL pin. “0” : Low “1” : High GL4-0 ...........These bits determine the volume level of the ZV port left channel by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all bits are set to “1”, volume is minimum (-34.5dB). ZEN ..............This bit selects whether ZV port is used or not. “0” : ZV port is power down state, and can not be used. “1” : ZV port can be used. ZAC ..............This bit is read only, and indicates whether the bit clock (ZV_BCK) is input to ZV port or not. “0” : The bit clock (ZV_BCK) is not input. “1” : ZV port is active because the bit clock (ZV_BCK) is input. GR4-0 ...........These bits determine the volume level of the ZV port right channel by 1.5dB step. Setting to them is the same as the upper GL4-0 bits. 66h : DIT Control 2 (Read/Write, Default: 0040h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 - - - - - - - * * * TX-3 * D3 D2 D1 D0 TX-8 DMU UDS 3AWE TX-3 .............SPDIF signal is output from No.43 DIT, if this bit is set to “1” at MSEL= “Low”. TX-8 .............SPDIF signal is output from No.48 DIT, if this bit is set to “1” at MSEL= “Low”. DMU.............Setting this bit to “1” mutes audio data output from DIT. UDS ..............This bit selects the data output from DIT. “0” : Data from the AC-Link “1” : Data from A/D converter 3AWE ...........This bit selects whether 3Ah register can be written or not. “0” : 3Ah register is Read Only. “1” : 3Ah register is Read / Write. D8, D7, D6 and D4 should not be changed from the default value. 14 March 6, 2001 YMF753 68h : 3D Mode Select (Read/Write, Default: 0C00h) D15 D14 D13 D12 - - - - D11 D10 WM1-0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - WM1-0 .........These bits select the mode of 3D / Bass / Treble according to the frequency response of the speaker. WM1 WM0 3D Mode Target Speaker Speaker Size 0 0 Do not select. – – 0 1 DeskTop Standard Speaker 5 – 12 cm 1 0 Notebook PC 1 Small Speaker 3 cm 1 1 Notebook PC 2 Smaller Speaker 1.5 cm 7Ch : Vendor ID 1 (Read Only, Default: 594Dh) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 “0” “1” “0” “1” “1” “0” “0” “1” “0” “1” “0” “0” “1” “1” “0” “1” 7Eh : Vendor ID 2 (Read Only, Default: 4803h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 “0” “1” “0” “0” “1” “0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “1” 7Ch and upper 8 bits of 7Eh indicate Yamaha vendor ID, which is “YMH”. “Y” is 59h, “M” is 4Dh, and “H” is 48h with ASCII code. Lower 8 bits of 7Eh is YMF753 revision ID (03h). 15 March 6, 2001 YMF753 SYSTEM CONNECTION DIAGRAM CAP1 MONO_OUT LNLVL_OUT_L LNLVL_OUT_R LINE_OUT_L LINE_OUT_R PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 LINE_IN_L LINE_IN_R MIC2 +5.0V YMF753-S DVdd1,2 DVss1,2 +3.3V XTL_OUT XTL_IN ZV BCK ZV SIN ZV LR SDATA IN SDATA OUT BIT CLK SYNC RESET# 1) Vref Vrefout MSEL AVdd1,2 AVss1,2 SDATA_IN SDATA_OUT BIT_CLK SYNC RESET# EXT24M EAPD (DIT) ZV_LR ZV_SIN ZV_BCK PC Beep Phone L-ch AUX R-ch AUX L-ch Video R-ch Video L-ch CD CD Ground R-ch CD MIC L-ch Line IN R-ch Line IN CAP6 CAP5 CAP4 CAP3 CAP2 Mono Out L-ch LNLVL Out R-ch LNLVL Out L-ch LINE Out R-ch LINE Out EAPD / DIT DGND AGND Power and Ground To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks. Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The layout of the ground pattern should be designed as large as possible and the impudence should be reduced to prevent from receiving ambient noise. In addition, use 0.1µF and 47µF capacitors to connect between the analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground. 2) Reference Voltage As the reference voltage determines all analog signals’ reference levels of YMF753, noise generated from the reference voltage could affect the YMF753’s analog performance. To stabilize the YMF753’s reference voltage, insert a 0.1µF ceramic capacitor in parallel with a 22µF capacitor between Vref pin and the ground. The 0.1µF ceramic capacitor should be designed as close to the Vref pin as possible 3) Master Clock To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock guarded on the ground so the noise can be reduced. 4) Unused Analog Input / Output pins For the unused analog input pins, short them through a 0.1µF ceramic capacitor to the analog ground. For the unused analog output pins, they should be left opened. 16 March 6, 2001 YMF753 5) Recommended Analog Voltage Circuit YMF753 is presumed that it is made to work in the analog power supply formed from +5.0±0.25V power supply, because the range of analog operating voltage is being made +4.0V to +5.25V. The recommended circuit to form the analog power supply from +5V power supply is shown in below. +5.0V 470 W 100 µF +4.3V 0.1 µF To YMF753’s AVdd1,2 0.1 µF 17 March 6, 2001 YMF753 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Analog Supply Voltage AVDD -0.3 7.0 V Digital Supply Voltage DVDD -0.5 7.0 V Analog Input Voltage VINA -0.5 AVDD + 0.5 V Digital Input Voltage VIND -0.5 DVDD + 0.5 V Ambient Temperature TOP 0 70 °C Storage Temperature TSTG -50 125 °C Note) DVSS = AVSS = 0V 2. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Analog Operating Voltage AVDD 4.00 5.00 5.25 V Digital Operating Voltage DVDD 4.75 5.00 5.25 V 3.135 3.30 3.465 V 0 25 70 °C Operating Ambient Temperature TOP Note) DVSS = AVSS = 0V When using a recommended analog voltage circuit, the output serves as AVDD (typical 4.3V). 18 March 6, 2001 YMF753 3. DC Characteristics 3-1. AC-Link Parameter Symbol Condition Min. Typ. Max. Unit Input Voltage VIN -0.30 - DVDD + 0.30 V Input Voltage High Level VIH 0.65 ´ DVDD - - V Input Voltage Low Level VIL - - 0.35 ´ DVDD V Output Voltage High Level VOH IOH = -5mA 0.9 ´ DVDD - - V Output Voltage Low Level VOL IOL = 5mA - - 0.1 ´ DVDD V -10 - 10 µA -10 - 10 µA Input Leakage Current - Output Leakage Current - Hi-Z Note) Applicable to RESET#, SYNC, BIT_CLK, SDATA_IN and SDATA_OUT. 3-2. Miscellaneous Parameter Symbol Condition Min. Typ. Max. Unit Input Voltage High Level 1 VIH1 *1 0.7 ´ DVDD - - V Input Voltage Low Level 1 VIL1 *1 - - 0.3 ´ DVDD V Input Voltage High Level 2 VIH2 *2 0.8 ´ AVDD - - V Input Voltage Low Level 2 VIL2 *2 - - 0.2 ´ AVDD V Input Voltage High Level 3 VIH3 *3, DVDD=3.3V 2.0 - - V *3, DVDD=5.0V 0.7 ´ DVDD - - V Input Voltage Low Level 3 VIL3 *3, DVDD=3.3V - - 0.8 V *3, DVDD=5.0V - - 0.3 ´ DVDD V Output Voltage High Level 1 VOH1 *4, IOH = -4mA 0.65 ´ AVDD - - V Output Voltage Low Level 1 VOL1 *4, IOL = 4mA - - 0.4 V Output Voltage High Level 2 VOH2 *5, IOH = -2mA 0.65 ´ AVDD - - V Output Voltage Low Level 2 VOL2 *5, IOL = 2mA - - 0.4 V Output Voltage High Level 3 VOH3 *6, IOH = -2mA DVDD - 0.4 - - V Output Voltage Low Level 3 VOL3 *6, IOL = 2mA - - 0.4 V Pull-up Resistor RONUP ID0#, ID1# - 100 - kW Pull-down Resistor RONDW *3 - 100 - kW Note) *1 : Applicable to XTL_IN, ID0# and ID1#. *2 : Applicable to MSEL. *3 : Applicable to ZV_LR, ZV_SIN and ZV_BCK. *4 : Applicable to EAPD. *5 : Applicable to DIT(No.43). *6 : Applicable to EXT24M and DIT(No.48). 19 March 6, 2001 YMF753 4. AC Characteristics (Under recommended operating conditions, Capacitor load=50pF) 4-1. Reset Parameter Symbol Min. Typ. Max. Unit RESET# active low pulse width Trst_low 1.0 - - µs RESET# inactive to BIT_CLK start up delay Trst2clk 162.8 - - ns SYNC active high pulse width Tsync_high 1.0 - - µs SYNC inactive to BIT_CLK start up delay Tsync2clk 162.8 - - ns Cold Reset (SDATA_OUT=“L”, SYNC=“L”) Warm Reset Cold Reset Trst2clk Trst_low RESET# VIL BIT_CLK Warm Reset Tsync2clk Tsync_high SYNC VIH BIT_CLK 20 March 6, 2001 YMF753 4-2. AC-link Interface Parameter Symbol BIT_CLK frequency BIT_CLK clock period Tclk_period BIT_CLK output jitter Min. Typ. Max. Unit - 12.288 - MHz - 81.4 - ns - - 750 ps BIT_CLK low pulse width Tclk_low 36.0 40.7 45.0 ns BIT_CLK high pulse width Tclk_high 36.0 40.7 45.0 ns SYNC frequency 48.0 SYNC period kHz Tsync_period - 20.8 - µs SYNC low pulse width Tsync_low - 19.5 - µs SYNC high pulse width Tsync_high - 1.3 - µs SDATA_OUT, SYNC setup time Tsetup 10.0 - - ns SDATA_OUT hold time Thold 20.0 - - ns Tco - - 15.0 ns Ts2_pdown - - 1.0 µs SDATA_IN delay time AC-link Low Power Mode End of slot 2 to BIT_CLK, SDATA_IN low BIT_CLK Tclk_high Tclk_low BIT_CLK Tclk_period SYNC Tsync_high Tsync_low SYNC Tsync_period Data Output and Input Timing Tco Tsetup BIT_CLK SDATA_IN Thold SDATA_OUT, SYNC 21 March 6, 2001 YMF753 AC-link Low Power Mode Slot1 Slot2 BIT_CLK SDATA_OUT Write to 26h Data PR4 Don’t Care Ts2_pdown SDATA_IN 4-3. Master Clock & External Clock Out Parameter Symbol Min. Typ. Max. Unit Tcycle - 40.69 - ns XTL_IN clock duty Duty-xtl 40 - 60 % EXT24M clock duty Duty-ext 40 - 60 % XTL_IN, EXT24M clock period XTL_IN & EXT24M XTL_IN EXT24M Tcycle 22 March 6, 2001 YMF753 4-4. Zoomed Video Port Parameter Symbol Min. Typ. Max. Unit ZV_BCK frequency fBCK 32fs 48fs 64fs kHz ZV_BCK duty DBCK 40 50 60 % ZV_LR delay time tLRD 120 - - ns ZV_LR setup time tLRS 32 - - ns ZV_SIN setup time tDS 32 - - ns ZV_SIN hold time tDH 2 - - ns Zoomed Video Port 1/fBCK ZV_BCK tDH tDS ZV_SIN tLRD tLRS ZV_LR 5. Power Consumption Parameter Min. Typ. Max. Unit AVDD = 4.3V / DVDD = 3.3V 45 mA AVDD = 5.0V / DVDD = 5.0V 55 mA Normal Operating AVDD = 4.3V 35 mA AVDD = 5.0V 43 mA DVDD = 3.3V 8 mA DVDD = 5.0V 12 mA Power Down Mode (PR0-PR5=0) AVDD = 4.3V / DVDD = 3.3V 10 µA AVDD = 5.0V / DVDD = 5.0V 20 µA AVDD = 4.3V 7 µA AVDD = 5.0V 12 µA DVDD = 3.3V 2 µA DVDD = 5.0V 4 µA 23 March 6, 2001 YMF753 6. Analog Characteristics Parameter Min. Typ. Max. Unit Full Scale Line Input AVDD / 5 Vrms Full Scale Microphone Input (0dB) AVDD / 5 Vrms Full Scale Microphone Input (+20dB) AVDD / 50 Vrms Full Scale Line Output AVDD / 5 Vrms 90 dB 95 dB Analog S/N CD to LINE_OUT Stereo input except CD to LINE_OUT 90 Analog Frequency Response 20 S/N : D/A converter (fs=48kHz) 85 90 dB S/N : A/D converter (fs=48kHz) 75 85 dB THD+N : Line Output 20,000 Hz AVDD=5.0V -70 -65 dB AVDD=4.3V -68 -62 dB 20 19,200 Hz Transition Band 19,200 28,800 Hz Stop Band 28,800 Hz 70 dB D/A & A/D Frequency Response Stop Band Rejection Out-of-Band Rejection 40 Group Delay dB 1 Power Supply Rejection Rate (1kHz) 40 Crosstalk between Inputs Channels ms dB -70 dB Attenuation & Gain Step PC_BEEP 3.0 dB Other than PC_BEEP 1.5 dB Input Impedance 10 kW Input Capacitor 7.5 pF Vrefout Voltage AVDD / 2 V Note) Typical conditions : TOP=25°C, DVDD=3.3V, AVDD=4.3V to 5.0V, 1kHz input sine wave, fs=48kHz, 0dB=AVDD/5 Vrms, 10kW / 50pF S/N (dynamic range) measurement: -60dB input, THD+N measurement: -3dB input 24 March 6, 2001 YMF753 EXTERNAL DIMENSIONS 9.00±0.40 C-PK48SP-2 7.00±0.30 25 24 48 13 7.00±0.30 37 12 1 P-0.50TYP 1.40TYP or 1.45TYP 1.85MAX. (Installation height) 0.20TYP or 0.18TYP 0 MIN. (STAND OFF) 9.00±0.40 36 (1.0) 0-10˚ 0.50±0.20 LEAD THICKNESS : 0.125TYP or 0.17TYP The shape of the molded corner may slightly different from the shape in this diagram. The figures in the parenthesis ( ) should be used as a reference. Plastic body dimension do not include burr of resin. UNIT : mm Note : The LSIs for surface mounting need for special care on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. 25 March 6, 2001 YMF753 IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer’s sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS’ INFRINGEMENT OF ANY THIRD PARTY’S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. Note) The specifications of this product are subject to improvement change without prior notice. AGENCY YAMAHA CORPORATION Address inquires to : Semi-conductor Sales & Marketing Department - Head Office - Tokyo Office - Osaka Office 26 All rights reserved © 2001 YAMAHA CORPORATION 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 March 6, Printed in 2001 Japan