CXP827P16
CMOS 8-bit Single Chip Microcomputer
Description
The CXP827P16 microcomputer is composed of a
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, fluorescent
display panel controller/driver, remote control receiver,
PWM output circuit and 32kHz timer/counter.
This IC also includes sleep/stop functions which
can be used to achieve low power consumption.
CXP827P16 is the PROM-incorporated version of
the CXP82716 with built-in mask ROM, and it is able to
write directly into the program. Thus, it is most suitable
for evaluation use during system development and for
small-quantity production.
64 pin SDIP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Instruction set which supports a wide array of data types
— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic,
and Boolean bit operations.
• Minimum instruction cycle
400ns at 10MHz
122µs at 32kHz
• On-chip PROM
16 Kbytes
• On-chip RAM
448 bytes (Including fluorescent display data area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation system
(conversion rate 32µs/10MHz)
— Serial interface
On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),
2 channels for 1 circuit
— Timers
8-bit timer
8-bit timer/counter
19-bit time-base timer
32kHz timer/counter
— Fluorescent display panel controller/driver
High voltage drive output port of 24 pins (40V)
Maximum of 144 segments display available
1 to 16-digit dynamic display
Dimmer function
On-chip pull-down resistor
Hardware key scan function (Maximum of 8 × 8 key matrix available)
— Remote control receiver circuit
On-chip 6-stage FIFO 8-bit pulse measurement counter
— PWM output
8-bit, 1-channel
• Interrupts
13 factors, 13 vectors multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
64-pin plastic SDIP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93Z22-ST
8
8
T8/S28 to T15/S21
S13 to S20
VFDP
KR0 to KR7
ADJ
TO
EC
PWM
CS0
SI0
SO0
SCK0
CS1
SI1
SO1
SCK1
RMC
8
T0 to T7
8
8
AN0 to AN7
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
8 BIT PWM
FIFO
FIFO
REMOCON
SERIAL
INTERFACE
UNIT
RAM
RAM
KEY SCAN
FDP
CONTROLLER/
DRIVER
A/D CONVERTER
2
INT0
INT1
INT2
INT3/NMI
2
PRESCALER/
TIME BASE TIMER
PROM
16KBYTES
SPC700
CPU CORE
TEX
TX
EXTAL
XTAL
RST
VDD
Vss
VPP
32kHz
TIMER/COUNTER
RAM
448 BYTES
CLOCK
GENERATOR /
SYSTEM CONTROL
PB0 to PB7
8
8
2
PH0 to PH1
PF5 to PF7
PE5 to PE6
2
3
PE0 to PE4
5
PC0 to PC7
PA0 to PA7
8
PORT A
PORT B
PORT C
PORT E
PORT
F
–2–
PORT H
INTERRUPT CONTROLLER
Block Diagram
CXP827P16
2
CXP827P16
Pin Configuration (Top View)
PH0/TX
1
64
VDD
PH1/TEX
2
63
PE5/PWM
VPP
3
62
PE4/RMC
PE6/ADJ/TO
4
61
PE3/INT3/NMI
PB0/CS1
5
60
PE2/INT2
PB1/CS0
6
59
PE1/INT1
PB2/SCK0
7
58
PE0/EC/INT0
PB3/SI0
8
57
VFDP
PB4/SO0
9
56
T0
PB5/SCK1
10
55
T1
PB6/SI1
11
54
T2
PB7/SO1
12
53
T3
PC0/KR0
13
52
T4
PC1/KR1
14
51
T5
PC2/KR2
15
50
T6
PC3/KR3
16
49
T7
PC4/KR4
17
48
T8/S28
PC5/KR5
18
47
T9/S27
PC6/KR6
19
46
T10/S26
PC7/KR7
20
45
T11/S25
PA0/AN0
21
44
T12/S24
PA1/AN1
22
43
T13/S23
PA2/AN2
23
42
T14/S22
PA3/AN3
24
41
T15/S21
PA4/AN4
25
40
S20
PA5/AN5
26
39
S19
PA6/AN6
27
38
S18
PA7/AN7
28
37
S17
RST
29
36
S16
EXTAL
30
35
PF7/S15
XTAL
31
34
PF6/S14
Vss
32
33
PF5/S13
Note) 1. Vpp (Pin 3) is always connected to VDD.
2. PH0/TX (Pin 1) is input port during port selection;
oscillation output during oscillation selection
–3–
CXP827P16
Pin Description
I/O
Symbol
PA0/AN0
to
PA7/AN7
I/O/Analog Input
PB0/CS1
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
Functions
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Chip select input for serial interface (CH1).
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Key return input for fluorescent display panel
(FDP) segment signal which performs key
scanning.
(8 pins)
PC0/KR0
to
PC7/KR7
I/O/Input
PE0/INT0/
EC
Input/Input/
Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/
Input
PE4/RMC
Input/Input
PE5
Output
8-bit PWM output.
PE6/ADJ/TO
Output
Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.
(Port E)
7-bit port.
Lower 5 bits are for
inputs; upper 2 bits are
for outputs.
(7 pins)
–4–
External interrupt
requests.
(4 pins)
External event input to
timer/counter.
Non-maskable interruption request input.
Input for remote control receiving circuit.
CXP827P16
Symbol
I/O
Functions
PF5/S13
to
PF7/S15
Output/Output
(Port F)
3-bit output port.
(3 pins)
S16 to S20
Output
Segment signal output for FDP. (5 pins)
T8/S28
to
T15/S21
Output/Output
Output for FDP timing and segment signals. (8 pins)
T0 to T7
Output
Timing signal output for FDP. (8 pins)
Segment signal output for FDP.
(3 pins)
FDP voltage supply when on-chip resistor is selected by mask option.
VFDP
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
Input
XTAL
Output
PH1/TEX
Input/Input
PH0/TX
Input/Output
(Port H)
2-bit input
port.
(2 pins)
RST
Input
System reset. Low-level active. RST is input pin.
Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.
Vpp
Positive power supply pin for writing of built-in PROM.
Under normal operating conditions, connect to VDD.
VDD
Positive power supply.
Vss
GND
–5–
CXP827P16
I/O Circuit Format for Pins
Pin
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
Circuit format
Port A
*
Pull-up resistor
AA
AAAA
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
"0" when reset
Input protection
circuit
Hi-Z
Data bus
RD (Port A)
Port A input
selection
"0" when reset
Input multiplexer
A/D converter
8 pins
Port B
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistors
approx. 100kΩ
∗
Pull-up resistor
AA
AAAA
"0" when reset
Port B data
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Data bus
Hi-Z
Schmitt input
RD (Port B)
CS0
CS1
SI0
SI1
4 pins
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistors
approx. 100kΩ
SI0 and SI1 are not schmitt input.
Port B
∗
Pull-up resistor
"0" when reset
SCK OUT
Serial clock output enable
AA
AAAA
Port B output
selection
"0" when reset
PB2/SCK0
PB5/SCK1
IP
Port B data
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
2 pins
SCK IN
–6–
∗ Pull-up transistors
approx. 100kΩ
Hi-Z
CXP827P16
Pin
When reset
Circuit format
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
PB4/SO0
PB7/SO1
"0" when reset
SO
Serial data output enable
Port B output
selection
"0" when reset
AA
AAAA
IP
Port B data
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
2 pins
∗ Pull-up transistors
approx. 100kΩ
AAAA
AAAA
AAAA
AAAA
Port C
∗2
Pull-up resistor
AA
AAAA
"0" when reset
PC0/KR0
to
PC7/KR7
Port C data
∗1
Port C direction
"0" when reset
Hi-Z
IP
Data bus
RD (Port C)
8 pins
∗1 Large current drive of 12mA possible
∗2 Pull-up transistors approx. 100kΩ
Key input signal
Port E
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
A A
EC/INT0
INT1
INT2
INT3/NMI
RMC
Schmitt input
IP
Data bus
RD (Port E)
5 pins
–7–
Hi-Z
CXP827P16
Pin
When reset
Circuit format
AAA
AAA
AAA
AAA
Port E
AA
AA
PWM
Port E output
selection
"0" when reset
PE5/PWM
Port E data
Output enable
"1" when reset
High level
Data bus
RD (Port E)
1 pin
Port E
AAAA
00
Port E data
PE6/TO/ADJ
Internal reset signal
"1" when reset TO
01
ADJ16K∗1
10
ADJ2K∗1
11
AA
AA(
MPX
∗2
AAAAA
AAAAA
Port E output selection(upper)
Port E output selection(lower)
High level
with approx.
150kΩ
resistor
when reset
∗1 ADJ signal is a frequency dividing output
for 32kHz oscillation frequency adjustment.
ADJ2K can be used for buzzer output.
∗2 Pull-up transistor approx. 150kΩ .
"00" when reset
TO output enable
1 pin
Port F
∗ High voltage drive transistor
Segment output data
PF5/S13
to
PF7/S15
∗
AAA
Output selection control signal
("0" when reset)
Port F data
Data bus
3 pin
RD (Port F)
–8–
AA
AA
Hi-Z
)
CXP827P16
Circuit format
Pin
When reset
AA
AA
AA
AA
∗ High voltage drive transistor
S16 to S20
T15/S21
to
T8/S28
T0 to T7
Segment output data
∗
Output selection control signal
("0" when reset)
Pull-down
resistor
21 pins
EXTAL
XTAL
2 pins
AA AA A
AA
IP
EXTAL
IP
Low level
VFDP
• Diagram shows circuit
construction for oscillation.
• During STOP feedback
resistor is disconnected,
and XTAL becomes "H"
level.
Oscillator
XTAL
32kHz oscillation
circuit control
"1" when reset
Data
bus
PH1/TEX
PH0/TX
AA AA AA
AA
AA
AA AA
PH1/TEX
2 pins
IP
IP
RD (Port H)
Data
bus
RD (Port H)
Clock
input
Oscillation
halted
prot input
PH0/TX
Pull-up resistor
RST
1 pin
IP
Schmitt input
–9–
Low level
CXP827P16
Absolute Maximum Ratings
Item
(Vss = 0V)
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
–0.3 to +13.0
V
Input voltage
VIN
–0.3 to +7.0∗1
V
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD – 40 to VDD + 0.3
V
As P channel transistor is open drain,
VDD voltage is determined as reference.
IOH
–5
mA
Other than display putput pins∗2: per pin
IODH1
–15
mA
Display output S13 to S20: per pin
IODH2
–35
mA
Display output T0 to T7
T8/S28 to T15/S21: per pin
∑IOH
–40
mA
Total of other than display output pins
∑IODH
–100
mA
Total of display output pins
IOL
15
mA
Port 1 pin
IOLC
20
mA
Large current port pin∗3
Low level total output current ∑IOL
100
mA
Total of all pins
Supply voltage
High level output current
High level
total output current
Low level output current
Symbol
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
1000
mW
Remarks
Incorporated PROM
∗1) VIN and VOUT must not exceed VDD+0.3V.
∗2) Specifies output current of general-purpose I/O ports.
∗3) The large current drive transistor is an N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP827P16
Recommended Operating Conditions
Item
Supply voltage
Symbol
VDD
(Vss = 0V)
Min.
Max.
Unit
Remarks
4.5
5.5
V
Guaranteed operation range for high speed
mode (1/2, 1/4 frequency dividing clock)
3.5
5.5
V
Guaranteed operation range for low speed
mode (1/16 frequency dividing clock)
2.7
5.5
V
Guaranteed operation range with TEX clock
2.5
5.5
V
Guaranteed data hold operation range
during STOP
V
∗4
Vpp
Vpp = VDD
VIH
0.7VDD
VDD
V
∗1
VIHS
0.8VDD
VDD
V
Hysteresis input∗2
VIHEX
VDD – 0.4
VDD +0.3
V
EXTAL pin∗3
VIL
0
0.3VDD
V
∗1
VILS
0
0.2VDD
V
Hysteresis input∗2
VILEX
–0.3
0.4
V
EXTAL pin∗3
Operating temperature Topr
–10
+75
°C
High level
input voltage
Low level
input voltage
∗1)
∗2)
∗3)
∗4)
All regular input port (PA, PB4, PB7, PC, PH).
For pins RST, CS0, CS1, SI0, SI1 SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.
Specifies only for external clock input.
Vpp should be the same voltage as VDD.
– 11 –
CXP827P16
Electrical Characteristics
DC Characteristics
Item
(Ta = –10 to +75°C, Vss = 0V)
Symbol
High level
VOH
output voltage
Low level
output voltage VOL
Pin
Input current
IIH
IIZ
3.5
V
EXTAL
TEX
RST
PA to PC∗1
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
VDD = 5.5V, VIL = 0.4V
–1.5
–400
µA
VDD = 4.5V, VIH = 4.0V
–3.3
µA
VDD = 5.5V, VIL = 0.4V
PA to PC∗1, VDD = 5.5V
PE0 to PE4 VI = 0, 5.5V
S13 to S20
Display
IOH
output current
S21/T15 to
S28/T8,
T0 to T7
Open drain
output leak
current (P-CH
Tr off state)
ILOL
S13 to S20,
S21/T15 to VDD = 5.5V
VOL = VDD – 35V
S28/T8,
VFDP = VDD – 35V
T0 to T7
RL
S16 to S20,
S21/T15 to VDD = 5V
S28/T8,
VFDP = VDD – 35V
T0 to T7
Pull-down
resistor
Unit
PA, PB, PC, VDD = 4.5V, IOH = –1.2mA
PE5, PE6
VDD = 4.5V, IOL = 1.8mA
IIL
I/O
leak current
Max.
V
IILT
IILR
Typ.
4.0
IILE
IIHT
Min.
VDD = 4.5V, IOH = –0.5mA
PC
IIHE
Condition
VDD = 4.5V
VOH = VDD –2.5V
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
50
µA
±10
µA
–8
mA
–20
mA
60
–20
µA
100
270
kΩ
20
40
mA
400
1000
µA
1.2
8
mA
9
30
µA
30
µA
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDD2
Supply
current∗2
IDDS1
VDD
SLEEP mode
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
IDDS2
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDDS3
STOP mode
VDD = 5.5V, termination of 10 MHz and
32 kHz crystal oscillation.
– 12 –
CXP827P16
Item
Input
capacitance
Symbol
CIN
Pin
Codition
PA to PC,
1MHz clock
PE0 to PE4,
0V for pins other than the measured
PH, EXTAL,
pins
XTAL, RST
Min.
Typ.
Max.
Unit
10
20
pF
∗1) In each pin of PA to PC, the input current is specified when pull-up resistor has been selected; leakage
current is specified when no resistor is selected.
∗2) All output pins are left open.
– 13 –
CXP827P16
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
System clock frequency
fC
Event count input clock
rise and fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input pulse width
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
Pin
Conditions
Typ.
Min.
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
1
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗ tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAAAAAA
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HCO4
TX
C1
C2
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
– 14 –
tEL
tTL
tER
tTR
CXP827P16
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
(2) Serial transfer
Item
Symbol
CS0 ↓→ SCK0 (CS1 ↓→ SCK1)
delay time
tDCSK
CS0 ↑→ SCK0 (CS1 ↑→ SCK1)
float delay time
tDCSKF SCK0 Chip select transfer mode
CS0 ↓→ SO0 (CS1 ↓→ SO1)
delay time
tDCSO
CS0 ↑→ SO0 (CS1 ↑→ SO1)
float delay time
Pin
Condition
Min.
SCK0 Chip select transfer mode
(SCK1) (SCK0 (SCK1) = output mode)
Unit
tsys + 200 ns
tsys + 200 ns
(SCK1) (SCK0 (SCK1) = output mode)
SO0
(SO1)
Max.
Chip select transfer mode
tsys + 200 ns
tDCSOF SO0
Chip select transfer mode
tsys + 200 ns
CS0 (CS1) high level width
tWHCS CS0
Chip select transfer mode
SCK0 (SCK1) cycle time
tKCY
SCK0 (SCK1)
High and Low level widths
(SO1)
tsys + 200
ns
SCK0 Input mode
(SCK1) Output mode
2tsys + 200
ns
16000/fc
ns
tKH
tKL
SCK0 Input mode
(SCK1) Output mode
tsys + 100
ns
8000/fc–5
ns
SI0 (SI1) input setup time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
0
ns
tSIK
SCK0 (SCK1) output mode
100
ns
SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
200
ns
tKSI
tsys + 200
ns
SCK0 ↓→ SO0 (SCK1 ↓→ SO1)
delay time
tKSO
SO0
(SO1)
SCK0 (SCK1) input mode
(CS1)
SCK0 (SCK1) output mode
SCK0 (SCK1) output mode
100
tsys + 200 ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF+1TTL.
– 15 –
CXP827P16
Fig. 4. Serial transfer CH0 timing
tWHCS
0.8VDD
CS0
(CS1)
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
(SCK1)
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
(SI1)
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
(SO1)
Output
data
0.2VDD
– 16 –
CXP827P16
(3) A/D converter characteristics
Item
Symbol
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
Conversion time
Sampling time
Pin
Condition
Min.
Ta = 25°C
VDD = 5.0V
VSS = 0V
Typ.
–10
10
70
mV
VFT∗2
4910
4970
5030
mV
tCONV
tSAMP
160/fADC∗3
µs
12/fADC∗3
µs
Analog input voltage VIAN
0
AN0 to AN7
VDD
Fig. 5. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1)V ZT : Value at which the digital conversion value changes
from 00 H to 01H and vice versa.
∗2)V FT : Value at which the digital conversion value changes
from FE H to FFH and vice versa.
∗3)f ADC indicates the below values due to the bit 6 (CKS) of
A/D control registor (ADC: 00F9 H) and the bit 7 (PCK1)
and bit 6 (PCK0) of clock control registor (CLC: 00FE H)
Linearity error
01H
CKS
00H
VZT
VFT
Analog input
0 (φ/2 selection)
1 (φ selection)
00 (φ= fEX/2)
fADC = fC/2
fADC = fC
01 (φ= fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ= fEX/16)
fADC = fC/16
fADC = fC/8
PCK1, 0
– 17 –
V
CXP827P16
(4) Interruption, reset input
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
External interruption
High and Low level widths
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input Low level width
tRSL
RST
Condition
Min.
Max.
Unit
1
µs
32/fc
µs
Fig 6. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI is specified only for
the falling edge)
0.2VDD
tIL
tIH
Fig. 7. RST input timing
tRSL
RST
0.2VDD
– 18 –
CXP827P16
Appendix
Fig. 8. Recommended oscillation circuit
AAAA
AAAA
(i) Main clock
EXTAL
XTAL
Rd
AAAA
AAAA
(ii) Main clock
EXTAL
XTAL
Rd
AAAAA
AAAAA
(iii) Sub clock
EXTAL
TEX
Rd
C2
C1
XTAL
TX
C2
C1
C1 C2
Manufacturer
MURATA
MFG
CO., LTD.
Model
fc (MHz)
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
4.19
CST8.00MTW∗
8.00
CST10.0MTW∗
10.00
C1 (pF)
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
30
0
(ii)
4.19
RIVER
ELETEC
CO., LTD.
HC-49/U03
12
8.00
12
0
10.00
(i)
4.19
HC-49/U (-S)
KINSEKI
LTD.
P3
27
27
10.00
20
20
32.768kHz
50
22
8.00
0
1M
(iii)
The above model with an asterisk (∗) includes the capacitors (C1, C2).
Selection Guide
Option Item
Package
Mask Product
CXP827P16S-1-
64-pin plastic SDIP
64-pin plastic SDIP
ROM capacitance
12 Kbytes/16 Kbytes
PROM 16 Kbytes
Reset pin pull-up resistor
Existent/Non-Existent
Existent
High voltage drive output pin
pull-down resistor
Existent/Non-Existent
Existent (T0 to T7, S16 to S28),
Non-Existent (S13 to S15)
– 19 –
CXP827P16
Characteristics Curves
IDD vs. VDD
IDD vs. fc
(fc = 10MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
20.0
1/2 frequency
dividing mode
20
5.0
1/16 frequency
dividing mode
32kHz mode
(instruction)
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
IDD — Supply current [mA]
IDD — Supply current [mA]
10.0
15
1/2 frequency dividing mode
10
5
1/16 frequency dividing mode
0.01
(10µA)
SLEEP mode
2
3
4
5
6
7
0
VDD — Supply voltage [V]
– 20 –
5
10
fc — System clock [MHz]
15
CXP827P16
Package Outline
Unit: mm
+ 0.1
0.05
0.25 –
64PIN SDIP (PLASTIC) 750mil
+ 0.4
57.6 – 0.1
64
19.05
+ 0.3
17.1 – 0.1
33
32
3 MIN
1.778
0.5 MIN
+ 0.4
4.75 – 0.1
1
0° to 15°
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
SONY CODE
SDIP-64P-01
EIAJ CODE
SDIP064-P-0750-A
JEDEC CODE
MOLDING COMPOUND
EPOXY / PHENOL RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
8.6g
– 21 –