TI 5962-1320201VXC

TPS7H1101-SP
TPS7H1201-HT
www.ti.com
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
1.5-V to 7-V, ULTRA LOW DROPOUT REGULATOR
Check for Samples: TPS7H1101-SP, TPS7H1201-HT
FEATURES
1
•
•
•
•
•
•
•
•
•
Current Share/Parallel Operation to Provide
Higher Output Current
Wide VIN Range: 1.5 V - 7 V
5962R13202:
– Radiation Hardness Assurance (RHA) up to
TID 100 krad (Si)
– Total Ionizing Dose 100 krad (Si)
– ELDRS free 100 krad (Si)
– Dose rate 10mRAD(si)/sec
– Single Event Latchup (SEL) Immune to
LET = 85MeV-cm2/mg
– SEB and SEGR Immune to
LET = 85MeV-cm2/mg
– SET/SEFI Onset Threshold
is = 40MeV-cm2/mg, See Radiation Report
for details
– SET/SEFI Cross-Section Plot, See Radiation
Report for details
Stable With Ceramic Output Capacitor
±2.0 % Accuracy over Line, Load and
Temperature (TPS7H1101-SP)
±4.2 % Accuracy over Line, Load and
Temperature (TPS7H1201-HT)
Programmable SoftStart
PowerGood Output
Low Dropout Voltage
– TPS7H1201-HT
100 mV (MAX) at 0.5 A (210°C) , VOUT= 6.8V
– TPS7H1101-SP
62 mV at 1 A (25°C), VOUT = 1. 8V
125 mV at 2 A (25°C), VOUT = 1.8 V
196 mV at 3 A (25°C), VOUT = 1.8 V
210 mV at 3 A (25°C), VOUT = 1.3 V
335 mV (MAX) at 3A (125°C) , VOUT = 1.3 V
•
•
•
•
•
Low Noise
– TPS7H1201-HT
20.26 µVRMS (VIN = 2.1 V, VOUT = 1.8 V at
0.5 A)
31.0 µVRMS (VIN = 7 V, VOUT = 6.7 V at 0.5 A)
– TPS7H1101-SP
20.33 µVRMS (VIN = 2 V, VOUT = 1.8V at 3A)
31.68 µVRMS (VIN = 7 V VOUT = 6.7V at 3A)
PSRR: Over 45 dB at 1 kHz
Load/Line Transient Response
Fold-Back Current Limit (TPS7H1101-SP)
16-Pin Thermally Enhanced Ceramic Flatpack
Package (HKS/HKR)
APPLICATIONS
•
•
•
•
•
•
•
•
(1)
(2)
TPS7H1101-SP: Rad Tolerant Applications
RF 5-V Components VCOs, Receivers, ADCs,
Amplifiers
Clock Distribution
Clean Analog Supply Requirements
Supports Harsh Environment Applications
TPS7H1201-HT Available in Extreme
(–55°C to 210°C) Temperature Range
TPS7H1101-SP Available in Military
(–55°C to 125°C) Temperature Range (1)
TPS7H1201-HT: Texas Instruments' high
temperature products utilize highly optimized
silicon (die) solutions with design and process
enhancements to maximize performance over
extended temperatures.
Engineering Evaluation (/EM) Samples are
Available (2)
Custom temperature ranges available
These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (e.g. No Burn-In,
etc.) and are tested to a temperature rating of 25°C only.
These units are not suitable for qualification, production,
radiation testing or flight use. Parts are not warranted for
performance over the full MIL specified temperature range of
-55°C to 125°C or operating life.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS7H1101-SP
TPS7H1201-HT
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
www.ti.com
DESCRIPTION
The TPS7H1x01 is a low dropout (LDO) linear regulator that uses a PMOS pass element configuration. It
operates under wide range of input voltage, from 1.5 V to 7V while offering excellent PSRR. The TPS7H1x01
features a precise and programmable fold back current limit implementation with a very wide adjustment range.
To support complex power requirements of FPGAs, DSPs, or Microcontrollers the TPS7H1x01 provides enable
on/off functionality, programmable SoftStart, current sharing capability, and a PowerGood open drain output. The
TPS7H1x01 is available in a thermally enhanced16-pin ceramic flatpack package (CFP) .
DESCRIPTION (CONTINUED)
xxx
VDO vs. IOUT (TPS7H1201-HT)
LDO Current Share (TPS7H1201-HT)
80
55.00
210 °C
70
53.00
125 °C
60
52.00
25 °C
% of Total Load
Dropout Voltage (mV)
LDO1
LDO2
54.00
50
-55 °C
40
30
51.00
50.00
49.00
48.00
47.00
20
46.00
10
45.00
0.2
0
0.0
0.1
0.2
0.3
0.4
0.4
IOUT (A)
0.8
1
Output Current
C001
VDO vs. IOUT (TPS7H1101-SP)
LDO Current Share (TPS7H1101-SP)
350
65.00
LDO1
LDO2
125 °C
300
60.00
250
55.00
25 °C
% of total Load
Dropout Voltage (mV)
0.6
0.5
200
-55 °C
150
100
50.00
45.00
40.00
50
0
35.00
0
0.5
1
1.5
2
2.5
3
0
1
2
IOUT (A)
3
4
5
6
Output Current
TYPICAL APPLICATION CIRCUIT
TPS7H1x01
5V
Power
Good
VIN
CIN
Rcs
COMP
EN
Rt
PCL
Rpcl
Soft
Start
CSS
2
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3.3 V
VOUT
CS
GND
COUT
Feed
Back
Rb
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS7H1101-SP TPS7H1201-HT
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TPS7H1201-HT
www.ti.com
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
over operating temperature range (unless otherwise noted)
UNIT
Input voltage range
VIN, PG
FB, COMP, PCL, CS, EN
Output voltage range
VOUT , SS
-0.3 to 7.5
V
-0.3 to VIN + 0.3
V
-0.3 to VIN
V
Peak output current
Internally limited
A
PG pin sink current
5
mA
Electrostatic discharge rating (HBM)
2
kV
Electrostatic discharge rating (CDM)
1
kV
Maximum Operating junction
temperature, TJ
TPS7H1201
-55 to 220
TPS7H1101
-55 to 150
Storage temperature, TJ
TPS7H1201
-65 to 220
TPS7H1101
-65 to 150
(1)
°C
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS7H1101-SP TPS7H1201-HT
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TPS7H1101-SP
TPS7H1201-HT
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
www.ti.com
THERMAL INFORMATION (1) (2) (3)
TPS7H1x01
THERMAL METRIC (4)
HKS
(HeatSlug_up_no
Underfill) (5)
HKR
(HeatSlug_down
Underfill) (6) (7)
HKR
(HeatSlug_down_no
Underfill)
16 PINS
16 PINS
16 PINS
θJA
Junction-to-ambient thermal resistance (8)
75.4
30.7
86.6
θJCtop
Junction-to-case (top) thermal resistance (9)
0.4
N/A
N/A
(10)
θJB
Junction-to-board thermal resistance
4.8
69
59.3
ψJT
Junction-to-top characterization
parameter (11)
1.1
2.4
5
ψJB
Junction-to-board characterization
parameter (12)
53.5
12.3
63.2
θJCbot
Junction-to-case (bottom) thermal
resistance (13)
N/A
0.6
0.6
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
4
UNITS
°C/W
Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.
Maximum power dissipation may be limited by overcurrent protection.
Test board conditions:
(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 48 0.010 inch thermal vias located under the device package
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature below 220°C. This is the point
where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or
below 220°C for best performance and long-term reliability.
Power rating at a specific ambient temperature TA should be determined with a junction temperature below 135°C. This is the point
where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or
below 230°C for best performance and long-term reliability.
Values listed in the underfill column were derived using properties from a composite, generic silver filled epoxy underfill. They are not
product specific.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Product Folder Links: TPS7H1101-SP TPS7H1201-HT
TPS7H1101-SP
TPS7H1201-HT
www.ti.com
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
TPS7H1201 ELECTRICAL CHARACTERISTICS
1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.3 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, over
operating temperature range (TJ = -55°C to 210°C), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
VFB
Feedback pin
voltage
VOUT
TEST CONDITIONS
MIN
1.5 V ≤ VIN ≤ 7 V
ΔVOUT%/
ΔVIN
Line regulation
1.5 V ≤ VIN ≤ 7 V
ΔVOUT%/
ΔIOUT
Load regulation
0.8 V ≤ VOUT ≤ 6.8 V, 0 ≤ ILoad ≤ 0.5 A
0.605
0.617
V
0.580
0.605
0.630
V
VIN 0.2
V
TJ = 125°C
-2
2
%
TJ = 210°C
-4.2
4.2
%
0.07
%/V
-0.07
(2)
%/A
0.5
3
0.2
0.6
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 125°C (2)
0.2
1
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 210°C (2)
0.84
3
(2)
0.5
3
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 25°C (2)
0.2
0.6
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 125°C (2)
0.2
1
(2)
0.84
3
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = -55°C
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 210°C
DC output load
regulation
0.01
0.0125
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 25°C
ΔVO
V
0.593
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = -55°C (2)
DC input line
regulation
VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = -55°C (2)
0.05
VOUT = 0.8 V, 0 ≤ILoad ≤ 0.5 A, TJ = 25°C (2)
0.05
VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 125°C (2)
0.07
(2)
0.51
VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 210°C
VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = -55°C (2)
0.10
VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 25°C (2)
0.04
(2)
0.05
VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 210°C (2)
0.47
55.5
VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 125°C
VDO
Dropout voltage
IOUT = 0.5 A, VOUT = 6.8 V, VIN = VOUT + 0.1 V
Programmable
output current limit
range
VIN = 1.5 V, VOUT = 1.2 V, PCL resistance = 47 kΩ
ICL
VIN = 1.5 V, VOUT = 1.2 V , PCL resistance varies
VCS
Operating voltage
range at CS
CSR
Current sense ratio ILOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V
IGND
GND pin current
VIN = 1.5V, VOUT = 1.2 V, IOUT = 0.5 A
IQ
Quiescent current
(no load)
ISHDN
UNIT
7
TJ = 210°C
0.8
IOUT ≤ 0.5 A, 1.5 V ≤ VIN ≤ 7 V, VOUT = 6.8 V (1)
MAX
TJ = 125°C
Output voltage range
Output voltage
accuracy
ΔVO
TYP
1.5
mV
mV
100
mV
500
700
mA
200
700
mA
0.3
VIN
V
13
20
mA
VIN = VOUT + 0.5 V, IOUT = 0 A
12
17
mA
Shutdown current
VEN < 0.5 V, 0.8 V ≤ VIN ≤ 7 V
15
4500
µA
ISNS, IFB
FB/SNS pin
current
VIN = 7 V, VOUT = 6.8 V
1
10
nA
IEN
EN pin input
current
VIN = 7 V, VEN = 7 V
6.75
610
nA
VILEN
EN pin input low
(disable)
0.30 x
VIN
V
VIHEN
EN pin input high
(enable)
0.75 x
VIN
V
Eprop Dly
Enable pin
propagation delay
(1)
(2)
VIN = 2.2 V, EN rise to IOUT rise
47394
650
1000
µs
Based upon using 0.1% resistors.
Line and load regulations done under pulse condition for T < 10 ms.
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TPS7H1101-SP
TPS7H1201-HT
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
www.ti.com
TPS7H1201 ELECTRICAL CHARACTERISTICS (continued)
1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.3 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, over
operating temperature range (TJ = -55°C to 210°C), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.4
1.6
UNIT
TEN
Enable pin turn-on
delay
VIN = 2.2 V, VOUT = 1.8 V, ILOAD = 0.5 A, COUT = 220 μF,
CSS = 2 nF
VTHPG
PG threshold on
No load,VOUT = 1.2 V and VOUT = 6.8 V
VTHPGHYS
PG hysteresis
1.5 V ≤ VIN ≤ 7 V
2
VOLPG
PG pin output low
IPG = 0 to -1 mA
73
300
mV
ILKGPG
PG pin leakage
current
VOUT > VTHPG, VPG = 7 V
0.02
20
µA
ISS
SS pin current
VIN = 1.5 V to 7 V
2.5
6.3
µA
PSRR
Power-supply
rejection ratio
VIN = 2.5 V, VOUT = 1.8 V, COUT = 220 μF
VN
Output noise
voltage
BW = 10 Hz to 100 kHz, IOUT = 500 mA, VIN = 2 V, VOUT = 1.8 V
TJ
Operating junction
temperature
6
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84
90
1 kHz
45
100 kHz
20
%
%
dB
20.26
-55
ms
µVRMS
210
°C
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Product Folder Links: TPS7H1101-SP TPS7H1201-HT
TPS7H1101-SP
TPS7H1201-HT
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SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
TPS7H1101 ELECTRICAL CHARACTERISTICS
1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, over
operating temperature range (TJ = -55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
VFB
Feedback pin voltage
VOUT
Output voltage range
Output voltage accuracy
TEST CONDITIONS
1.5 V ≤ VIN ≤ 7 V
0 A ≤ IOUT ≤ 3 A, 1.5 V ≤ VIN ≤ 7 V,
VOUT = 0.8 V, 1.2 V, 1.8 V, 6.65 V (2)
(1)
Line regulation
1.5 V ≤ VIN ≤ 7 V
ΔVOUT%/
ΔIOUT
Load regulation
0.8 V ≤ VOUT ≤ 6.65 V, 0 ≤ ILoad ≤ 3 A
(1)
(2)
(3)
TYP
1.5
ΔVOUT%/
ΔVIN
ΔVI
MIN
DC input line regulation
0.594
UNIT
7
V
0.616
V
0.8
VIN - 0.35
V
-2
2
%
-0.07
0.605
MAX
0.01
0.07
0.08
%/V
%/A
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V,
IOUT = 10 mA, TJ = -55°C (3)
0.5
3
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V,
IOUT = 10 mA, TJ = 25°C (3)
0.2
0.6
1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V,
IOUT = 10 mA, TJ = 125°C (3)
0.2
1.0
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V,
IOUT = 10 mA, TJ = -55°C (3)
0.5
3.0
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V,
IOUT = 10 mA, TJ = 25°C (3)
0.2
0.6
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V,
IOUT = 10 mA, TJ = 125°C (3)
0.2
1.0
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.8 V,
IOUT = 10 mA, TJ = -55°C (3)
0.5
3.0
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.8 V,
IOUT = 10 mA, TJ = 25°C (3)
0.2
0.6
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.8 V,
IOUT = 10 mA, TJ = 125°C (3)
0.2
1.0
mV
The output voltage accuracy of condition at IOUT = 2 A and IOUT = 3 A is specified by characterization , but not production tested.
Based upon using 0.1% resistors.
Line and load regulations done under pulse condition for T < 10 ms.
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TPS7H1101-SP
TPS7H1201-HT
SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
www.ti.com
TPS7H1101 ELECTRICAL CHARACTERISTICS (continued)
1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, over
operating temperature range (TJ = -55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TYP
MAX
VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5)
TEST CONDITIONS
MIN
0.4
1.0
VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5)
0.6
1.1
VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5)
0.8
1.3
VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5)
0.8
1.8
VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5)
1.3
1.8
VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C
1.6
2.4
VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5)
1.1
1.9
VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5)
1.9
2.6
VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C
2.5
3.4
0.3
1.2
VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5)
0.5
1.3
(5)
0.6
1.3
VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5)
0.8
1.6
VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5)
1.1
2.1
VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5)
1.5
2.1
VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C
DC output load regulation (4)
(5)
VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5)
VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C
ΔVO
(5)
(5)
1.0
1.7
VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5)
1.1
2.4
VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5)
2.2
3.5
0.1
0.9
VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5)
0.3
0.9
VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5)
0.4
1.2
VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C
VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C
(5)
(5)
1.4
2.4
VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5)
0.7
1.4
VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5)
0.6
1.9
VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5)
2.5
3.9
VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C
(5)
1.2
2.1
VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5)
1.2
2.5
VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5)
1.5
2.9
VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C
(5)
0.4
2.6
VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5)
2.8
3.5
VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5)
3.5
5.9
VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C
(5)
1.1
4.7
VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5)
5.8
8.0
VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5)
5.6
9.3
VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5)
3.7
8.0
VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C
VDO
ICL
VCS
(4)
(5)
(6)
8
(5)
13.0
25
Worst case dropout voltage (4) IOUT = 3 A, VOUT = 1.3 V, VIN = VOUT + VDO
210
335
Dropout voltage (4)
196
Programmable output current
limit range
IOUT = 3 A, VOUT = 1.8 V, VIN = VOUT + VDO
UNIT
mV
mV
VIN = 1.5 V, VOUT = 1.2 V , PCL resistance =
47 kΩ
500
750
mA
VIN = 1.5 V, VOUT = 1.2 V , PCL resistance
varies
200
3500 (6)
mA
0.3
VIN
Operating voltage range at
CS
V
The parameter is guaranteed to the limit specified by characterization, but not production tested.
Line and load regulations done under pulse condition for T < 10 ms.
The maximum limit of the ICLparameter is guaranteed to the limit specified by characterization, but not production tested.
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SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
TPS7H1101 ELECTRICAL CHARACTERISTICS (continued)
1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, over
operating temperature range (TJ = -55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CSR
Current sense ratio
ILOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V
47394
IGND
GND pin current
VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A
10
16
mA
IQ
Quiescent current (no load)
VIN = VOUT + 0.5 V, IOUT = 0 A
7
10
mA
26
230
µA
1400
µA
1
5
nA
20
150
nA
1.5 V ≤ VIN ≤ 7 V
ISHDN
Shutdown current
1.5 V ≤ VIN ≤ 7 V, Post 100kRads (si), TJ =
25°C (7)
ISNS, IFB
FB/SNS pin current
VIN = 7 V, VOUT = 6.65 V
IEN
EN pin input current
VIN = 7 V, VEN = 7 V, VOUT = 6.65 V
VILEN
EN pin input low (disable)
3.5 V < VIN < 7 V
0.30 x VIN
VIHEN
EN pin input high (enable)
3.5 V < VIN < 7 V
0.75 x VIN
Eprop Dly
Enable pin propagation delay
VIN = 2.2 V, EN rise to IOUTrise
650
1000
µs
TEN
Enable pin turn-on delay
VIN = 2.2 V, VOUT = 1.8 V, ILOAD = 1 A,
COUT = 220 µF, CSS = 2 nF
1.4
1.6
ms
VTHPG
PG threshold
No load, 0.8 V ≤ VOUT ≤ 6.65 V
VTHPGHYS
PG hysteresis
1.5 V ≤ VIN ≤ 7 V
VOLPG
PG pin output low
IPG = 0 to -1 mA
120
300
mV
ILKGPG
PG pin leakage current
VOUT > VTHPG, VPG = 7 V
0.5
2.5
µA
ISS
SS pin charge current
VIN = 1.5 V to 7 V
2.5
3.5
µA
ISSdisb
SS pin disable current
VIN = 1.5 V to 7 V
10
µA
VSS
SS pin voltage (device
enabled) (8)
VIN = 1.5 V to 7 V
1.2
V
VSSdisb
SS pin low level input voltage
to disable device
VIN = 1.5 V to 7 V
PSRR
Power-supply rejection ratio
VIN = 2.5 V, VOUT = 1.8 V,
COUT = 220 µF
VN
Output noise voltage
BW = 10 Hz to 100 kHz,
IOUT = 3 A, VIN = 2 V, VOUT = 1.8 V
TSD
Thermal shutdown
temperature
TJ
Operating junction
temperature
(7)
(8)
86
V
V
90
%
2
%
0.4
1 kHz
48
100 kHz
25
V
dB
20.33
µVRMS
185
-55
°C
125
°C
This maximum limit applies to SMD 5962R13202 post 100kRads (Si) test at 25°C.
Any external pull up voltage should not exceed 1.2 V.
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PIN ASSIGNMENTS
HKS PACKAGE
(TOP VIEW)
FB
16
1
SS
COMP
15
2
EN
VOUT
14
3
VIN
VOUT
13
4
VIN
5
VIN
Thermal Pad
(Top Side)
VOUT
12
VOUT
11
6
VIN
CS
10
7
PCL
PG/OC
9
8
GND
HKR PACKAGE
(TOP VIEW)
10
SS
1
16
FB
EN
2
15
COMP
VIN
3
14
VOUT
VIN
4
13
VOUT
12
VOUT
Thermal Pad
(Bottom Side)
VIN
5
VIN
6
11
VOUT
PCL
7
10
CS
GND
8
9
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PG/OC
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Table 1. PIN FUNCTIONS
PIN
NAME
VIN
DESCRIPTION
No.
3, 4, 5, 6
VOUT
11, 12, 13, 14
Unregulated supply voltage. It’s recommended to connect an input capacitor as a good analog circuit practice.
Regulated output.
FB
16
The output voltage feedback input through voltage dividers. See Feedback Circuit section.
GND
8
Ground/Thermal Pad (1)
EN
2
Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disable the device; VIN
voltage must be greater than 3.5 V.
For VIN less than 3.5 V, enable pin cannot be used to disable the device. It is recommended to connect the
enable pin to VIN.
CS
10
Current sense pin. Resistor connected from CS to VIN. CS pin indicates voltage proportional to output current.
CS pin low: Foldback current limit disabled (Apply for TPS7H1101-SP only)
CS pin high: Foldback current limit enabled (Apply for TPS7H1101-SP only)
SS
1
SoftStart pin. Connecting an external capacitor slows down the output voltage ramp rate after enable event.
The SoftStart pin can be used to disable the device as described in SoftStart section.
PG/OC
9
PowerGood pin. PG is open drain output to indicate the output voltage reaches to 90% of target. PG pin is
also used as indicator when over current condition is activated.
PCL
7
Programmable current limit. A resistor to GND sets the over current limit activation point.
The range of resistor that can be used on the PCL pin to GND is 47kΩ to 160 kΩ (TPS7H1201-HT).
The range of resistor that can be used on the PCL pin to GND is 8.2 kΩ to 160 kΩ (TPS7H1101-SP).
COMP
15
Output of error amplifier
(1)
Thermal Pad must be connected to GND
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CS
Rcs
Vcs Voltage proportional
to Output current
CS
Vout
Vin
PMOS
Rt
2mA
Vref=1.2V
PCL
OCP
Rb
EN
Vref
Vref/2
Thermal
Protection
Rpcl
Iss
SS
+
+
Vfb
Css
Comp
0.6V
1.1Vfb
+
PG
0.9Vfb
+
-
Figure 1. Functional Block Diagram
12
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TPS7H1X01 DETAILED DESCRIPTION
TPS7H1101 Overview
The TPS7H1101 is 3A, 1.5-V to 7-V low dropout (LDO) linear regulator that uses PMOS pass element
configuration.
It uses TI’s proprietary process to achieve low noise, high PSRR combined with high thermal performance in a
16-pin ceramic flatpack package (HKR).
A number of features are incorporated in the design to provide high reliability and system flexibility. Current
foldback, overload, current limit and thermal protection are incorporated in the design to make it viable for harsh
environments.
A resistor connected from the CS (current sense) pin to VIN indicates voltage proportional to the output current.
When CS is held high, foldback current limit is enabled. Shorting CS low will disable the foldback current limit.
A resistor connected from programmable current limit (PCL) pin to ground sets the over current limit activation
point. When over current limit activation point is reached, it results in LDO going into current foldback mode.
Output current is reduced to approximately 50% of the current limit set point.
TPS7H1101 incorporates thermal protection which disables the output when the junction temperature rises
approximately 185°C, allowing the device to cool. Depending on the power dissipation, thermal resistance and
ambient temperature, the thermal protection wil turn on. Cycling limits the dissipation of the regulator, protecting
it from damage as a result of overheating.
The device also has a current sense monitoring feature. A resistor connected from the CS (current sense) pin to
VIN indicates voltage proportional to the output load current. A detailed description of this feature is provided in
Programmable Current Limit (PCL) section.
In order to provide system flexibility for demanding current needs, the LDO can be configured in parallel
operation as indicated in Figure 31. Detailed parallel operation is provided in the Current Sharing section.
An enable feature is incorporated in the design allowing one to enable or disable the LDO. Power Good, an open
drain connection, indicates the status of the output voltage. These provide the customers system flexibility in
monitoring and controlling the LDO operation. When using Enable function, VIN voltage must be greater than
3.5 V. For VIN from 1.5 V to 7 V, TPS7H1101 can be disabled using SoftStart (SS) pin as described in
Enable/Disable section.
TPS7H1201 Overview
The TPS7H1201 is a 0.5A , 1.5-V to 7-V low dropout (LDO) linear regulator that uses PMOS pass element
configuration.
It uses TI’s proprietary process to achieve low noise, high PSRR combined with high thermal performance in a
16-pin ceramic flatpack package (HKS).
A number of features are incorporated in the design to provide high reliability and system flexibility. Overload
protection is incorporated in the design to make it viable for harsh environments.
A resistor connected from programmable current limit (PCL) pin to ground sets the current limit activation point.
When current limit activation point is reached, output voltage drops while output load current is maintained at
current limit point.
The device also has a current sense monitoring feature. A resistor connected from the CS (current sense) pin to
VIN indicates voltage proportional to the output load current. A detailed description of this feature is provided in
Programmable Current Limit (PCL) section.
In order to provide system flexibility for demanding current needs, the LDO can be configured in parallel
operation as indicated in Figure 31. Detaled parallel operation is provided in the Current Sharing section.
An enable feature is incorporated in the design allowing one to enable or disable the LDO. Power Good, an open
drain connection, indicates the status of the output voltage. These provide the customers system flexibility in
monitoring and controlling the LDO operation. When using Enable function, VIN voltage must be greater than
3.5 V. For VIN from 1.5 V to 7 V, TPS7H1201 can be disabled using SoftStart (SS) pin as described in
Enable/Disable section.
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TYPICAL CHARACTERISTICS (TPS7H1201-HT)
Feedback Voltage
vs.
Temperature
Quiescent Current
vs.
Temperature
16
0.624
VIN = 1.5 V
Quiescent Current (mA)
Feedback Voltage (V)
0.620
0.616
0.612
0.608
14
12
10
0.604
Vin
= 7.0V
V
IN = 7.5 V
0.600
Vin
= 1.5
1.5V
V
V
IN =
8
±55
15
±20
50
85
120
155
190
Junction Temperature (ƒC)
225
±75 ±50 ±25
0
25
50
75 100 125 150 175 200 225
Junction Temperature (ƒC)
C004
Figure 2.
Figure 3.
Ground Current
vs.
Temperature
Dropout Voltage
vs.
Temperature
C005
80
16
Dropout Voltage (mV)
Ground Current (mA)
Load = 0.5 A
14
12
10
60
40
Load = 0.5 A
No Load
8
±55 ±30
±5
20
45
70
95
Junction Temperature (ƒC)
3,500
±75 ±50 ±25
0
25
50
75 100 125 150 175 200 225
Junction Temperature (ƒC)
C006
Figure 4.
Figure 5.
Shutdown Current
vs.
Temperature
PG Threshold
vs.
Temperature
C007
100
Vin
= 7.5
7.0V
V
V
IN =
VOUT = 6.8 V
V
V
Vin
= 1.5
1.5V
IN =
95
2,500
PG Threshold (%)
Shutdown Current (uA)
3,000
20
120 145 170 195 220
2,000
1,500
1,000
90
85
500
0
80
±75 ±50 ±25
0
25
50
75 100 125 150 175 200 225
Junction Temperature (ƒC)
±75 ±50 ±25
0
Figure 6.
14
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25
50
75 100 125 150 175 200 225
Junction Temperature (ƒC)
C008
C009
Figure 7.
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SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (TPS7H1201-HT) (continued)
Power Supply Ripple Rejection
vs.
Frequency
IOUT = 250 mA
Power Supply Ripple Rejection
vs.
Frequency
IOUT = No Load
0
0
IOUT = 250 mA
±20
±20
±30
±30
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
10
100
IOUT = No Load
±10
PSRR (dB)
PSRR (dB)
±10
1k
10k
100k
1M
Frequency (Hz)
10
100
1k
10k
100k
Frequency (Hz)
C012
Figure 8.
1M
C011
Figure 9.
Load Regulation
vs.
Temperature
0.4
VVout
V
= 0.8
0.8V
OUT =
Load Regulation (uA)
6.8V
VVout
OUT ==6.8
0.3
0.2
0.1
0.0
±75 ±50 ±25
0
25
50
75 100 125 150 175 200 225
Junction Temperature (ƒC)
C010
Figure 10.
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TYPICAL CHARACTERISTICS (TPS7H1101-SP)
Feedback Voltage
vs.
Temperature
Quiescent Current
vs.
Temperature
0.608
10
Quiescent Current (mA)
Feedback Voltage (V)
0.607
0.606
0.605
VIN = 1.5 V
0.604
0.603
9
8
VIN = 7 V
7
VIN = 1.5 V
6
VIN = 7 V
0.602
-55
5
-35
-15
5
25
45
65
85
105
±55
125
±35
±15
25
45
Figure 11.
Figure 12.
Ground Current
vs.
Temperature
Dropout Voltage
vs.
Temperature
65
85
105
125
C014
320
13
12
Load = 2 A
280
11
Dropout Voltage (mV)
Ground Current (mA)
5
Junction Temperature (ƒC)
Junction Temperature (°C)
10
9
No Load
8
7
Load = 3 A
240
200
160
6
5
±55
±35
±15
5
25
45
65
85
105
Junction Temperature (ƒC)
125
120
-55
-15
5
25
45
65
Junction Temperature (°C)
Figure 13.
Figure 14.
Shutdown Current
vs.
Temperature
PG Threshold
vs.
Temperature
80
95
PG Threshold (%)
VIN = 7 V
60
40
VIN = 1.5 V
20
105
85
105
125
VOUT = 6.8 V
90
85
0
80
±55
±35
±15
5
25
45
65
Junction Temperature (ƒC)
85
105
125
±55
±35
±15
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5
25
45
65
Junction Temperature (ƒC)
C017
Figure 15.
16
85
100
100
Shutdown Current (uA)
-35
C015
125
C018
Figure 16.
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SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
APPLICATION INFORMATION
Adjustable Output Voltage (Feedback Circuit)
The Output voltage of the TPS7H1101-SP can be set to user programmable level between 0.8 V and 6.65 V.
The Output voltage of the TPS7H1201-HT can be set to user programmable level between 0.8 V and 6.8 V.This
can be achieved by using a resistor divider connected between VOUT, FB and GND pins. RTOP connected
between VOUT and VFB and RBOTTOM being connected between VFB and GND.
VOUT can be determined by using Equation 1.
(RTOP + RBOTTOM) · VFB
VOUT = ¾
RBOTTOM
(1)
Where VFB = 0.605 V.
Table 2. Resistor Values for Typical Voltages
VOUT
RTOP
RBOTTOM
0.8 V
10 kΩ
30.1 kΩ
1V
10 kΩ
15 kΩ
1.2 V
10 kΩ
10 kΩ
1.5 V
15 kΩ
10 kΩ
1.8 V
20 kΩ
10 kΩ
2.5 V
32 kΩ
10.1 kΩ
3.3 V
45.9 kΩ
10.2 kΩ
4V
59 kΩ
10.4 kΩ
5V
77.7 kΩ
10.6 kΩ
5.5 V
78.7 kΩ
9.65 kΩ
6V
78.7 kΩ
8.75 kΩ
6.5 V
78.7 kΩ
7.96 kΩ
6.6 V
79.6 kΩ
7.96 kΩ
6.7 V
78.7 kΩ
7.77 kΩ
Programmable Current Limit (PCL)
Programmable current limit resistor, Rpcl, sets the over current limit activation point and can be calculated per
Rpcl = ( CSR * Vref )/ (ICL - 0.0403),
Where Vref = 0.605 V, ICL = programmable current limit (A) and Current Sense Ratio (CSR) is the ratio of Output
Load Current to ICS.The typical value of the CSR is 47394.
Figure 17 shows the the Output Load Current (IOUT) versus PCL pin current (ICL)
A suitable resistor Rpcl must be chosen to ensure the CS pin is within its operating range of 0.3 V to VIN.
For TPS7H1201-HT, the maximum programmable current limit is 700 mA. The range of resistor that can be used
on the PCL pin to GND is 47 kΩ to 160 kΩ.
For TPS7H1101-SP, the maximum programmable current limit is 3.5 A. The range of resistor that can be used
on the PCL pin to GND is 8.2 kΩ to 160 kΩ.
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4.5
4.0
Output Current (A)
3.5
3.0
2.5
2.0
1.5
1.0
VIN = 2.3 V
VOUT = 1.8 V
y = 47394x + 0.0403
0.5
0.0
0
10
20
30
40
50
60
70
80
90
100
PCL Pin Current (µA)
C001
Figure 17. IOUT (A) vs IPCL (µA)
High Side Current Sense
The relatinoship between the SoftStart (SS) current andd RCS is shown in the formulas below. A suitable value of
RCS should be selected hence VCS is within the votlage as specified in the electrical characteristics table.
Iload
ICS = ¾¾
CSR
VIN - VCS
RCS = ¾¾
ICS
(2)
(3)
Iload is the output load current
CSR is the current sense ratio
For TPS7H1101-SP, Figure 20 shows typical curve VCS vs IOUT for Vin = 2.28 V and RCS = 3.65 kΩ. A resistor
connected from current sense (CS) pin to VIN indicates voltage proportional to the output current.
2.35
VIN = 2.3 V
VOUT = 1.8 V
y = 0.078x + 2.2853
CS Pin Voltage (V)
2.30
2.25
2.20
2.15
2.10
2.05
2.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Load Current (A)
C003
Figure 18. VCS (V) vs IOUT (A) (TPS7H1101-SP)
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Monitoring current in CS pin (ICS vs IOUT) indicates the current sense ratio (CSR) between the main PMOSFET
and the current sense MOSFET as shown in Figure 21.
4
VIN = 2.3 V
VOUT = 1.8 V
Output Current (A)
3
3
2
2
Ics (A) - 0.3 V
y = 48150x - 0.1926
Ics (A) - 2.3 V
y = 47935x - 0.1865
Ics (V) - 5 V
y = 48061x - 0.1899
1
1
0
0
10
20
30
40
50
60
70
CS Pin Current (µA)
80
C002
Figure 19. IOUT (A) vs ICS (A) (TPS7H1101-SP)
For TPS7H1201-HT, monitoring the voltage at the CS pin will indicate voltage proportional to the output current.
Figure 20 shows typical curve VCS vs IOUT for VIN = 2.28 V and RCS = 3.65 kΩ.
2.290
y = -0.0732x + 2.2804
CS Pin Voltage (V)
2.280
2.270
2.260
2.250
2.240
2.230
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Output Current (A)
C002
Figure 20. VCS (V) vs IOUT (A) (TPS7H1201-HT)
Monitoring current in CS pin (ICS vs IOUT) indicates the current sense ratio between the main PMOSFET and the
current sense MOSFET as shown in Figure 21.
0.7
Output Current (A)
0.6
0.5
0.4
0.3
0.2
0.1
y = 49917x - 0.2466
0
0.00E+00
5.00E-06
1.00E-05
1.50E-05
2.00E-05
CS Pin Current (A)
C003
Figure 21. IOUT (A) vs ICS (A)
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TPS7H1101-SP
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Figure 22 shows IOUT vs ICS when the voltage on CS pin is varied from 0.3 V to 7 V.
0.6
VIN = 2.3V
VOUT = 1.8V
Output Current (A)
0.5
0.4
0.3
0.2
0.3V
2.3V
5V
7V
0.1
0.0
0
2
4
6
8
10
12
14
16
CS Pin Current (A)
Figure 22. IOUT (A) vs ICS (A) (TPS7H1201-HT)
Current Foldback
1. The TPS7H1101-SP has Current Foldback feature which can be enabled when Current Sense (CS) pin is
held high, Shorting CS low will disable the foldback current limit.
2. With foldback current limit enabled, when current limit trip point is activated,
(a) Output voltage will drop low
(b) output current will fold back to approx. 50% of the current limit trip point.
This results in minimizing the power loss under fault conditions. Monitoring the voltage at the CS pin will
indicate voltage proportional to the output current.
Power Good (PG)
Power good pin is an open drain connection, connect it high via pull up resistor to external voltage source. Power
Good pin indicates the status of the output voltage.
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Transient Response
For TPS7H1101-SP, waveforms below indicate the transient response behavior of the LDO for 50% step load
change.
Channel 1: Output voltage overshoot / undershoot
Channel 2: Step load in current
Channel 3: Input voltage
Figure 23. Load Transient Response:
Step Load 0.1 A to 1.6 A, VIN = 2.3 V, VOUT = 1.8 V (TPS7H1101-SP)
Figure 24. Expanded View Overshoot
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Figure 25. Expanded View Undershoot
Waveforms below indicate the transient response behavior of the TPS7H1201-HT.
Figure 26. Load Transient Response: Step Load 0 A to 250 mA, VIN = 2.3 V, VOUT = 1.8 V (TPS7H1101-SP)
Figure 27. Expanded View Overshoot
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Figure 28. Expanded View Undershoot
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TPS7H1101-SP
TPS7H1201-HT
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Current Sharing
For demanding load requirements, multiple LDOs can be paralleled as indicated in Figure 31 below. In parallel
mode CS pin of LDO#1 must be connected to PCL pin of LDO#2 via a series resistor RCL and CS pin of LDO#2
must be connected to PCL pin of LDO#1 via series resistor RCL. Typical value of RCL in parallel operation is
3.75Kohm for current limit > 6A. In parallel configuration, RCL (resistor from PCL to GND) and RCS (resistor from
CS pin to VIN) must be left open (unpopulated). The RCL value needs to be selected so that the operating
condition of CS pin is maintained, as specified in the electrical characteristics table. The current from PCL
through RCL of LDO1 is determined by the output load current of LDO2 divided by the Current Sense Ratio
(CSR). Hence, the voltage at CS pin of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458) / CSR *
RCL). Typical Value of RCL is 3.65 Kohm. This parallel configuration will provide higher reliability (MTBF) for
system needs due to reduced stress on the components, as the load current will be shared between the two
LDOs.
Alternately, it can also provide twice the output current to meet system needs. When using two LDOs in parallel
operation for higher output load current, use POL TPS50x01 as an input source.
65.00
LDO1
LDO2
60.00
% of total Load
55.00
50.00
45.00
40.00
35.00
0
1
2
3
4
5
6
Output Current
Figure 29. LDO Current Share (TPS7H1101-SP)
55.00
LDO1
LDO2
54.00
53.00
% of Total Load
52.00
51.00
50.00
49.00
48.00
47.00
46.00
45.00
0.2
0.4
0.6
0.8
1
Output Current
Figure 30. LDO Current Share (TPS7H1201-HT)
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SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013
Rpg
Ccomp
Vref
+
PG
+ SS
- FB
Comp
Vout
LDO1
Rt
CS
PCL
RLoad
Cout
Rcl
Rcl
Rcl
Optional
Rb
Cx
Ccomp
Vref
+
+ SS
CS
PCL
Comp
LDO2
- FB
PG
Css
Rpg
Cout
Figure 31. Functional Block Diagram (Parallel Operation)
Soft-Start
Connecting a capacitor on CS pin to GND (CSS) slows down the output voltage ramp rate. The soft-start
capacitor will charge up to 1.2 V.
tSS · ISS
CSS = ¾
VFB
(4)
Where:
tss = Soft-start time
Iss = 2.5 µA
VFB = VREF / 2 = 0.605 V
Enable/Disable
For Vin from 1.5 V to 7 V, TPS7H1x01 can be disabled using SoftStart (SS) pin. The minimum SoftStart pull
down current is 10 μA, with soft-start to ground voltage of 400 mV or lower. External voltage applied to SoftStart
(SS) pin must be limited to 1.2 V maximum. Removing the logic low condition on SoftStart shall enable the
device allowing the SoftStart capacitor to get charged by the internal current source. Alternatively, for VIN greater
than 3.5 V, the device can be disabled by pulling the enable pin to logic low. In all other cases, the enable pin
should be connected to VIN.
Output Noise
Output noise is measured using HP3495A. Plots below shows noise of the TPS7H1101-SP and TPS7H1201-HT
in µV/√Hz vs Frequency
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Noise (µV/√Hz)
10
1
0.1
0.01
10
100
1,000
10,000
100,000
Frequency (Hz)
Figure 32. TPS7H1101-SP - RMS Noise (10 Hz - 100 kHz) = 20.33 µVrms, VIN = 2 V, VOUT = 1.8 V at 3 A, ,
CIN = 220uF, CLOAD = 220uF
10
Noise ( μ V/√Hz)
1
0.1
0.01
10
100
1000
10000
100000
Frequency (Hz)
Figure 33. TPS7H1101-SP - RMS Noise (10 Hz - 100 kHz) = 31.68 μVrms, VIN = 7 V, VOUT = 6.7 V at Iload = 3
A, CIN = 220 uF, CLOAD = 220 uF
10
Noise (µV/√Hz)
1
0.1
0.01
10
100
1000
10000
100000
Frequency (Hz)
Figure 34. TPS7H1201-HT - RMS Noise (10 Hz - 100 kHz) = 20.26 μVrms, VIN = 2.1 V, VOUT = 1.8 V at Iload =
0.5 A, CIN = 220 uF, CLOAD = 220 uF
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10
Noise (µV/√Hz)
1
0.1
0.01
10
100
1000
10000
100000
1000000
Frequency (Hz)
Figure 35. TPS7H1201-HT - RMS Noise (10 Hz - 100 kHz) = 31 μVrms, VIN = 7 V, VOUT = 6.7 V at Iload = 0.5
A, CIN = 220 uF, CLOAD = 220 uF
Capacitors
TPS7H1X01 requires the use of a combination of tantalum and ceramic capacitors to achieve good volume to
capacitance ratio. Table 3 highlights some of the capacitors used in the device. It is recommended that proper
derating guidelines as recommended by capacitor manufacturer be followed based upon output voltage and
operating temperature.
Note polymer based tantalum capacitors must be derated to at least 60% of rated voltage, whereas manganese
oxide (MnO2) based tantalum capacitors should be derated to 33% of rated voltage depending upon the
operating temperature.
It is recommended to use a tantalum capacitor along with a 0.1µF ceramic capacitor for improved performance.
The device is stable for input and output tantalum capacitor values of 10 µF to 220 µF with the ESR range of
10 mΩ to 2 Ω. However the dynamic performance of the device will vary based on load conditions and the
capacitor values used.
It is important to ensure that good design layout practice be followed to ensure that the traces connecting VIN to
GND pins of LDO and VOUT to GND pins of LDO should be kept short to reduce inductance. Trace length should
be no longer than 5 cm.
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Table 3. TPS7H1x01 Capacitors
Capacitor Part Number
Capacitor Details
(Capacitor, Voltage, ESR)
Type
Vendor
T493X226M025AH6x20 (1)
22 µF, 25 V, 35 mΩ
Tantalum - MnO2
Kemet
T525D476M016ATE035
(1)
47 µF, 10 V, 35 mΩ
Tantalum - Polymer
Kemet
T525D107M010ATE025 (1)
100 µF, 10 V, 25 mΩ
Tantalum - Polymer
Kemet
T541X337M010AH6720 (1)
330 µF, 10 V, 6 mΩ
Tantalum - Polymer
Kemet
T525D227M010ATE025
(1)
220 µF, 10 V, 25 mΩ
Tantalum - Polymer
Kemet
T495X107K016ATE100 (1)
100 µF, 16 V, 100 mΩ
Tantalum - MnO2
Kemet
CWR29FK227JTHC (1)
220 µF, 100 V, 180 mΩ
Tantalum - MnO2
AVX
THJE107K016AJH
100 µF, 16 V, 58 mΩ
Tantalum
AVX
THJE227K010AJH
220 µF, 10 V, 40 mΩ
Tantalum
AVX
SMX33C336KAN360
33 µF, 25 V
Stacked ceramic
AVX
(1)
Operating temperature is -55°C to 125°C.
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REVISION HISTORY
Changes from Revision E (September 2013) to Revision F
Page
•
Added table note (1) to THERMAL INFORMATION ............................................................................................................. 4
•
Added sections to DETAILED DESCRIPTION ................................................................................................................... 18
•
Added Figure 35 ................................................................................................................................................................. 27
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-1320201VXC
ACTIVE
CFP
HKR
16
1
TBD
NIAU
N / A for Pkg Type
-55 to 125
5962-1320201VXC
TPS7H1101-SP
5962R1320201VXC
PREVIEW
CFP
HKR
16
1
TBD
NIAU
N / A for Pkg Type
-55 to 125
5962R1320201VXC
TPS7H1101-RHA
TPS7H1101HKR/EM
PREVIEW
CFP
HKR
16
TBD
NIAU
N / A for Pkg Type
25 Only
TPS7H1101HKREM
TPS7H1201SHKS
ACTIVE
CFP
HKS
16
TBD
Call TI
Call TI
-55 to 210
1
TPS7H1201SHKS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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