Keypad Decoder and I/O Expansion ADP5589 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 16-element FIFO for event recording 19 configurable I/Os allowing functions such as Keypad decoding for matrix up to 11 × 8 Key press/release interrupts Key pad lock/unlock GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open drain Dual programmable logic blocks PWM generator Internal PWM generation External PWM with internal PWM AND function Clock divider Reset generators I2C interface with fast-mode plus (Fm+) support up to 1 MHz Open-drain interrupt output 24-lead LFCSP 3.5 mm × 3.5 mm 25-ball WLCSP 1.99 mm × 1.99 mm GND VDD ADP5589 UVLO POR RST SDA OSCILLATOR I2C INTERFACE SCL INT R0 R1 KEY SCAN AND DECODE R2 R3 R4 R5 GPI SCAN AND DECODE R6 R7 C0 C1 C2 REGISTERS I/O CONFIG LOGIC 1 LOGIC 2 C3 C4 CLK DIV C5 C6 PWM C7 C8 Devices requiring keypad entry and I/O expansion capabilities RESET 1 GEN C9 C10 RESET 2 GEN 09714-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The ADP5589 is a 19 I/O port expander with built-in keypad matrix decoder, programmable logic, reset generator, and PWM generator. I/O expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs. need to monitor different registers for event changes. The ADP5589 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C compatible interface. The ADP5589, which handles all key scanning and decoding, can flag the main processor via an interrupt line when new key events have occurred. In addition, GPI changes and logic changes can be tracked as events via the FIFO, eliminating the The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, saving board area and cost. Rev. B The ADP5589 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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Technical Support www.analog.com ADP5589 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Event FIFO .....................................................................................9 Applications ....................................................................................... 1 Key Scan Control ...........................................................................9 Functional Block Diagram .............................................................. 1 GPO Output ................................................................................ 15 General Description ......................................................................... 1 Logic Blocks ................................................................................ 16 Revision History ............................................................................... 2 PWM Block ................................................................................. 17 Specifications..................................................................................... 3 Clock Divider Block ................................................................... 17 Absolute Maximum Ratings............................................................ 5 Reset Blocks ................................................................................ 17 Thermal Resistance ...................................................................... 5 Interrupts ..................................................................................... 18 ESD Caution .................................................................................. 5 Register Interface ............................................................................ 19 Pin Configuration and Function Descriptions ............................. 6 Register Map ................................................................................... 21 Quick Device Overview ................................................................... 7 Detailed Register Descriptions ................................................. 23 Device Enable................................................................................ 8 Application Diagram...................................................................... 48 Device Overview .......................................................................... 8 Outline Dimensions ....................................................................... 49 Detailed Description ........................................................................ 9 Ordering Guide .......................................................................... 49 REVISION HISTORY 1/13—Rev. A to Rev. B Changes to Detailed Register Descriptions Section and Table 7 .............................................................................................. 22 Changes to Table 33 and Table 34 ................................................ 29 Changes to Table 36 ........................................................................ 30 Changes to Table 37 ........................................................................ 31 Changes to Table 69 ........................................................................ 41 Changes to Table 84 ........................................................................ 46 Changes to Figure 31 ...................................................................... 48 8/11—Revision A: Initial Version Rev. B | Page 2 of 52 Data Sheet ADP5589 SPECIFICATIONS VDD = 1.8 V to 3.3 V, TA = −40°C to +85⁰C, unless otherwise noted. 1 Table 1. Parameter SUPPLY VOLTAGE VDD Input Voltage Range Undervoltage Lockout Threshold SUPPLY CURRENT Standby Current Operating Current (One Key Press) Symbol VDD UVLOVDD ISTNBY ISCAN = 10 ms ISCAN = 10 ms ISCAN = 10 ms ISCAN = 10 ms PULL-UP, PULL-DOWN RESISTANCE Pull-Up Option 1 Pull-Up Option 2 Pull-Down INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10) Logic Low Input Voltage Logic High Input Voltage Input Leakage Current (Per Pin) PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10) Logic Low Output Voltage 2 Logic Low Output Voltage 3 Logic High Output Voltage Logic High Leakage Current (Per Pin) OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA) Logic Low Output Voltage (INT) Logic Low Output Voltage (SDA) Logic High Leakage Current (Per Pin) Logic Propagation Delay FF1 Hold Time 4 FF1 Setup Time4 FF2 Hold Time4 FF2 Setup Time4 GPIO Debounce4 Internal Oscillator Frequency 5 I2C TIMING SPECIFICATIONS Delay from UVLO/Reset Inactive to I2C Access SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Test Conditions/Comments UVLO active, VDD falling UVLO inactive, VDD rising Min 1.65 1.2 VDD = 1.65 V VDD = 3.3 V CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 1.65 V CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 1.65 V CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 3.3 V CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 3.3 V 50 150 150 VIL VIH VI-Leak Typ Sink current = 10 mA Sink current = 10 mA Source current = 5 mA VOL VOL VOH-Leak ISINK = 10 mA ISINK = 20 mA 3.6 1.6 V V V 1 1 30 4 10 40 μA µA µA 35 45 µA 75 85 μA 80 90 μA 100 300 300 150 450 450 kΩ kΩ kΩ 0.1 0.3 × VDD V V 1 µA 0.4 0.5 0.7 × VDD 0.1 0.1 125 0 175 0 175 OSCFREQ 900 fSCL tHIGH tLOW tSU; DAT tHD; DAT tSU; STA 0 0.26 0.5 50 0 0.26 Rev. B | Page 3 of 52 Unit 1.3 1.4 0.7 × VDD VOL VOL VOH VOH-Leak Max 1000 1 0.4 0.4 1 300 70 1100 60 1000 V V V µA V V µA ns ns ns ns ns µs kHz µs kHz µs µs ns µs µs ADP5589 Data Sheet Parameter Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line Symbol tHD; STA tBUF tSU; STO tVD; DAT tVD; ACK tR tF tSP CB 6 Test Conditions/Comments Min 0.26 0.5 0.26 Typ Max 0.45 0.45 120 120 50 550 0 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V. Maximum of five GPIOs active simultaneously. 3 All GPIOs active simultaneously. 4 Guaranteed by design. 5 All timers are referenced from the base oscillator and have the same ±10% accuracy. 6 CB is the total capacitance of one bus line in picofarads. 1 2 tF tR tSU; DAT 70% 30% SDA 70% 30% tF tVD; DAT tHD; DAT tHIGH tR 70% 30% SCL 70% 30% 70% 30% tHD; STA S 70% 30% tLOW NINTH CLOCK 1/fSCL FIRST CLOCK CYCLE tBUF SDA tHD; STA tSU; STA tVD; ACK tSP tSU; STO 70% 30% Sr VIL = 0.3VDD P NINTH CLOCK VIH = 0.7VDD Figure 2. I2C Interface Timing Diagram Rev. B | Page 4 of 52 S 09714-002 SCL Unit µs µs µs µs µs ns ns ns pF Data Sheet ADP5589 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VDD to Ground SCL, SDA, RST, INT, R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 to Ground Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Soldering Conditions 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating –0.3 V to 4 V –0.3 V to (VDD + 0.3 V) Table 3. −40°C to +125°C Thermal Resistance 24-Lead LFCSP Maximum Power Dissipation 25-Ball WLCSP Maximum Power Dissipation −65°C to +150°C JEDEC J-STD-020 ESD CAUTION −40°C to +85°C1 In applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(MAX)) is dependent on the maximum operating junction temperature (TJ(MAXOP) = 125°C), the maximum power dissipation of the device (PD(MAX)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), using the following equation: TA(MAX) = TJ(MAXOP) − (θJA × PD(MAX)). Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to ground. Rev. B | Page 5 of 52 θJA 43.83 120 43 120 Unit C/W mW C/W mW ADP5589 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS R7 1 18 VDD R6 2 17 RST R5 3 ADP5589 16 C7 R4 4 TOP VIEW (Not to Scale) 15 C6 R3 5 14 C5 R2 6 09714-003 C3 12 C2 11 9 C0 C1 10 R0 8 R1 7 13 C4 1 2 3 4 5 A VDD SDA SCL GND C10 B R0 INT RST C0 C9 C R2 R1 C1 C2 C8 D R4 R3 C3 C4 C7 E R5 R6 R7 C5 C6 TOP VIEW (BALL SIDE DOWN) Not to Scale NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 3. LFCSP Pin Configuration 09714-104 19 C8 21 C10 20 C9 22 SDA 24 INT 23 SCL BALLA1 CORNER Figure 4. WLCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. (LFCSP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EP (pad) Pin No. (WLCSP) E3 E2 E1 D1 D2 C1 C2 B1 B4 C3 C4 D3 D4 E4 E5 D5 B3 A1 C5 B5 A5 A2 A3 B2 A4 Mnemonic R7 R6 R5 R4 R3 R2 R1 R0 C0 C1 C2 C3 C4 C5 C6 C7 RST VDD C8 C9 C10 SDA SCL INT GND Description GPIO 8. This pin functions as Row 7 if used as keypad. GPIO 7. This pin functions as Row 6 if used as keypad. GPIO 6. This pin functions as Row 5 if used as keypad. GPIO 5 (GPIO alternate function: RESET1). This pin functions as Row 4 if used as keypad. GPIO 4 (GPIO alternate function: LC1, PWM_OUT, or CLK_OUT. This pin functions as Row 3 if used as keypad. GPIO 3 (GPIO alternate function: LB1). This pin functions as Row 2 if used as a keypad. GPIO 2 (GPIO alternate function: LA1). This pin functions as Row 1 if used as a keypad. GPIO 1 (GPIO alternate function: LY1). This pin functions as Row 0 if used as a keypad. GPIO 9. This pin functions as Column 0 if used as keypad. GPIO 10. This pin functions as Column 1 if used as keypad. GPIO 11. This pin functions as Column 2 if used as keypad. GPIO 12. This pin functions as Column 3 if used as keypad. GPIO 13 (GPIO alternate function: RESET2). This pin functions as Column 4 if used as keypad. GPIO 14. This pin functions as Column 5 if used as keypad. GPIO 15 (GPIO alternate function: LC2, PWM_IN, or CLK_IN). This pin functions as Column 6 if used as keypad. GPIO 16 (GPIO alternate function: LB2). This pin functions as Column 7 if used as keypad. Input Reset Signal. Supply Voltage Input. GPIO 17 (GPIO alternate function: LA2). This pin functions as Column 8 if used as keypad. GPIO 18 (GPIO alternate function: LY2). This pin functions as Column 9 if used as keypad. GPIO 19. This pin functions as Column 10 if used as keypad. I2C Data Input/Output. I2C Clock Input. Open-Drain Interrupt Output. Ground. The exposed pad of the LFCSP package must be connected to ground. Rev. B | Page 6 of 52 Data Sheet ADP5589 QUICK DEVICE OVERVIEW VDD GND ADP5589 UVLO POR RST OSCILLATOR SDA I2C INTERFACE INT SCL (R0) (R1) (R2) (R3) (R4) (R5) (R6) (R7) (C0) (C1) (C2) (C3) (C4) (C5) (C6) (C7) (C8) (C9) (C10) R0 R1 R2 R3 R4 R5 R6 R7 C0 C1 C2 C3 C4 I/O CONFIGURATION ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9 COL 10 (R0) (R1) (R2) (R3) (R4) (R5) (R6) (R7) (C0) (C1) (C2) (C3) (C4) (C5) (C6) (C7) (C8) (C9) (C10) GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 (R1) (R2) (R3) LA1 LB1 LC1 (R0) LY1 (C8) (C7) (C6) LA2 (C9) LY2 (C6) CLK_IN (R3) CLK_OUT I2C BUSY? KEY EVENT GPI EVENT FIFO UPDATE LOGIC EVENT KEY SCAN AND DECODE GPI SCAN AND DECODE REGISTERS LOGIC 1 C5 C7 C8 C9 C10 LB2 LC2 (C6) PWM_IN (R3) PWM_OUT (R4) RESET1 (C4) RESET2 LOGIC 2 CLK DIV PWM RESET1 GEN RST RESET2 GEN 09714-004 C6 Figure 5. Internal Block Diagram Rev. B | Page 7 of 52 ADP5589 Data Sheet DEVICE ENABLE When sufficient voltage is applied to VDD and the RST pin is driven with a logic high level, the ADP5589 starts up in standby mode with all settings at default. The user can configure the device via the I2C interface. When the RST pin is low, the ADP5589 enters a reset state and all settings return to default. The RST pin features a debounce filter. DEVICE OVERVIEW The ADP5589 contains 19 multiconfigurable input/output pins. Each pin can be programmed to enable the device to carry out its various functions, as follows: • • • • • • Keypad matrix decoding (11-column by 8-row matrix maximum). General-purpose I/O expansion (up to 19 inputs/outputs). PWM generation. Clock division of externally supplied source. Dual logic function building blocks (up to three inputs, one output). Two reset generators. All 19 input/output pins have an I/O structure, as shown in Figure 6. VDD 100kΩ 300kΩ Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or pulled down with a 300 kΩ resistor. For logic output drive, each I/O has a 5 mA PMOS source and a 10 mA NMOS sink for push-pull type output. For open-drain output situations, the 5 mA PMOS source is not enabled. For logic input applications, each I/O can be sampled directly or, alternatively, sampled through a debounce filter. The I/O structure shown in Figure 6 allows for all GPI and GPO functions, as well as PWM and clock divide functions. For key matrix scan and decode, the scanning circuit uses the 100 kΩ or 300 kΩ resistor for pulling up keypad row pins and the 10 mA NMOS sinks for grounding keypad column pins (see the Key Scan Control section for details about key decoding). Configuration of the device is carried out by programming an array of internal registers via the I2C interface. Feedback of device status and pending interrupts can be flagged to an external processor via the INT pin. The ADP5589 is offered with three feature sets. Table 5 lists the options that are available for each model of the ADP5589. Table 5. Available Options Models ADP5589ACPZ-00-R7 ADP5589ACBZ-00-R7 ADP5589ACPZ-01-R7 ADP5589ACBZ-01-R7 ADP5589ACPZ-02-R7 ADP5589ACBZ-02-R7 Description All GPIOs pulled up (default option) Reset pass-through1 Pull-down on special function pins2 I/O Reset pass-through implies that the RESET1 output (R4) follows the logic level of the reset input pin, RST, after the oscillator has been enabled. 2 Special function pins are defined as R0 (Row 0), R3 (Row 3), R4 (Row 4), C4 (Column 4), C6 (Column 6), and C9 (Column 9). 1 300kΩ DEBOUNCE 09714-005 I/O DRIVE Figure 6. I/O Structure Rev. B | Page 8 of 52 Data Sheet ADP5589 DETAILED DESCRIPTION EVENT FIFO EC = 3 FIRST READ It is important to understand the function of the event FIFO. The ADP5589 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However, it is possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well. An event count, EC[4:0], is composed of five bits and works in tandem with the FIFO so that the user knows how much of the FIFO must be read back at any given time. KEY 3 PRESSED KEY 3 RELEASED GPI 7 ACTIVE EC = 2 SECOND READ KEY 3 RELEASED GPI 7 ACTIVE EC = 1 THIRD READ GPI 7 ACTIVE The FIFO is composed of 16 eight-bit sections that the user accesses by reading the FIFO_x registers. The actual FIFO is not in user accessible registers until a read occurs. The FIFO can be thought of as a “first in, first out” buffer used to fill Register 0x03 to Register 0x12. The event FIFO is made up of 16 eight-bit registers. In each register, Bits[6:0] hold the event identifier, and Bit 7 holds the event state. With seven bits, 127 different events can be identified. See Table 11 for event decoding. OVRFLOW_INT KEY EVENTS GPI EVENTS FIFO UPDATE EC[4:0] LOGIC EVENTS EVENT2[7:0] EVENT3[7:0] EVENT4[7:0] The FIFO registers (0x03 to 0x12) always point to the top of the FIFO (that is, the location of EVENT1[7:0]). If the user tries to read back from any location in a FIFO, data is always obtained from the top of that FIFO. This ensures that events can only be read back in the order in which they occurred, thus ensuring the integrity of the FIFO system. A FIFO overflow event occurs when more than 16 events are generated prior to an external processor reading a FIFO and clearing it. EVENT5[7:0] EVENT6[7:0] EVENT7[7:0] 7 6 5 4 3 2 1 If an overflow condition occurs, the overflow status bit is set. An interrupt is generated if overflow interrupt is enabled, signaling to the processor that more than 16 events have occurred. 0 EVENT9[7:0] EVENT10[7:0] EVENT11[7:0] EVENT8_IDENTIFIER[6:0] EVENT12[7:0] KEY SCAN CONTROL EVENT13[7:0] General EVENT8_STATE EVENT15[7:0] EVENT16[7:0] 09714-006 EVENT14[7:0] Figure 8. FIFO Operation Some of the onboard functions of ADP5589 can be programmed to generate events on the FIFO. A FIFO update control block manages updates to the FIFO. If an I2C transaction is accessing any of the FIFO address locations, updates are paused until the I2C transaction has completed. EVENT1[7:0] EVENT8[7:0] 09714-007 EC = 0 Figure 7. Breakdown of Eventx[7:0] Bits When events are available on the FIFO, the user should first read back the event count, EC[4:0], to determine how many events must be read back. Events can be read from the top of the FIFO only. When an event is read back, all remaining events in the FIFO are shifted up one location, and the EC[4:0] count is decremented. The 19 input/output pins can be configured to decode a keypad matrix up to a maximum size of 88 switches (11 × 8 matrix). Smaller matrices can also be configured, freeing up the unused row and column pins for other I/O functions. The R0 through R7 I/O pins comprise the rows of the keypad matrix. The C0 through C10 I/O pins comprise the columns of the keypad matrix. Pins used as rows are pulled up via the internal 300 kΩ (or 100 kΩ) resistors. Pins used as columns are driven low via the internal NMOS current sink. Rev. B | Page 9 of 52 ADP5589 Data Sheet scanned; therefore, if multiple keys are pressed, they are detected. VDD To prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth. KEY SCAN CONTROL R0 1 2 3 4 5 6 7 8 9 R1 R2 If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled up high. The key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. When the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode. 3 × 3 KEYPAD MATRIX Figure 9. Simplified Key Scan Block Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low. The key scanner operates by checking the row pins to see if they are low. If Switch 6 in the matrix is pressed, R1 connects to C2. The key scan circuit senses that one of the row pins is pulled low, and a key scan cycle begins. Key scanning involves driving all column pins high, then driving each column pin, one at a time, low and sensing whether a row pin is low or not. All row/column pairs are For the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. A logic high level represents the key status as pressed, and a logic low represents released. This eliminates the need to draw individual row/column signals when describing key events. KEY PRESSED KEY x KEY RELEASED KEY RELEASED 09714-009 C2 09714-008 C1 C0 Figure 10. Logic Low: Released; Logic High: Pressed Figure 11 shows a detailed representation of the key scan block and its associated control and status signals. When all row and column pins are used, a matrix of 88 unique keys can be scanned. Rev. B | Page 10 of 52 Data Sheet ADP5589 PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] PIN_CONFIG_C[2:0] RESET_TRIGGER_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] LOCK_EN EXT_LOCK_EVENT[7:0] UNLOCK1[7:0] UNLOCK2[7:0] UNLOCK_TIMER[2:0] INT_MASK_TIMER[4:0] RESET 1_INITIATE RESET 2_INITIATE LOCK_STAT LOCK_INT EVENT_INT KEY SCAN CONTROL OVRFLOW_INT I2C BUSY? KEY EVENT GPI EVENT EC[4:0] FIFO UPDATE LOGIC EVENT FIFO COLUMN SINK ON/OFF ROW SENSE I/O CONFIGURATION 89 1 2 3 4 5 6 7 8 9 10 11 90 12 13 14 15 16 17 18 19 20 21 22 91 23 24 25 26 27 28 29 30 31 32 33 92 34 35 36 37 38 39 40 41 42 43 44 93 45 46 47 48 49 50 51 52 53 54 55 94 56 57 58 59 60 61 62 63 64 65 66 95 67 68 69 70 71 72 73 74 75 76 77 96 78 79 80 81 82 83 84 85 86 87 88 09714-010 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 R0 R1 R2 R3 R4 R5 R6 R7 Figure 11. Detailed Key Scan Block KEY 32 KEY SCAN EVENT_INT EC[4:0] If a smaller 3 × 3 matrix is configured, for example, using the C5, C6, and C7 column pins and the R1, R2, and R3 row pins, only the nine event identifiers (17, 18, 19, 28, 29, 30, 39, 40, and 41) can possibly be observed on the FIFO, as shown in Figure 11. By default, the ADP5589 records key presses and releases on the FIFO. Figure 12 illustrates what happens when a single key is pressed and released. Initially, the key scanner is idle. When Key 32 is pressed, the scanner begins scanning through all configured row/column pairs. After the scan wait time, the scanner again scans through all configured row/column pairs and detects that Key 32 has remained pressed, which sets the EVENT_INT interrupt. The event counter, EC[4:0], is incremented to 1, EVENT1[7:0] of the FIFO is updated with its event identifier set to 32, and its Event1_State bit is set to 1, indicating a press. 1 FIFO KEY 32 PRESS 1 32 KEY 32 RELEASE 0 32 0 0 0 0 2 09714-011 Use Registers PIN_CONFIG_A[7:0] (0x49), PIN_CONFIG_B[7:0] (0x4A), and PIN_CONFIG_C[2:0] (0x4B) to configure I/Os for keypad decoding. The number label on each key switch represents the event identifier that is recorded if that switch is pressed. If all row/column pins are configured, it is possible to observe all 88 key identifiers on the FIFO. Figure 12. Press and Release Event The key scanner continues the scan/wait cycles while the key remains pressed. If the scanner detects that the key has been released for two consecutive scan cycles, the event counter EC[4:0] is incremented to 2, and EVENT2[7:0] of the FIFO is updated with its event identifier set to 32. Its Event2_State bit is set to 0, indicating a release. The key scanner goes back to idle mode because no other keys are pressed. The EVENT_INT interrupt can be triggered by both press and release key events. As shown in Figure 13, if Key 32 is pressed, EVENT_INT is asserted, EC[4:0] is updated, and the FIFO is updated. During the time that the key is still pressed, it is possible for the FIFO to be read, the event counter decremented to 0, and EVENT_INT cleared. When the key is finally released, EVENT_INT is asserted, the event counter incremented, and the FIFO updated with the release event information. Rev. B | Page 11 of 52 ADP5589 Data Sheet COL0 KEY 32 KEY SCAN COL1 COL2 PRESS PRESS GHOST PRESS ROW0 EVENT_INT CLEARED EVENT_INT FIFO 1 32 0 0 0 0 0 0 FIFO READ FIFO 0 0 0 0 0 0 0 0 ROW1 1 FIFO KEY 32 RELEASE 0 32 0 0 0 0 0 0 ROW2 Figure 13. Asserting the EVENT_INT Interrupt Figure 14. COL0-ROW3 is a Ghost Key Due to Short Between ROW0, COL0, COL2 and ROW3 During Key Press Key Pad Extension As shown in Figure 11, the keypad can be extended if each row is connected directly to ground by a switch. If the switch placed between R0 and ground is pressed, the whole row is grounded. When the key scanner completes scanning, it normally detects Key 1 to Key 11 as being pressed; however, this unique condition is decoded by the ADP5589, and Key Event 89 is assigned to it. Up to eight more key event assignments are possible, allowing the keypad size to extend up to 96. However, if one of the extended keys is pressed, none of the keys on that row is detectable. Activation of a ground key causes all other keys sharing that row to be undetectable. Ghosting Ghosting is an occurrence where, given certain key press combinations on a keypad matrix, a false positive reading of an additional key is detected. Ghosting is created when three or more keys are pressed simultaneously on multiple rows or columns (see Figure 14). Key combinations that form a right angle on the keypad matrix can cause ghosting. The solution to ghosting is to select a keypad matrix layout that takes into account three key combinations that are most likely to be pressed together. Multiple keys pressed across one row or across one column do not cause ghosting. Staggering keys so that they do not share a column also avoids ghosting. The most common practice is to place keys that are likely to be pressed together in the same row or column. Some examples of keys that are likely to be pressed together are as follows: ROW3 09714-013 KEY 32 PRESS 0 09714-012 1 EC[4:0] The navigation keys in combination with Select. The navigation keys in combination with the space bar. The reset combination keys, such as CTRL + ALT + DEL. FIFO Lock/Unlock The ADP5589 features a lock mode, whereby events are prevented from updating the FIFO or the event counter or from generating EVENT_INT interrupts until an unlock event is detected. The lock feature is enabled by setting the LOCK_EN (0x37[0]) bit or, alternatively, by a user programmable key or GPI event (set via EXT_LOCK_EVENT[7:0], Address 0x35). If the lock feature is enabled by the LOCK_EN bit, the LOCK_STAT (0x02[5]) bit is set. If the lock feature is enabled by an external event, then the LOCK_STAT bit is set, and a LOCK_INT interrupt is generated. Unlock events are programmed via the UNLOCK1[7:0] (0x33) and UNLOCK2[7:0] (0x34) registers. Bits[6:0] comprise the even number. Bit 7 determines the active/inactive event (see the UNLOCK1 Register 0x33 (Table 59) and the UNLOCK2 Register 0x34 (Table 60). If the user chooses to use only one unlock event, only the UNLOCK1[7:0] register should be programmed. Unlock events can be key press events (Event 1 to Event 88). Key release events are ignored when the keypad is locked and should not be used as unlock events. GPIs configured to generate FIFO updates can also be used as unlock events (Event 97 to Event 115, either active or inactive). If either UNLOCKx register is programmed with Value 127 (Event 127), this means that any allowable event (key or GPI) is the unlock event. For example, if UNLOCK1[6:0] is programmed with 17, and UNLOCK2[6:0] is programmed with 127, the unlock sequence is Key 17 press followed by any other allowable event. If the first unlock event is detected, partial unlock has occurred. If the next event after the first unlock event is not the second unlock event, then a full lock state is entered again. If the next event after the first unlock event is the second unlock event, then LOCK_STAT is cleared, and a LOCK_INT interrupt is generated. The user can at any stage clear LOCK_EN. This clears the LOCK_STAT bit but does not cause a LOCK_INT interrupt to be generated. Rev. B | Page 12 of 52 Data Sheet ADP5589 When full unlock is achieved, FIFO and event count updates resume. Note that if a key press is used as the second unlock event, the release of that key is captured on the FIFO after unlocking is completed. The ADP5589 features an unlock timer, UNLOCK_TIMER[2:0] (0x36[2:0]). When enabled, after the first unlock event occurs, the unlock timer begins counting, and the second unlock event must occur before the unlock timer expires. If the unlock timer expires, the first unlock event must occur again to restart the unlock process. Figure 15 shows a simple state diagram of the unlocking process. NO YES FIRST UNLOCK EVENT? The ADP5589 features an interrupt mask timer, INT_MASK_ TIMER[4:0] (0x36[7:3]). When this timer and lock mode are enabled, a single EVENT_INT is generated if any key is pressed or any GPI (programmed to update the FIFO) is active. When the EVENT_INT is generated, the mask timer begins counting. No additional EVENT_INT interrupts are generated until the mask timer expires and a new key is pressed or any GPI (programmed to update the FIFO) is active, unless the unlock events occur, in which case, normal operation is resumed. Allowing a single EVENT_INT interrupt is useful to alert the processor to turn on its screen and display an unlock message to the user. Blanking out additional key presses ensures that the processor is not unnecessarily interrupted until the unlock events occur. Figure 16 shows the unlock sequence when the interrupt mask timer is enabled. LOCKED LOCK_STAT = 1 EVENT DETECTED? When lock mode is enabled, no EVENT_INT interrupts can be generated until the unlock events occur. NO YES LOCK_STAT = 1 NO SECOND UNLOCK EVENT REQUIRED? YES NO UNLOCK TIMER ENABLED? YES EVENT DETECTED? NO START UNLOCK TIMER YES EVENT DETECTED? NO YES UNLOCK TIMER EXPIRED? YES NO SECOND UNLOCK EVENT? NO UNLOCK LOCK_STAT = 0 09714-014 YES Figure 15. State Diagram of Unlocking Process Rev. B | Page 13 of 52 ADP5589 Data Sheet LOCKED LOCK_STAT = 1 EVENT DETECTED? NO YES MASK TIMER ENABLED? YES YES SET EVENT_INT = 1 MASK TIMER EXPIRED? NO NO START MASK TIMER FIRST UNLOCK EVENT? NO YES LOCK_STAT = 1 NO SECOND UNLOCK EVENT REQUIRED? YES NO UNLOCK TIMER ENABLED? YES EVENT DETECTED? NO START UNLOCK TIMER YES YES SET EVENT_INT = 1 YES EVENT DETECTED? MASK TIMER ENABLED? MASK TIMER EXPIRED? NO NO YES NO YES MASK TIMER ENABLED? START MASK TIMER SET EVENT_INT = 1 YES MASK NO TIMER EXPIRED? NO START MASK TIMER UNLOCK TIMER EXPIRED? YES NO SECOND UNLOCK EVENT? NO UNLOCK LOCK_STAT = 0 Figure 16. Unlock Sequence Rev. B | Page 14 of 52 09714-015 YES Data Sheet ADP5589 GPI 6 GPI Input GPI_INT_LEVEL_A[5] GPI_INTERRUPT_EN_A[5] GPI_STATUS_A[5] CLEARED BY READ GPI_INT_STAT_A[5] PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] CLEARED BY WRITE ‘1’ GPI_INT PIN_CONFIG_C[2:0] Figure 18. Single GPI Example LOCK_EN EXT_LOCK_EVENT[7:0] LOCK_STAT GPIs can be programmed to generate FIFO events via the GPI_EVENT_EN_x registers. GPIs in this mode do not generate GPI_INT interrupts and instead generate EVENT_INT interrupts. Figure 19 shows several GPI lines and their effects on the FIFO and event count, EC[4:0]. LOCK_INT GPI 6 UNLOCK1[7:0] UNLOCK2[7:0] UNLOCK_TIMER[2:0] INT_MASK_TIMER[4:0] GPIO_DIRECTION_A[7:0] GPIO_DIRECTION_B[7:0] GPIO_DIRECTION_C[2:0] GPI_INT_LEVEL_A[7:0] GPI_INT_LEVEL_B[7:0] EVENT_INT GPI_INT_LEVEL_C[2:0] GPI 14 GPI_INTERRUPT_EN_A[7:0] GPI_INT GPI_INTERRUPT_EN_B[7:0] GPI_INT_STAT_A[7:0] GPI_INTERRUPT_EN_C[2:0] GPI_INT_STAT_B[7:0] GPI_EVENT_EN_A[7:0] GPI_INT_STAT_C[2:0] LCK_TRK_GPI GPI 2 GPI_STATUS_A[7:0] GPI_EVENT_EN_B[7:0] GPI_EVENT_EN_C[2:0] 09714-017 Each of the 19 I/O lines can be configured as a general-purpose logic input line. Figure 17 shows a detailed representation of the GPI scan and detect block and all its associated control and status signals. GPI SCAN CONTROL GPI SCAN GPI_STATUS_B[7:0] GPI_STATUS_C[2:0] RESET_TRIGGER_TIME[2:0] EVENT_INT RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] EC[4:0] RESET1_EVENT_C[7:0] 1 RESET2_EVENT_A[7:0] 2 3 4 5 6 (R0) GPIO 1 (R1) GPIO 2 (R2) GPIO 3 (R3) GPIO 4 (R4) (R5) GPIO 5 GPIO 6 (R6) GPIO 7 (R7) GPIO 8 (C0) GPIO 9 OVRFLOW_INT I2C BUSY? KEY EVENT GPI EVENT FIFO UPDATE GPI 2 ACTIVE GPI 6 ACTIVE GPI 14 ACTIVE GPI 14 INACTIVE GPI 6 ACTIVE GPI 2 ACTIVE EC[4:0] LOGIC EVENT FIFO Figure 19. Multiple GPI Lines Example (C1) GPIO 10 (C2) GPIO 11 (C3) GPIO 12 (C4) GPIO 13 (C5) GPIO 14 (C6) GPIO 15 (C10) GPIO 19 09714-016 (C7) GPIO 16 (C8) GPIO 17 (C9) GPIO 18 Figure 17. GPI Scan and Detect Block The current input state of each GPI can be read back using the GPI_STATUS_x registers. Each GPI can be programmed to generate an interrupt via the GPI_INTERRUPT_EN_x registers. The interrupt status is stored in the GPI_INT_STAT_x registers. GPI interrupts can be programmed to trigger on inputs being high or on inputs being low via the GPI_INT_LEVEL_x registers. If any of the GPI interrupts is triggered, the master GPI_INT interrupt is also triggered. Figure 18 demonstrates a single GPI and how it affects its corresponding status and interrupt status bits. FIFO 1 101 1 105 1 113 0 113 0 105 0 101 09714-018 RESET2_EVENT_B[7:0] The GPI scanner is idle until it detects a level transition. It scans the GPI inputs and updates accordingly. It then returns to idle immediately; it does not scan/wait, like the key scanner. As such, the GPI scanner can detect narrow pulses once they get past the 50 μs input debounce filter. GPIs (programmed for FIFO updating) can be used as keypad unlock events via the UNLOCKx registers (see the FIFO Lock/Unlock section). The LCK_TRK_GPI bit can be used to allow GPIs (programmed for FIFO updating) to be tracked when the keypad is locked. GPO OUTPUT Each of the 19 I/O lines can be configured as a general-purpose output (GPO) line. Figure 6 shows a detailed diagram of the I/O structure. See the Detailed Register Descriptions section for GPO configuration and usage. Rev. B | Page 15 of 52 ADP5589 Data Sheet LOGIC BLOCKS The outputs from the logic blocks can be configured to generate interrupts. They can also be configured to generate events on the FIFO. The LCK_TRK_LOGIC (0x4D[4]) bit can be used to allow logic events (programmed for FIFO updating) to be tracked when the keypad is locked. Several of the ADP5589 I/O lines can be used as inputs and outputs for implementing some common logic functions. The R1, R2, and R3 I/O pins can be used as inputs, and the R0 I/O pin can be used as an output for Logic Block 1. Figure 21 and Figure 22 show detailed diagrams of the internal make-up of each logic block, illustrating the possible logic functions that can be implemented. The C8, C7, and C6 I/O pins can be used as inputs, and the C9 I/O pin can be used as an output, for Logic Block 2. It is also possible to cascade the output of Logic Block 1 as an alternate input for Logic Block 2 (LY1 is used instead of LA2). LOGIC BLOCK1 LOGIC BLOCK2 (R1) LA1 (C8) LA2 (R2) LB1 (R3) LC1 (C7) LB2 (C6) LC2 LA1_INV LA2_INV LB1_INV LB2_INV LC1_INV LY1 (R0) LC2_INV LY2_INV LY1_INV FF1_SET FF2_SET SET D FF1_CLR LOGIC1_SEL[2:0] LY2 (C9) Q SET D FF2_CLR LOGIC2_SEL[2:0] CLR R3_EXTEND_CFG[1:0] Q CLR C6_EXTEND_CFG OVRFLOW_INT LCK_TRK_LOGIC I2C BUSY? LOGIC1_INT_LEVEL EC[4:0] KEY EVENT LOGIC2_INT_LEVEL FIFO UPDATE GPI EVENT LOGIC1_EVENT_EN LOGIC EVENT LOGIC EVENT/INT GENERATOR LOGIC2_EVENT_EN RESET_TRIGGER_TIME[2:0] FIFO RESET1_EVENT_A[7:0] EVENT_INT LOGIC1_INT LOGIC2_INT RESET1_EVENT_B[7:0] 09714-019 RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] Figure 20. Logic Blocks Overview LA1 LA1 0 LA1 1 IN_LA1 OUT SEL IN_LA1 LA1_INV AND 0 IN_LB1 AND IN_LC1 LB1 LB1 0 LB1 1 OUT LC1 0 LC1 1 AND1 SEL MUX GND IN_LA1 SEL OUT OUT IN_LB1 OR 0 IN_LB1 LB1_INV LC1 1 OR IN_LC1 IN_LC1 1 OUT AND1 OR1 001 OR1 SEL XOR1 FF1 IN_LA1 XOR 0 IN_LB1 SEL XOR IN_LC1 1 OUT XOR1 IN_LA1 IN_LB1 SEL LC1_INV IN_LC1 FF1_SET 000 010 LY1 011 OUT 100 LY1 0 1 OUT LY1 SEL 101 110 LY1_INV 111 SEL[2:0] SET IN_LA1 D Q FF1 LOGIC1_SEL[2:0] IN_LB1 CLR FF1_CLR 0 IN_LC1 1 SEL R3_EXTEND_CFG[1:0] = 01 Figure 21. Logic Block 1 Rev. B | Page 16 of 52 09714-020 OUT Data Sheet ADP5589 LA2 (LY1) LA2 0 OUT LY1 1 LA2 SEL OUT 1 SEL (IN_LY1) IN_LA2 LA2_INV IN_LB2 (LY1) LY1_CASCADE (IN_LY1) IN_LA2 0 AND 0 AND IN_LC2 LB2 LB2 LB2 0 1 OUT IN_LB2 SEL LC2 LC2 0 1 OUT OR 0 OR IN_LC2 IN_LC2 SEL LC2_INV (IN_LY1) IN_LA2 OUT AND2 SEL MUX GND IN_LB2 LB2_INV LC2 (IN_LY1) IN_LA2 1 1 OUT AND2 OR2 OR2 SEL XOR2 FF2 XOR 0 IN_LB2 XOR IN_LC2 1 OUT XOR2 IN_LA2 IN_LB2 SEL IN_LC2 000 001 010 LY2 011 OUT 100 0 LY2 1 OUT LY2 SEL 101 LY2_INV 110 111 FF2_SET SEL[2:0] SET IN_LA2 D LOGIC2_SEL Q FF2 IN_LB2 CLR FF2_CLR 0 OUT SEL 09714-021 1 IN_LC2 C6_EXTEND_CFG = 1 Figure 22. Logic Block 2 PWM_EN PWM_MODE PWM_OFFT_LOW_BYTE[7:0] OFF TIME[15:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] ON TIME[15:0] 0 OUT 1 SEL PWM GENERATOR (C6) PWM_IN (R3) PWM_OUT AND 09714-022 PWM_OFFT_HIGH_BYTE[7:0] PWM_IN_AND Figure 23. PWM Block Diagram PWM BLOCK CLOCK DIVIDER BLOCK The ADP5589 features a PWM generator whose output can be configured to drive out on I/O Pin R3. PWM on/off times are programmed via four 8-bit registers. The ADP5589 features a clock divider block that divides down the frequency of an externally supplied source via I/O Pin C6. The output of the divider is driven out on I/O Pin R3. The highest frequency obtainable from the PWM is performed by setting the least significant bit (LSB) of both the on and off bit patterns, resulting in a 500 kHz signal with a 50% duty cycle. Each LSB respresents 1 µs of on or off time. The PWM block provides support for continuous PWM mode as well as a one-shot mode (see Table 74). Additionally, an external signal can be AND’ed with the internal PWM signal. This option can be selected by writing a 1 to PWM_IN_AND, PWM_CFG[2]. The input to the external AND is the C6 I/O pin. C6 should be set to GPI (GPIO15). Note that the debounce for C6 will result in a delay of the AND’ing, and can be controlled using register GPI_15_DEB_DIS (Address 0x28, Bit[6]). CLK_DIV_EN CLK_DIV[4:0] (C6) CLK_IN CLK DIVIDER 0 1 CLK_OUT (R3) OUT SEL CLK_INV 09714-023 Newly programmed values are not latched until the final byte, PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written to (see Figure 23). Figure 24. Clock Divider Block RESET BLOCKS The ADP5589 features two reset blocks that can generate reset conditions if certain events are detected at the same time. Up to three reset trigger events can be programmed for RESET1. Up to two reset trigger events can be programmed for RESET2. The event scan control blocks monitor whether these events are present for the duration of RESET_TRIGGER_TIME[2:0] (0x3D[4:2]). If they are, reset-initiate signals are sent to the reset generator blocks. The generated reset signal pulse width is programmable. Newly programmed values are not latched until the final byte, PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written. Rev. B | Page 17 of 52 ADP5589 Data Sheet INTERRUPTS RST RST_PASSTHRU_EN KEY SCAN CONTROL GPI SCAN CONTROL The INT pin can be asserted low if any of the internal interrupt sources is active. The user can select which internal interrupts interact with the external interrupt pin in register INT_EN (Address 0x4E, Bits[7:0]) (refer to Table 86). allows the user to choose whether the external interrupt pin remains asserted, or deasserts for 50 µs, then reasserts, in the case that there are multiple internal interrupts asserted, and one is cleared (refer to Table 85). RESET1_ (R4) INITIATE RESET RESET1 GEN 1 RESET_PULSE_WIDTH[1:0] RESET GEN 2 LOGIC BLOCK CONTROL (C4) RESET2 EVENT_INT EVENT_IEN GPI_INT 09714-024 RESET_TRIGGER_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] RESET2_ INITIATE GPI_IEN LOGIC1_INT Figure 25. Reset Blocks LOGIC1_IEN INT DRIVE The RESET1 signal uses I/O Pin R4 as its output. A passthrough mode allows the main RST pin to be output on the R4 pin also. INT LOGIC2_INT LOGIC2_IEN OVRFLOW_INT The RESET2 signal uses I/O Pin C4 as its output. OVRFLOW_IEN It is not recommended to use the immediate trigger time (see the details of the RESET_CFG Register, 0x3D, in Table 69) because this setting may cause false triggering. Rev. B | Page 18 of 52 LOCK_INT LOCK_IEN INT_CFG Figure 26. Asserting INT Low 09714-025 The reset generation signals are useful in situations where the system processor has locked up and the system is unresponsive to input events. The user can press one of the reset event combinations and initiate a system-wide reset. This alleviates the need for removing the battery from the system and performing a hard reset. Data Sheet ADP5589 REGISTER INTERFACE Register access of the ADP5589 is acquired via its I2C-compatible serial interface. The interface can support clock frequencies of up to 1 MHz. If the user is accessing the FIFO or key event counter (KEC), FIFO/KEC updates are paused. If the clock frequency is very low, events may not be recorded in a timely manner. FIFO or KEC updates can happen up to 23 μs after an interrupt is asserted because of the number of I2C cycles required to perform an I2C read or write. This delay should not present an issue to the user. R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5589 acknowledges the data byte by pulling the data line low. The pointer address is then incremented to write the next data byte, until it finishes writing the n data byte. The ADP5589 pulls the data line low after every byte, and a stop condition completes the sequence. Figure 27 shows a typical write sequence for programming an internal register. The cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the ADP5589 is 0x34, followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5589 acknowledges the data byte by pulling the data line low. A stop condition completes the sequence. Figure 29 shows a typical byte read sequence for reading internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. A start condition is repeated, followed by the 7-bit device address (0x34), followed by the R/W bit set to 1 for a read cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The host pulls the data line high (no acknowledge), and a stop condition completes the sequence. Figure 28 shows a typical multibyte write sequence for programming internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 STOP 8-BIT REGISTER POINTER 0 8-BIT WRITE DATA ADP5589 ACK ADP5589 ACK ADP5589 ACK 0 09714-026 START Figure 27. I2C Single-Byte Write Sequence 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 STOP 8-BIT REGISTER POINTER ADP5589 ACK 0 WRITE BYTE 1 ADP5589 ACK 0 WRITE BYTE 2 ADP5589 ACK 0 ADP5589 ACK 0 WRITE BYTE n ADP5589 ACK 0 ADP5589 ACK Figure 28. I2C Multibyte Write Sequence REPEAT START 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 8-BIT REGISTER POINTER ADP5589 ACK 0 1 = READ 7-BIT DEVICE ADDRESS ADP5589 ACK Figure 29. I2C Single-Byte Read Sequence Rev. B | Page 19 of 52 1 0 ADP5589 ACK STOP 8-BIT READ DATA 1 NO ACK 09714-027 START 09714-028 START ADP5589 Data Sheet followed by the R/W bit set to 1 for a read cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read. The host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence. START 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 REPEAT START 8-BIT REGISTER POINTER ADP5589 ACK 0 1 = READ 7-BIT DEVICE ADDRESS ADP5589 ACK 1 0 STOP READ BYTE 1 ADP5589 ACK Figure 30. I2C Multibyte Read Sequence Rev. B | Page 20 of 52 0 READ BYTE 2 MASTER ACK 0 MASTER ACK 0 READ BYTE n MASTER ACK 1 NO ACK 09714-029 Figure 30 shows a typical multibyte read sequence for reading internal registers. The cycle begins with a start condition, followed by the 7-bit device address (0x34), followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. A start condition is repeated, followed by the 7-bit device address (0x34), Data Sheet ADP5589 REGISTER MAP Table 6. Addr. 0x00 0x01 R/W R R/W Bit 7 Bit 6 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 R R R R R R R R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LOGIC2_STAT Event1_State Event2_State Event3_State Event4_State Event5_State Event6_State Event7_State Event8_State Event9_State Event10_State Event11_State Event12_State Event13_State Event14_State Event15_State Event16_State Reserved Bit 5 MAN_ID LOGIC2_INT LOGIC1_STAT LOCK_STAT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 4 Bit 1 Bit 0 REV_ID LOGIC1_ LOCK_INT OVRFLOW_ GPI_INT EVENT_INT INT INT EC[4:0] EVENT1_IDENTIFIER[6:0] EVENT2_IDENTIFIER[6:0] EVENT3_IDENTIFIER[6:0] EVENT4_IDENTIFIER[6:0] EVENT5_IDENTIFIER[6:0] EVENT6_IDENTIFIER[6:0] EVENT7_IDENTIFIER[6:0] EVENT8_IDENTIFIER[6:0] EVENT9_IDENTIFIER[6:0] EVENT10_IDENTIFIER[6:0] EVENT11_IDENTIFIER[6:0] EVENT12_IDENTIFIER[6:0] EVENT13_IDENTIFIER[6:0] EVENT14_IDENTIFIER[6:0] EVENT15_IDENTIFIER[6:0] EVENT16_IDENTIFIER[6:0] GPI_INT_STAT_A[7:0] GPI_INT_STAT_B[7:0] GPI_INT_STAT_C[2:0] GPI_STATUS_A[7:0] GPI_STATUS_B[7:0] GPI_STATUS_C[2:0] RPULL_CONFIG_A[7:0] RPULL_CONFIG_B[7:0] RPULL_CONFIG_C[7:0] RPULL_CONFIG_D[7:0] RPULL_CONFIG_E[5:0] GPI_INT_LEVEL_A[7:0] GPI_INT_LEVEL_B[7:0] GPI_INT_LEVEL_C[2:0] GPI_EVENT_EN_A[7:0] GPI_EVENT_EN_B[7:0] GPI_EVENT_EN_C[2:0] GPI_INTERRUPT_EN_A[7:0] GPI_INTERRUPT_EN_B[7:0] GPI_INTERRUPT_EN_C[2:0] DEBOUNCE_DIS_A[7:0] DEBOUNCE_DIS_B[7:0] DEBOUNCE_DIS_C[2:0] GPO_DATA_OUT_A[7:0] GPO_DATA_OUT_B[7:0] GPO_DATA_OUT_C[2:0] GPO_OUT_MODE_A[7:0] GPO_OUT_MODE_B[7:0] GPO_OUT_MODE_C[2:0] GPIO_DIRECTION_A[7:0] GPIO_DIRECTION_B[7:0] GPIO_DIRECTION_C[2:0] Rev. B | Page 21 of 52 Bit 3 Bit 2 ADP5589 Data Sheet Addr. 0x33 R/W R/W Bit 7 UNLOCK1_ STATE UNLOCK2_ STATE EXT_LOCK_ STATE Bit 6 0x34 R/W 0x35 R/W 0x36 0x37 0x38 R/W R/W R/W 0x39 R/W 0x3A R/W 0x3B R/W 0x3C R/W 0x3D R/W 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x48 0x49 0x4A 0x4B 0x4C R/W R/W R/W R/W R/W PULL_SELECT 0x4D R/W OSC_EN 0x4E R/W Bit 5 Bit 4 Bit 3 UNLOCK1[6:0] Bit 2 Bit 1 Bit 0 UNLOCK2[6:0] EXT_LOCK_EVENT[6:0] INT_MASK_TIMER[4:0] UNLOCK_TIMER[2:0] Reserved RESET1_ EVENT_A Level RESET2_ EVENT_B Level RESET1_ EVENT_B Level RESET1_ EVENT_B Level RESET1_ EVENT_B Level RESET2_POL LOCK_EN RESET1_EVENT_A[6:0] RESET1_EVENT_B[6:0] RESET1_EVENT_C[6:0] RESET2_EVENT_A[6:0] RESET2_EVENT_B[6:0] RESET1_POL RST_ PASSTHRU_EN RESET_TRIGGER_TIME[2:0] RESET_PULSE_WIDTH[1:0] PWM_OFFT_LOW_BYTE[7:0] PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] Reserved Reserved Reserved LY1_CASCADE CLK_INV LY1_INV LY2_INV Reserved PWM_IN_AND LC1_INV LC2_INV Reserved LY2_DBNC_DIS LB1_INV LB2_INV LOGIC2_ EVENT_EN CLK_DIV[4:0] LA1_INV LA2_INV FF2_SET LOGIC2_INT_ LEVEL FF2_CLR LY1_DBNC_ DIS Reserved PWM_MODE PWM_EN CLK_DIV_EN LOGIC1_SEL[2:0] LOGIC2_SEL[2:0] FF1_SET FF1_CLR LOGIC1_ LOGIC1_INT_ EVENT_EN LEVEL KEY_POLL_TIME[1:0] PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] Reserved C4_EXTEND_ R4_EXTEND_ CFG CFG CORE_FREQ[1:0] Reserved LOGIC2_IEN C6_ EXTEND_CFG LCK_TRK_ LOGIC LOGIC1_ IEN Rev. B | Page 22 of 52 R3_EXTEND_CFG[1:0] LCK_TRK_GPI LOCK_IEN OVRFLOW_ IEN PIN_CONFIG_C[2:0] C9_EXTEND_ R0_EXTEND_ CFG CFG INT_CFG RST_CFG GPI_IEN EVENT_IEN Data Sheet ADP5589 DETAILED REGISTER DESCRIPTIONS Note: N/A throughout this section means not applicable. Note: All registers default to 0000 0000 unless otherwise specified. ID Register 0x00 Table 7. ID Bit Descriptions Bits Name [7: 4] MAN_ID [3:0] REV_ID Default = 0001 XXXX R/W R R Description Manufacturer ID, default = 0001. Rev ID. INT_STATUS Register 0x01 Table 8. INT_STATUS Bit Descriptions Bits [7: 6] 5 Name N/A LOGIC2_INT R/W R/W 4 LOGIC1_INT R/W 3 LOCK_INT R/W 2 OVRFLOW_INT R/W 1 GPI_INT R/W 0 EVENT_INT R/W Description Reserved. 0 = no interrupt. 1 = interrupt due to a general Logic 2 condition. Write a 1 to this bit to clear it. 0 = no interrupt. 1 = interrupt due to a general Logic 1 condition. Write a 1 to this bit to clear it. 0 = no interrupt. 1 = interrupt due to a lock/unlock condition. The user can read LOCK_STAT (0x02[5]) to determine if LOCK_INT is due to a lock or unlock event. If LOCK_STAT = 1, LOCK_INT is due to a lock event. If LOCK_STAT = 0, LOCK_INT is due to an unlock event. Write a 1 to this bit to clear it. If lock mode is enabled via the software bit LOCK_EN (0x37[0]), a LOCK_INT is not generated because the processor knows it just enabled lock mode. If lock mode is disabled (while locked) via the software bit LOCK_EN, a LOCK_INT is not generated because the processor knows it just disabled lock mode. 0 = no interrupt. 1 = interrupt due to an overflow condition. Write a 1 to this bit to clear it. 0 = no interrupt. 1 = interrupt due to a general GPI condition. This bit is not set by a GPI that has been configured to update the FIFO and event count. Write a 1 to this bit to clear it. This bit cannot be cleared until all GPI_x_INT bits are cleared. 0 = no interrupt. 1 = interrupt due to key event (press/release), GPI event (GPI programmed for FIFO updates), or Logic 1/Logic 2 event (programmed for FIFO updates).Write a 1 to this bit to clear it. Status Register 0x02 Table 9. Status Bit Descriptions Bits 7 Name LOGIC2_STAT R/W R 6 LOGIC1_STAT R 5 LOCK_STAT R [4:0] EC[4:0] R Description 0 = output from Logic Block 2. (LY2) is low. 1 = output from Logic Block 2. (LY2) is high. 0 = output from Logic Block 1 (LY1) is low. 1 = output from Logic Block 1 (LY1) is high. 0 = unlocked. 1 = locked. Event count value. Indicates how many events are currently stored on the FIFO. Rev. B | Page 23 of 52 ADP5589 Data Sheet FIFO_1 Register 0x03 Table 10. FIFO_1 Bit Descriptions Bits 7 Name Event1_State R/W R [6:0] EVENT1_IDENTIFIER[6:0] Description The seven lower bits of each FIFO location contain the event identifier, which can be decoded to reveal the event recorded. Table 11 outlines each event number, what it represents, and the I/O pins associated with it. Bit 7 is the Event 1 state. This bit represents the state of the event that is recorded in EVENT1_IDENTIFIER[6:0]. For key events (Event 1 to Event 96). 1 = key is pressed. 0 = key is released. For GPI and logic events (Event 97 to Event 117). 1 = GPI/logic is active. 0 = GPI/logic is inactive. Active and inactive states are programmable. Table 11. Event Decoding Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Meaning No event Key 1 (R0, C0) Key 2 (R0, C1) Key 3 (R0, C2) Key 4 (R0, C3) Key 5 (R0, C4) Key 6 (R0, C5) Key 7 (R0, C6) Key 8 (R0, C7) Key 9 (R0, C8) Key 10 (R0, C9) Key 11 (R0, C10) Key 12 (R1, C0) Key 13 (R1, C1) Key 14 (R1, C2) Key 15 (R1, C3) Key 16 (R1, C4) Key 17 (R1, C5) Key 18 (R1, C6) Key 19 (R1, C7) Key 20 (R1, C8) Key 21 (R1, C9) Key 22 (R1, C10) Key 23 (R2, C0) Key 24 (R2, C1) Key 25 (R2, C2) Key 26 (R2, C3) Key 27 (R2, C4) Key 28 (R2, C5) Key 29 (R2, C6) Key 30 (R2, C7) Key 31 (R2, C8) Event No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Meaning Key 32 (R2, C9) Key 33 (R2, C10) Key 34 (R3, C0) Key 35 (R3, C1) Key 36 (R3, C2) Key 37 (R3, C3) Key 38 (R3, C4) Key 39 (R3, C5) Key 40 (R3, C6) Key 41 (R3, C7) Key 42 (R3, C8) Key 43 (R3, C9) Key 44 (R3, C10) Key 45 (R4, C0) Key 46 (R4, C1) Key 47 (R4, C2) Key 48 (R4, C3) Key 49 (R4, C4) Key 50 (R4, C5) Key 51 (R4, C6) Key 52 (R4, C7) Key 53 (R4, C8) Key 54 (R4, C9) Key 55 (R4, C10) Key 56 (R5, C0) Key 57 (R5, C1) Key 58 (R5, C2) Key 59 (R5, C3) Key 60 (R5, C4) Key 61 (R5, C5) Key 62 (R5, C6) Key 63 (R5, C7) Event No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Rev. B | Page 24 of 52 Meaning Key 64 (R5, C8) Key 65 (R5, C9) Key 66 (R5, C10) Key 67 (R6, C0) Key 68 (R6, C1) Key 69 (R6, C2) Key 70 (R6, C3) Key 71 (R6, C4) Key 72 (R6, C5) Key 73 (R6, C6) Key 74 (R6, C7) Key 75 (R6, C8) Key 76 (R6, C9) Key 77 (R6, C10) Key 78 (R7, C0) Key 79 (R7, C1) Key 80 (R7, C2) Key 81 (R7, C3) Key 82 (R7, C4) Key 83 (R7, C5) Key 84 (R7, C6) Key 85 (R7, C7) Key 86 (R7, C8) Key 87 (R7, C9) Key 88 (R7, C10) Key 89 (R0, GND) Key 90 (R1, GND) Key 91 (R2, GND) Key 92 (R3, GND) Key 93 (R4, GND) Key 94 (R5, GND) Key 95 (R6, GND) Event No. 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Meaning Key 96 (R7, GND) GPI 1 (R0) GPI 2 (R1) GPI 3 (R2) GPI 4 (R3) GPI 5 (R4) GPI 6 (R5) GPI 7 (R6) GPI 8 (R7) GPI 9 (C0) GPI 10 (C1) GPI 11 (C2) GPI 12 (C3) GPI 13 (C4) GPI 14 (C5) GPI 15 (C6) GPI 16 (C7) GPI 17 (C8) GPI 18 (C9) GPI 19 (C10) Logic 1 Logic 2 Unused Unused Unused Unused Unused Unused Unused Unused Unused Wildcard for unlock Data Sheet ADP5589 FIFO_2 Register 0x04 Table 12. FIFO_2 Bit Descriptions Bits 7 [6:0] Name Event2_State EVENT2_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. FIFO_3 Register 0x05 Table 13. FIFO_3 Bit Descriptions Bits 7 [6: 0] Name Event3_State EVENT3_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. FIFO_4 Register 0x06 Table 14. FIFO_4 Bit Descriptions Bits 7 [6:0] Name Event4_State EVENT4_IDENTIFIER[6:0] FIFO_5 Register 0x07 Table 15. FIFO_5 Bit Descriptions Bits 7 [6:0] Name Event5_State EVENT5_IDENTIFIER[6:0] FIFO_6 Register 0x08 Table 16. FIFO_6 Bit Descriptions Bits 7 [6:0] Name Event6_State EVENT6_IDENTIFIER[6:0] FIFO_7 Register 0x09 Table 17. FIFO_7 Bit Descriptions Bits 7 [6:0] Name Event7_State EVENT7_IDENTIFIER[6:0] FIFO_8 Register 0x0A Table 18. FIFO_8 Bit Descriptions Bits 7 [6:0] Name Event8_State EVENT8_IDENTIFIER[6:0] FIFO_9 Register 0x0B Table 19. FIFO_9 Bit Descriptions Bits 7 [6:0] Name Event9_State EVENT9_IDENTIFIER[6:0] Rev. B | Page 25 of 52 ADP5589 Data Sheet FIFO_10 Register 0x0C Table 20. FIFO_10 Bit Descriptions Bits 7 [6:0] Name Event10_State EVENT10_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. FIFO_11 Register 0x0D Table 21. FIFO_11 Bit Descriptions Bits 7 [6:0] Name Event11_State EVENT11_IDENTIFIER[6:0] FIFO_12 Register 0x0E Table 22. FIFO_12 Bit Descriptions Bits 7 [6:0] Name Event12_State EVENT12_IDENTIFIER[6:0] FIFO_13 Register 0x0F Table 23. FIFO_13 Bit Descriptions Bits 7 [6:0] Name Event13_State EVENT13_IDENTIFIER[6:0] FIFO_14 Register 0x10 Table 24. FIFO_14 Bit Descriptions Bits 7 [6: 0] Name Event14_State EVENT14_IDENTIFIER[6:0] FIFO_15 Register 0x11 Table 25. FIFO_15 Bit Descriptions Bits 7 [6: 0] Name Event15_State EVENT15_IDENTIFIER[6:0] FIFO_16 Register 0x12 Table 26. FIFO_16 Bit Descriptions Bits 7 [6: 0] Name Event16_State EVENT16_IDENTIFIER[6:0] Rev. B | Page 26 of 52 Data Sheet ADP5589 GPI_INT_STAT_A Register 0x13 Table 27. GPI_INT_STAT_A Bit Descriptions Bits 7 Name GPI_8_INT R/W R 6 GPI_7_INT R 5 GPI_6_INT R 4 GPI_5_INT R 3 GPI_4_INT R 2 GPI_3_INT R 1 GPI_2_INT R 0 GPI_1_INT R Description 0 = no interrupt. 1 = interrupt due to GPI_8 (R7 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_7 (R6 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_6 (R5 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_5 (R4 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_4 (R3 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_3 (R2 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_2 (R1 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_1 (R0 pin). Cleared on read. GPI_INT_STAT_B Register 0x14 Table 28. GPI_INT_STAT_B Bit Descriptions Bits 7 Name GPI_16_INT R/W R 6 GPI_15_INT R 5 GPI_14_INT R 4 GPI_13_INT R 3 GPI_12_INT R 2 GPI_11_INT R 1 GPI_10_INT R 0 GPI_9_INT R Description 0 = no interrupt. 1 = interrupt due to GPI_16 (C7 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_15 (C6 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_14 (C5 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_13 (C4 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_12 (C3 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_11 (C2 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_10 (C1 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_9 (C0 pin). Cleared on read. GPI_INT_STAT_C Register 0x15 Table 29. GPI_INT_STAT_C Bit Descriptions Bits [7: 3] 2 Name R/W GPI_19_INT R 1 GPI_18_INT R 0 GPI_17_INT R Description Reserved. 0 = no interrupt. 1 = interrupt due to GPI_19 (C10 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_18 (C9 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_17 (C8 pin). Cleared on read. Rev. B | Page 27 of 52 ADP5589 Data Sheet GPI_STATUS_A Register 0x16 Table 30. GPI_STATUS_A Bit Descriptions Bits 7 Name GPI_8_STAT R/W R 6 GPI_7_STAT R 5 GPI_6_STAT R 4 GPI_5_STAT R 3 GPI_4_STAT R 2 GPI_3_STAT R 1 GPI_2_STAT R 0 GPI_1_STAT R Description 0 = GPI_8 (R7 pin) is low. 1 = GPI_8 (R7 pin) is high. 0 = GPI_7 (R6 pin) is low. 1 = GPI_7 (R6 pin) is high. 0 = GPI_6 (R5 pin) is low. 1 = GPI_6 (R5 pin) is high. 0 = GPI_5 (R4 pin) is low. 1 = GPI_5 (R4 pin) is high. 0 = GPI_4 (R3 pin) is low. 1 = GPI_4 (R3 pin) is high. 0 = GPI_3 (R2 pin) is low. 1 = GPI_3 (R2 pin) is high. 0 = GPI_2 (R1 pin) is low. 1 = GPI_2 (R1 pin) is high. 0 = GPI_1 (R0 pin) is low. 1 = GPI_1 (R0 pin) is high. GPI_STATUS_B Register 0x17 Table 31. GPI_STATUS_B Bit Descriptions Bits 7 Name GPI_16_STAT R/W R 6 GPI_15_STAT R 5 GPI_14_STAT R 4 GPI_13_STAT R 3 GPI_12_STAT R 2 GPI_11_STAT R 1 GPI_10_STAT R 0 GPI_9_STAT R Description 0 = GPI_16 (C7 pin) is low. 1 = GPI_16 (C7 pin) is high. 0 = GPI_15 (C6 pin) is low. 1 = GPI_15 (C6 pin) is high. 0 = GPI_14 (C5 pin) is low. 1 = GPI_14 (C5 pin) is high. 0 = GPI_13 (C4 pin) is low. 1 = GPI_13 (C4 pin) is high. 0 = GPI_12 (C3 pin) is low. 1 = GPI_12 (C3 pin) is high. 0 = GPI_11 (C2 pin) is low. 1 = GPI_11 (C2 pin) is high. 0 = GPI_10 (C1 pin) is low. 1 = GPI_10 (C1 pin) is high. 0 = GPI_9 (C0 pin) is low. 1 = GPI_9 (C0 pin) is high. GPI_STATUS_C Register 0x18 Table 32. GPI_STATUS_C Bit Descriptions Bits [7: 3] 2 Name R/W GPI_19_STAT R 1 GPI_18_STAT R 0 GPI_17_STAT R Description Reserved. 0 = GPI_19 (C10 pin) is low. 1 = GPI_19 (C10 pin) is high. 0 = GPI_18 (C9 pin) is low. 1 = GPI_18 (C9 pin) is high. 0 = GPI_17 (C8 pin) is low. 1 = GPI_17 (C8 pin) is high. Rev. B | Page 28 of 52 Data Sheet ADP5589 RPULL_CONFIG_A Register 0x19 Table 33. RPULL_CONFIG_A Bit Descriptions Bits [7:6] Name R3_PULL_CFG R/W R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [5:4] R2_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3:2] R1_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [1: 0] R0_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. ADP5589AC_Z-00-R7, ADP5589AC_Z-01-R7 Default = 0000 0000 ADP5589AC_Z-02-R7 Default = 0100 0001 RPULL_CONFIG_B Register 0x1A Table 34. RPULL_CONFIG_B Bit Descriptions Bits [7 :6] Name R7_PULL_CFG R/W R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [5: 4] R6_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3: 2] R5_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [1: 0] R4_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. ADP5589AC_Z-00-R7, ADP5589AC_Z-01-R7 Default = 0000 0000 ADP5589AC_Z-02-R7 Default = 0000 0001 Rev. B | Page 29 of 52 ADP5589 Data Sheet RPULL_CONFIG_C Register 0x1B Table 35. RPULL_CONFIG_C Bit Descriptions Bits [7 :6] Name C3_PULL_CFG R/W R/W [5: 4] C2_PULL_CFG R/W [3: 2] C1_PULL_CFG R/W [1: 0] C0_PULL_CFG R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. RPULL_CONFIG_D Register 0x1C Table 36. RPULL_CONFIG_D Bit Descriptions Bits [7: 6] Name C7_PULL_CFG R/W R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [5:4] C6_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3: 2] C5_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [1: 0] C4_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. ADP5589AC_Z-00-R7, ADP5589AC_Z-01-R7 Default = 0000 0000 ADP5589AC_Z-02-R7 Default = 0001 0001 Rev. B | Page 30 of 52 Data Sheet ADP5589 RPULL_CONFIG_E Register 0x1D Table 37. RPULL_CONFIG_E Bit Descriptions Bits [7: 6] [5:4] Name R/W Description Reserved. C10_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3: 2] C9_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [1: 0] C8_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. ADP5589AC_Z-00-R7, ADP5589AC_Z-01-R7 Default = 0000 0000 ADP5589AC_Z-02-R7 Default = 0000 0100 GPI_INT_LEVEL_A Register 0x1E Table 38. GPI_INT_LEVEL_A Bit Descriptions Bits 7 Name GPI_8_INT_LEVEL R/W R/W 6 GPI_7_INT_LEVEL R/W 5 GPI_6_INT_LEVEL R/W 4 GPI_5_INT_LEVEL R/W 3 GPI_4_INT_LEVEL R/W 2 GPI_3_INT_LEVEL R/W 1 GPI_2_INT_LEVEL R/W 0 GPI_1_INT_LEVEL R/W Description 0 = GPI_8 interrupt is active low. 1 = GPI_8 interrupt is active high. 0 = GPI_7 interrupt is active low. 1 = GPI_7 interrupt is active high. 0 = GPI_6 interrupt is active low. 1 = GPI_6 interrupt is active high. 0 = GPI_5 interrupt is active low. 1 = GPI_5 interrupt is active high. 0 = GPI_4 interrupt is active low. 1 = GPI_4 interrupt is active high. 0 = GPI_3 interrupt is active low. 1 = GPI_3 interrupt is active high. 0 = GPI_2 interrupt is active low. 1 = GPI_2 interrupt is active high. 0 = GPI_1 interrupt is active low (GPI_1_INT is set whenever R0 is low). 1 = GPI_1 interrupt is active high (GPI_1_INT is set whenever R0 is high). Rev. B | Page 31 of 52 ADP5589 Data Sheet GPI_INT_LEVEL_B Register 0x1F Table 39. GPI_INT_LEVEL_B Bit Descriptions Bits 7 Name GPI_16_INT_LEVEL R/W R/W 6 GPI_15_INT_LEVEL R/W 5 GPI_14_INT_LEVEL R/W 4 GPI_13_INT_LEVEL R/W 3 GPI_12_INT_LEVEL R/W 2 GPI_11_INT_LEVEL R/W 1 GPI_10_INT_LEVEL R/W 0 GPI_9_INT_LEVEL R/W Description 0 = GPI_16 interrupt is active low. 1 = GPI_16 interrupt is active high. 0 = GPI_15 interrupt is active low. 1 = GPI_15 interrupt is active high. 0 = GPI_14 interrupt is active low. 1 = GPI_14 interrupt is active high. 0 = GPI_13 interrupt is active low. 1 = GPI_13 interrupt is active high. 0 = GPI_12 interrupt is active low. 1 = GPI_12 interrupt is active high. 0 = GPI_11 interrupt is active low. 1 = GPI_11 interrupt is active high. 0 = GPI_10 interrupt is active low. 1 = GPI_10 interrupt is active high. 0 = GPI_9 interrupt is active low. 1 = GPI_9 interrupt is active high. GPI_INT_LEVEL_C Register 0x20 Table 40. GPI_INT_LEVEL_C Bit Descriptions Bits [7: 3] 2 Name R/W GPI_19_INT_LEVEL R/W 1 GPI_18_INT_LEVEL R/W 0 GPI_17_INT_LEVEL R/W Description Reserved. 0 = GPI_19 interrupt is active low. 1 = GPI_19 interrupt is active high. 0 = GPI_18 interrupt is active low. 1 = GPI_18 interrupt is active high. 0 = GPI_17 interrupt is active low. 1 = GPI_17 interrupt is active high. GPI_EVENT_EN_A Register 0x21 Table 41. GPI_EVENT_EN_A Bit Descriptions Bits 7 Name GPI_8_EVENT_EN R/W R/W 6 GPI_7_EVENT_EN R/W 5 GPI_6_EVENT_EN R/W 4 GPI_5_EVENT_EN R/W 3 GPI_4_EVENT_EN R/W 2 GPI_3_EVENT_EN R/W 1 GPI_2_EVENT_EN R/W 0 GPI_1_EVENT_EN R/W Description 0 = disable GPI events. 1 = allow GPI 8 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 7 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 6 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 5 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 4 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 3 activity to generate events on the FIFO. 0 =disable GPI events. 1 = allow GPI 2 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 1 activity to generate events on the FIFO. GPIs in this mode are considered FIFO events and can be used for unlock purposes. GPI activity in this mode causes EVENT_INT interrupts. GPIs in this mode do not generate GPI_INT interrupts. Rev. B | Page 32 of 52 Data Sheet ADP5589 GPI_EVENT_EN_B Register 0x22 Table 42. GPI_EVENT_EN_B Bit Descriptions Bits 7 Name GPI_16_EVENT_EN R/W R/W 6 GPI_15_EVENT_EN R/W 5 GPI_14_EVENT_EN R/W 4 GPI_13_EVENT_EN R/W 3 GPI_12_EVENT_EN R/W 2 GPI_11_EVENT_EN R/W 1 GPI_10_EVENT_EN R/W 0 GPI_9_EVENT_EN R/W Description 0 = disable GPI events. 1 = allow GPI 16 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 15 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 14 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 13 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 12 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 11 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 10 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 9 activity to generate events on the FIFO. GPI_EVENT_EN_C Register 0x23 Table 43. GPI_EVENT_EN_C Bit Descriptions Bits [7: 3] 2 Name R/W GPI_19_EVENT_EN R/W 1 GPI_18_EVENT_EN R/W 0 GPI_17_EVENT_EN R/W Description Reserved. 0 = disable GPI events. 1 = allow GPI 19 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 18 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 17 activity to generate events on the FIFO. GPI_INTERRUPT_EN_A Register 0x24 Table 44. GPI_INTERRUPT_EN_A Bit Descriptions Bits 7 Name GPI_8_INT_EN R/W R/W 6 GPI_7_INT_EN R/W 5 GPI_6_INT_EN R/W 4 GPI_5_INT_EN R/W 3 GPI_4_INT_EN R/W 2 GPI_3_INT_EN R/W 1 GPI_2_INT_EN R/W Description 0 = GPI_8_INT is disable. 1 = GPI_8_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_8_INT is set and the GPI interrupt condition is met. 0 = GPI_7_INT is disable. 1 = GPI_7_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_7_INT is set and the GPI interrupt condition is met. 0 = GPI_6_INT is disable. 1 = GPI_6_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_6_INT is set and the GPI interrupt condition is met. 0 = GPI_5_INT is disable. 1 = GPI_5_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_5_INT is set and the GPI interrupt condition is met. 0 = GPI_4_INT is disable. 1 = GPI_4_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_4_INT is set and the GPI interrupt condition is met. 0 = GPI_3_INT is disable. 1 = GPI_3_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_3_INT is set and the GPI interrupt condition is met. 0 = GPI_2_INT is disable. 1 = GPI_2_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_2_INT is set and the GPI interrupt condition is met. Rev. B | Page 33 of 52 ADP5589 0 GPI_1_INT_EN Data Sheet R/W 0 = GPI_1_INT is disable. 1 = GPI_1_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_2_INT is set and the GPI interrupt condition is met. GPI_INTERRUPT_EN_B Register 0x25 Table 45. GPI_INTERRUPT_EN_B Bit Descriptions Bits 7 Name GPI_16_INT_EN R/W R/W 6 GPI_15_INT_EN R/W 5 GPI_14_INT_EN R/W 4 GPI_13_INT_EN R/W 3 GPI_12_INT_EN R/W 2 GPI_11_INT_EN R/W 1 GPI_10_INT_EN R/W 0 GPI_9_INT_EN R/W Description 0 = GPI_16_INT is disabled. 1 = GPI_16_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_16_INT is set and the GPI interrupt condition is met. 0 = GPI_15_INT is disabled. 1 = GPI_15_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_15_INT is set and the GPI interrupt condition is met. 0 = GPI_14_INT is disabled. 1 = GPI_14_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_14_INT is set and the GPI interrupt condition is met. 0 = GPI_13_INT is disabled. 1 = GPI_13_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_13_INT is set and the GPI interrupt condition is met. 0 = GPI_12_INT is disabled. 1 = GPI_12_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_12_INT is set and the GPI interrupt condition is met. 0 = GPI_11_INT is disabled. 1 = GPI_11_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_11_INT is set and the GPI interrupt condition is met. 0 = GPI_10_INT is disabled. 1 = GPI_10_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_10_INT is set and the GPI interrupt condition is met. 0 = GPI_9_INT is disabled. 1 = GPI_9_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_9_INT is set and the GPI interrupt condition is met. GPI_INTERRUPT_EN_C Register 0x26 Table 46. GPI_INTERRUPT_EN_C Bit Descriptions Bits [7: 3] 2 Name R/W GPI_19_INT_EN R/W 1 GPI_18_INT_EN R/W 0 GPI_17_INT_EN R/W Description Reserved. 0 = GPI_19_INT is disabled. 1 = GPI_19_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_19_INT is set and the GPI interrupt condition is met. 0 = GPI_18_INT is disabled. 1 = GPI_18_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_18_INT is set and the GPI interrupt condition is met. 0 = GPI_17_INT is disabled. 1 = GPI_17_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_17_INT is set and the GPI interrupt condition is met. Rev. B | Page 34 of 52 Data Sheet ADP5589 DEBOUNCE_DIS_A Register 0x27 Table 47. DEBOUNCE_DIS_A Bit Descriptions Bits 7 Name GPI_8_DEB_DIS R/W R/W 6 GPI_7_DEB_DIS R/W 5 GPI_6_DEB_DIS R/W 4 GPI_5_DEB_DIS R/W 3 GPI_4_DEB_DIS R/W 2 GPI_3_DEB_DIS R/W 1 GPI_2_DEB_DIS R/W 0 GPI_1_DEB_DIS R/W Description 0 = debounce enabled on GPI 8. 1 = debounce disabled on GPI 8. 0 = debounce enabled on GPI 7. 1 = debounce disabled on GPI 7. 0 = debounce enabled on GPI 6. 1 = debounce disabled on GPI 6. 0 = debounce enabled on GPI 5. 1 = debounce disabled on GPI 5. 0 = debounce enabled on GPI 4. 1 = debounce disabled on GPI 4. 0 = debounce enabled on GPI 3. 1 = debounce disabled on GPI 3. 0 = debounce enabled on GPI 2. 1 = debounce disabled on GPI 2. 0 = debounce enabled on GPI 1. 1 = debounce disabled on GPI 1. DEBOUNCE_DIS_B Register 0x28 Table 48. DEBOUNCE_DIS_B Bit Descriptions Bits 7 Name GPI_16_DEB_DIS R/W R/W 6 GPI_15_DEB_DIS R/W 5 GPI_14_DEB_DIS R/W 4 GPI_13_DEB_DIS R/W 3 GPI_12_DEB_DIS R/W 2 GPI_11_DEB_DIS R/W 1 GPI_10_DEB_DIS R/W 0 GPI_9_DEB_DIS R/W Description 0 = debounce enabled on GPI 16. 1 = debounce disabled on GPI 16. 0 = debounce enabled on GPI 15. 1 = debounce disabled on GPI 15. 0 = debounce enabled on GPI 14. 1 = debounce disabled on GPI 14. 0 = debounce enabled on GPI 13. 1 = debounce disabled on GPI 13. 0 = debounce enabled on GPI 12. 1 = debounce disabled on GPI 12. 0 = debounce enabled on GPI 11. 1 = debounce disabled on GPI 11. 0 = debounce enabled on GPI 10. 1 = debounce disabled on GPI 10. 0 = debounce enabled on GPI 9. 1 = debounce disabled on GPI 9. Rev. B | Page 35 of 52 ADP5589 Data Sheet DEBOUNCE_DIS_C Register 0x29 Table 49. DEBOUNCE_DIS_C Bit Descriptions Bits [7:3] 2 Name R/W GPI_19_DEB_DIS R/W 1 GPI_18_DEB_DIS R/W 0 GPI_17_DEB_DIS R/W Description Reserved. 0 = debounce enabled on GPI 19. 1 = debounce disabled on GPI 19. 0 = debounce enabled on GPI 18. 1 = debounce disabled on GPI 18. 0 = debounce enabled on GPI 17. 1 = debounce disabled on GPI 17. GPO_DATA_OUT_A Register 0x2A Table 50. GPO_DATA_OUT_A Bit Descriptions Bits 7 Name GPO_8_DATA R/W R/W 6 GPO_7_DATA R/W 5 GPO_6_DATA R/W 4 GPO_5_DATA R/W 3 GPO_4_DATA R/W 2 GPO_3_DATA R/W 1 GPO_2_DATA R/W 0 GPO_1_DATA R/W Description 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. GPO_DATA_OUT_B Register 0x2B Table 51. GPO_DATA_OUT_B Bit Descriptions Bits 7 Name GPO_16_DATA R/W R/W 6 GPO_15_DATA R/W 5 GPO_14_DATA R/W 4 GPO_13_DATA R/W 3 GPO_12_DATA R/W 2 GPO_11_DATA R/W 1 GPO_10_DATA R/W 0 GPO_9_DATA R/W Description 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. Rev. B | Page 36 of 52 Data Sheet ADP5589 GPO_DATA_OUT_C Register 0x2C Table 52. GPO_DATA_OUT_C Bit Descriptions Bits [7: 3] 2 Name R/W GPO_19_DATA R/W 1 GPO_18_DATA R/W 0 GPO_17_DATA R/W Description Reserved. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. GPO_OUT_MODE_A Register 0x2D Table 53. GPO_OUT_MODE_A Bit Descriptions Bits 7 Name GPO_8_OUT_MODE R/W R/W 6 GPO_7_OUT_MODE R/W 5 GPO_6_OUT_MODE R/W 4 GPO_5_OUT_MODE R/W 3 GPO_4_OUT_MODE R/W 2 GPO_3_OUT_MODE R/W 1 GPO_2_OUT_MODE R/W 0 GPO_1_OUT_MODE R/W Description 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. GPO_OUT_MODE_B Register 0x2E Table 54. GPO_OUT_MODE_B Bit Descriptions Bits 7 Name GPO_16_OUT_MODE R/W R/W 6 GPO_15_OUT_MODE R/W 5 GPO_14_OUT_MODE R/W 4 GPO_13_OUT_MODE R/W 3 GPO_12_OUT_MODE R/W 2 GPO_11_OUT_MODE R/W 1 GPO_10_OUT_MODE R/W 0 GPO_9_OUT_MODE R/W Description 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. Rev. B | Page 37 of 52 ADP5589 Data Sheet GPO_OUT_MODE_C Register 0x2F Table 55. GPO_OUT_MODE_C Bit Descriptions Bits [7: 3] 2 Name R/W GPO_19_DIR R/W 1 GPO_18_DIR R/W 0 GPO_17_DIR R/W Description Reserved. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. GPIO_DIRECTION_A Register 0x30 Table 56. GPIO_DIRECTION_A Bit Descriptions Bits 7 Name GPIO_8_DIR R/W R/W 6 GPIO_7_DIR R/W 5 GPIO_6_DIR R/W 4 GPIO_5_DIR R/W 3 GPIO_4_DIR R/W 2 GPIO_3_DIR R/W 1 GPIO_2_DIR R/W 0 GPIO_1_DIR R/W Description 0 = GPIO 8 is an input. 1 = GPIO 8 is an output. 0 = GPIO 7 is an input. 1 = GPIO 7 is an output. 0 = GPIO 6 is an input. 1 = GPIO 6 is an output. 0 = GPIO 5 is an input. 1 = GPIO 5 is an output. 0 = GPIO 4 is an input. 1 = GPIO 4 is an output. 0 = GPIO 3 is an input. 1 = GPIO 3 is an output. 0 = GPIO 2 is an input. 1 = GPIO 2 is an output. 0 = GPIO 1 is an input. 1 = GPIO 1 is an output. GPIO_DIRECTION_B Register 0x31 Table 57. GPIO_DIRECTION_B Bit Descriptions Bits 7 Name GPIO_16_DIR R/W R/W 6 GPIO_15_DIR R/W 5 GPIO_14_DIR R/W 4 GPIO_13_DIR R/W 3 GPIO_12_DIR R/W 2 GPIO_11_DIR R/W 1 GPIO_10_DIR R/W 0 GPIO_9_DIR R/W Description 0 = GPIO 16 is an input. 1 = GPIO 16 is an output. 0 = GPIO 15 is an input. 1 = GPIO 15 is an output. 0 = GPIO 14 is an input. 1 = GPIO 14 is an output. 0 = GPIO 13 is an input. 1 = GPIO 13 is an output. 0 = GPIO 12 is an input. 1 = GPIO 12 is an output. 0 = GPIO 11 is an input. 1 = GPIO 11 is an output. 0 = GPIO 10 is an input. 1 = GPIO 10 is an output. 0 = GPIO 9 is an input. 1 = GPIO 9 is an output. Rev. B | Page 38 of 52 Data Sheet ADP5589 GPIO_DIRECTION_C Register 0x32 Table 58. GPIO_DIRECTION_C Bit Descriptions Bits [7:3] 2 Name R/W GPIO_19_DIR R/W 1 GPIO_18_DIR R/W 0 GPIO_17_DIR R/W Description Reserved. 0 = GPIO 19 is an input. 1 = GPIO 19 is an output. 0 = GPIO 18 is an input. 1 = GPIO 18 is an output. 0 = GPIO 17 is an input. 1 = GPIO 17 is an output. UNLOCK1 Register 0x33 Table 59. UNLOCK1 Bit Descriptions Bits 7 Name UNLOCK1_STATE R/W R/W [6:0] UNLOCK1[6:0] R/W Description Defines which state the first unlock event should be For key events: 0 = not applicable; releases not used for unlock. 1 = press is used as unlock event. For GPIs and logic outputs configured for FIFO updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines the first event that must be detected to unlock the keypad after LOCK_EN has been set. UNLOCK2 Register 0x34 Table 60. UNLOCK2 Bit Descriptions Bits 7 Name UNLOCK2_STATE R/W R/W [6:0] UNLOCK2[6:0] R/W Description Defines which state the second unlock event should be. For key events: 0 = not applicable; releases not used for unlock. 1 = press is used as unlock event. For GPIs and logic outputs configured for FIFO updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines the second event that must be detected to unlock the keypad after LOCK_EN has been set. EXT_LOCK_EVENT Register 0x35 Table 61. EXT_LOCK_EVENT Bit Descriptions Bits 7 Name EXT_LOCK_STATE R/W R/W [6:0] EXT_LOCK_EVENT[6:0] R/W Description Defines which state the lock event should be. For key events: 0 = not applicable; releases not used for unlock. 1 = press is used as unlock event. For GPIs and logic outputs configured for FIFO updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines an event that can lock the keypad. When this event is detected, LOCK_INT is set. Rev. B | Page 39 of 52 ADP5589 Data Sheet UNLOCK_TIMERS Register 0x36 Table 62. UNLOCK_TIMERS Bit Descriptions Bits [7: 3] Name INT_MASK_TIMER[4:0] R/W R/W [2: 0] UNLOCK_TIMER[2:0] R/W Description If the keypad is locked and this timer is set, any key event (or GPI/logic event programmed to FIFO update) is allowed to generate an EVENT_INT interrupt. This timer then begins counting, and no further events generate an interrupt until this timer has expired (or both unlock events have occurred). 00000 = disabled. 00001 = 1 sec. 00010 = 2 sec. 11110 = 30 sec. 11111 = 31 sec. Defines the time in which the second unlock event must occur after the first unlock event has occurred. If the second unlock event does not occur within this time (or any other event occurs), the keypad goes back to full lock mode. 000 = disabled. 001 = 1 sec. 010 = 2 sec. 011 = 3 sec. 100 = 4 sec. 101 = 5 sec. 110 = 6 sec. 111 = 7 sec. LOCK_CFG Register 0x37 Table 63. LOCK_CFG Bit Descriptions Bits [7:1] 0 Name R/W LOCK_EN R/W Description Reserved. Enable the lock function. RESET1_EVENT_A Register 0x38 Table 64. RESET1_EVENT_A Bit Descriptions Bits 7 Name RESET1_EVENT_A Level R/W R/W [6:0] RESET1_EVENT_A[6:0] R/W Description Defines which level the first reset event should be. For key events: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. For GPIs and logic outputs configured for FIFO updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines an event that can be used to generate the RESET1 signal. Up to three events can be defined for generating the RESET1 signal, using RESET1_EVENT_A[6:0], RESET1_EVENT_B[6:0], and RESET1_EVENT_C[6:0]. If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. RESET1_EVENT_B Register 0x39 Table 65. RESET1_EVENT_B Bit Descriptions Bits 7 [6: 0] Name RESET1_EVENT_B Level RESET1_EVENT_B[6:0] R/W R/W R/W Description Defines which level the second reset event should be. Defines an event that can be used to generate the RESET1 signal. Rev. B | Page 40 of 52 Data Sheet ADP5589 RESET1_EVENT_C Register 0x3A Table 66. RESET1_EVENT_C Bit Descriptions Bits 7 [6: 0] Name RESET1_EVENT_B Level RESET1_EVENT_C[6:0] R/W R/W R/W Description Defines which level the third reset event should be. Defines an event that can be used to generate the RESET1 signal. RESET2_EVENT_A Register 0x3B Table 67. RESET2_EVENT_A Bit Descriptions Bits 7 Name RESET1_EVENT_B Level R/W R/W [6:0] RESET2_EVENT_A[6:0] R/W Description Defines which level the first reset event should be. For key events: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. For GPIs and logic outputs configured for FIFO updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines an event that can be used to generate the RESET2 signal. Up to two events can be defined for generating the RESET2 signal, using RESET2_EVENT_A[6:0] and RESET2_EVENT_B[6:0]. If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. RESET2_EVENT_B Register 0x3C Table 68. RESET2_EVENT_B Bit Descriptions Bits 7 [6:0] Name RESET1_EVENT_B Level RESET2_EVENT_B[6:0] R/W R/W R/W Description Defines which level the second reset event should be. Defines an event that can be used to generate the RESET2 signal. Description Sets the polarity of RESET2. 0 = RESET2 is active low. 1 = RESET2 is active high. Sets the polarity of RESET1. 0 = RESET1 is active low. 1 = RESET1 is active high. Allows the RST pin to override (OR with) the RESET1signal. Function not applicable to RESET2. Defines the length of time that the reset events must be active before a reset signal is generated. All events must be active at the same time for the same duration. Parameter common to both RESET1 and RESET2. 000 = immediate. 001 = 1.0 sec. 010 = 1.5 sec. 011 = 2.0 sec. 100 = 2.5 sec. 101 = 3.0 sec. 110 = 3.5 sec. 111 = 4.0 sec. RESET_CFG Register 0x3D Table 69. RESET_CFG Bit Descriptions Bits 7 Name RESET2_POL R/W R/W 6 RESET1_POL R/W 5 RST_PASSTHRU_EN R/W [4:2] RESET_TRIGGER_TIME[2:0] R/W Rev. B | Page 41 of 52 ADP5589 Bits [1:0] Data Sheet Name RESET_PULSE_WIDTH[1:0] R/W R/W Description Defines the pulse width of the reset signals. Parameter common to both RESET1 and RESET2. 00 = 500 µs. 01 = 1 ms. 10 = 2 ms. 11 = 10 ms. ADP5589AC_Z-00-R7, ADP5589AC_Z-02-R7 Default = 0000 0000 ADP5589AC_Z-01-R7 Default = 0010 0000 PWM_OFFT_LOW Register 0x3E Table 70. PWM_OFFT_LOW Bit Descriptions Bits [7: 0] Name PWM_OFFT_LOW_BYTE[7:0] R/W R/W Description Lower eight bits of PWM off time. PWM_OFFT_HIGH Register 0x3F Table 71. PWM_OFFT_HIGH Bit Descriptions Bits [7: 0] Name PWM_OFFT_HIGH_BYTE[7:0] R/W R/W Description Upper eight bits of PWM off time. PWM_ONT_LOW Register 0x40 Table 72. PWM_ONT_LOW Bit Descriptions Bits [7:0] Name PWM_ONT_LOW_BYTE[7:0] R/W R/W Description Lower eight bits of PWM on time. PWM_ONT_HIGH Register 0x41 Table 73. PWM_ONT_HIGH Bit Descriptions Bits [7:0] Name PWM_ONT_HIGH_BYTE[7:0] R/W R/W Description Upper eight bits of PWM on time. Note that updated PWM times are not latched until this byte is written to. PWM count times are referenced from the internal oscillator. The fastest oscillator setting is 500 kHz (1 µs increments). Therefore, maximum on/off time is 1 µs × (216 −1) = 65.5 ms This gives PWM frequencies from 500 kHz down to 7.6 Hz. PWM_CFG Register 0x42 Table 74. PWM_CFG Bit Descriptions Bits [7:3] 2 1 Name R/W PWM_IN_AND PWM_MODE R/W R/W 0 PWM_EN R/W Description Reserved. AND the internally generated PWM signal with an externally supplied PWM signal (C6). Defines PWM mode. 0 = continuous. 1 = one shot. If a one-shot is performed, the PWM_EN bit is automatically cleared. If a second one-shot must be performed, the user must set PWM_EN again. Enable PWM generator. Rev. B | Page 42 of 52 Data Sheet ADP5589 CLOCK_DIV_CFG Register 0x43 Table 75. CLOCK_DIV_CFG Bit Descriptions Bits 7 6 [5: 1] Name R/W CLK_INV CLK_DIV[4:0] R/W R/W 0 CLK_DIV_EN R/W Description Reserved. Inverts the divided down clock signal. Defines the divide down scale of the externally supplied clock. 00000 = divide by 1 (pass-through). 00001 = divide by 2. 00010 = divide by 3. 00011 = divide by 4. 11111 = divide by 32. Enables the clock divider circuit to divide down the externally supplied clock signal. LOGIC_1_CFG Register 0x44 Table 76. LOGIC_1_CFG Bit Descriptions Bits 7 6 Name R/W LY1_INV R/W 5 LC1_INV R/W 4 LB1_INV R/W 3 LA1_INV R/W [2: 0] LOGIC1_SEL[2:0] R/W Description Reserved. 0 = LY1 output not inverted before passing into Logic Block 1. 1 = inverts output LY1 from Logic Block 1. 0 = LC1 input not inverted before passing into Logic Block 1. 1 = inverts input LC1 before passing it into Logic Block 1. 0 = LB1 input not inverted before passing into Logic Block 1. 1 = inverts input LB1 before passing it into Logic Block 1. 0 = LA1 input not inverted before passing into Logic Block 1. 1 = inverts input LA1 before passing it into Logic Block 1. Configures the digital mux for Logic Block 1. 000 = off/disable. 001 = AND1. 010 = OR1. 011 = XOR1. 100 = FF1. 101 = IN_LA1. 110 = IN_LB1. 111 = IN_LC1. LOGIC_2_CFG Register 0x45 Table 77. LOGIC_2_CFG Bit Descriptions Bits 7 Name LY1_CASCADE R/W R/W 6 LY2_INV R/W 5 LC2_INV R/W 4 LB2_INV R/W 3 LA2_INV R/W Description 0 = use Input LA2 for Logic Block 2. 1 = use Output LY1 from Logic Block 1 instead of LA2 as the input for Logic Block 2. The R0 pin can be used as GPIO or key when cascade is in use. 0 = LY2 input not inverted before passing into Logic Block 2. 1 = inverts Output LY2 from Logic Block 2. 0 = LC2 input not inverted before passing into Logic Block 2. 1 = inverts Input LC2 before passing it into Logic Block 2. 0 = LB2 input not inverted before passing into Logic Block 2. 1 = inverts Input LB2 before passing it into Logic Block 2. 0 = LA2 input not inverted before passing into Logic Block 2. 1 = inverts Input LA2 before passing it into Logic Block 2. Rev. B | Page 43 of 52 ADP5589 Bits [2: 0] Data Sheet Name LOGIC2_SEL[2:0] R/W R/W Description Configures the digital mux for Logic Block 2. 000 = off/disable. 001 = AND2. 010 = OR2. 011 = XOR2. 100 = FF2. 101 = IN_LA2. 110 = IN_LB2. 111 = IN_LC2. LOGIC_FF_CFG Register 0x46 Table 78. LOGIC_FF_CFG Bit Descriptions Bits [7: 4] 3 Name FF2_SET R/W R/W R/W 2 FF2_CLR R/W 1 FF1_SET R/W 0 FF1_CLR R/W Description Reserved. 0 = FF2 not set in Logic Block 2. 1 = set FF2 in Logic Block 2. 0 = FF2 not cleared in Logic Block 2. 1 = clear FF2 in Logic Block 2. 0 = FF1 not set in Logic Block 1. 1 = set FF1 in Logic Block 1. 0 = FF1 not cleared in Logic Block 1. 1 = clear FF1 in Logic Block 1. LOGIC_INT_EVENT_EN Register 0x47 Table 79. LOGIC_INT_EVENT_EN Bit Descriptions Bits [7: 6] 5 Name LY2_DBNC_DIS R/W R/W R/W 4 LOGIC2_EVENT_EN R/W 3 LOGIC2_INT_LEVEL R/W 2 LY1_DBNC_DIS R/W 1 LOGIC1_EVENT_EN R/W 0 LOGIC1_INT_LEVEL R/W Description Reserved. 0 = output of Logic Block 2 is debounced before entering the event/interrupt block. 1 = output of Logic Block 2 is not debounced before entering the event/interrupt block. Use with caution because glitches may generate interrupts prematurely. 0 = LY2 cannot generate interrupt. 1 = allow LY2 activity to generate events on the FIFO. Configure the logic level of LY2 that generates an interrupt. 0 = LY2 is active low. 1 = LY2 is active high. 0 = output of Logic Block 1 is debounced before entering the event/interrupt block. 1 = output of Logic Block 1 is not debounced before entering the event/interrupt block. Use with caution because glitches may generate interrupts prematurely. 0 = LY1 cannot generate interrupt. 1 = allow LY1 activity to generate events on the FIFO. Configure the logic level of LY1 that generates an interrupt. 0 = LY1 is active low. 1 = LY1 is active high. POLL_TIME_CFG Register 0x48 Table 80. POLL_TIME_CFG Bit Descriptions Bits [7: 2] [1: 0] Name R/W KEY_POLL_TIME[1:0] R/W Description Reserved. Configure time between consecutive scan cycles. 00 = 10 ms. 01 = 20 ms. 10 = 30 ms. 11 = 40 ms. Rev. B | Page 44 of 52 Data Sheet ADP5589 PIN_CONFIG_A Register 0x49 Table 81. PIN_CONFIG_A Bit Descriptions Bits 7 Name R7_CONFIG R/W R/W 6 R6_CONFIG R/W 5 R5_CONFIG R/W 4 R4_CONFIG R/W 3 R3_CONFIG R/W 2 R2_CONFIG R/W 1 R1_CONFIG R/W 0 R0_CONFIG R/W Description 0 = GPIO 8. 1 = Row 7. 0 = GPIO 7. 1 = Row 6. 0 = GPIO 6. 1 = Row 5. 0 = GPIO 5 (see R4_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, RESET1). 1 = Row 4. 0 = GPIO 4 (see R3_EXTEND_CFG[1:0] in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, LC1/PWM_OUT/CLK_OUT). 1 = Row 3. 0 = GPIO 3. 1 = Row 2. 0 = GPIO 2. 1 = Row 1. 0 = GPIO 1 (see R0_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, LY1). 1 = Row 0. PIN_CONFIG_B Register 0x4A Table 82. PIN_CONFIG_B Bit Descriptions Bits 7 Name C7_CONFIG R/W R/W 6 C6_CONFIG R/W 5 C5_CONFIG R/W 4 C4_CONFIG R/W 3 C3_CONFIG R/W 2 C2_CONFIG R/W 1 C1_CONFIG R/W 0 C0_CONFIG R/W Description 0 = GPIO 16. 1 = Column 7. 0 = GPIO 15 (see C6_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, LC2). 1 = Column 6. 0 = GPIO 14. 1 = Column 5. 0 = GPIO 13 (see C4_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, RESET2). 1 = Column 4. 0 = GPIO 12. 1 = Column 3. 0 = GPIO 11. 1 = Column 2. 0 = GPIO 10. 1 = Column 1. 0 = GPIO 9. 1 = Column 0. PIN_CONFIG_C Register 0x4B Table 83. PIN_CONFIG_C Bit Descriptions Bits [7: 3] 2 Name R/W C10_CONFIG R/W 1 C9_CONFIG R/W 0 C8_CONFIG R/W Description Reserved. 0 = GPIO 19. 1 = Column 10. 0 = GPIO 18 (see C9_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, LY2). 1 = Column 9. 0 = GPIO 17. 1 = Column 8. Rev. B | Page 45 of 52 ADP5589 Data Sheet PIN_CONFIG_D Register 0x4C Table 84. PIN_CONFIG_D Bit Descriptions Bits 7 Name PULL_SELECT R/W R/W Description 0 = 300 kΩ used for row pull-up during key scanning. 1 = 100 kΩ used for row pull-up during key scanning. 6 C4_EXTEND_CFG R/W 0 = C4 remains configured as GPIO 13. 1 = C4 reconfigured as RESET2 output. 5 R4_EXTEND_CFG R/W 0 = R4 remains configured as GPIO 5. 1 = R4 reconfigured as RESET1 output. 4 C6_EXTEND_CFG R/W 0 = C6 remains configured as GPIO 15. 1 = C6 reconfigured as LC2 input for Logic Block 2. [3:2] R3_EXTEND_CFG[1:0] R/W 00 = R3 remains configured as GPIO 4. 01 = R3 reconfigured as LC1 input for Logic Block 1. 10 = R3 reconfigured as PWM_OUT/CLK_OUT outputs from PWM and clock divider blocks. 11 = unused. 1 C9_EXTEND_CFG R/W 0 = C9 remains configured as GPIO 18. 1 = C9 reconfigured as LY2 output from Logic Block 2. 0 R0_EXTEND_CFG R/W 0 = R0 remains configured as GPIO 1. 1 = R0 reconfigured as LY1 output from Logic Block 1. ADP5589AC_Z-00-R7, ADP5589AC_Z-02-R7 Default = 0000 0000 ADP5589AC_Z-01-R7 Default = 0010 0000 GENERAL_CFG_B Register 0x4D Table 85. GENERAL_CFG_B Bit Descriptions Bits 7 Name OSC_EN R/W R/W [6:5] CORE_FREQ[1:0] R/W 4 LCK_TRK_LOGIC R/W 3 LCK_TRK_GPI R/W 2 1 INT_CFG R/W 0 RST_CFG R/W Description 0 = disable internal 1 MHz oscillator. 1 = enable internal 1 MHz oscillator. Sets the input clock frequency fed from the base 1 MHz oscillator to the digital core. Slower frequencies result in less IDD. However, key and GPI scan times increase. 00 = 50 kHz. 01 = 100 kHz. 10 = 200 kHz. 11 = 500 kHz. 0 = allow logic outputs (programmed for FIFO updates) to be tracked on the FIFO if the keypad is locked. 1 = do not track. 0 = allow GPIs (programmed for FIFO updates) to be tracked on the FIFO if the keypad is locked. 1 = do not track. Unused Configure the behavior of the INT pin if the user tries to clear it while an interrupt is pending. 0 = INT pin remains asserted if an interrupt is pending. 1 = INT pin deasserts for 50 µs and reasserts if an interrupt is pending. Configure the response ADP5589 has to the RST pin. 0 = ADP5589 resets if RST is low. 1 = ADP5589 does not reset if RST is low. Rev. B | Page 46 of 52 Data Sheet ADP5589 INT_EN Register 0x4E Table 86. INT_EN Bit Descriptions Bits [7: 6] 5 Name R/W Description Reserved. 0 = Logic 2 interrupt is disabled. 1 = assert the INT pin if LOGIC2_INT is set. LOGIC2_IEN R/W 4 LOGIC1_IEN R/W 0 = Logic 1 interrupt is disabled. 1 = assert the INT pin if LOGIC1_INT is set. 3 LOCK_IEN R/W 0 = lock interrupt is disabled. 1 = assert the INT pin if LOCK_INT is set. 2 OVRFLOW_IEN R/W 0 = overflow interrupt is disabled. 1 = assert the INT pin if OVRFLOW_INT is set. 1 GPI_IEN R/W 0 = GPI interrupt is disabled. 1 = assert the INT pin if GPI_INT is set. 0 EVENT_IEN R/W 0 = event interrupt is disabled. 1 = assert the INT pin if EVENT_INT is set. Rev. B | Page 47 of 52 ADP5589 Data Sheet APPLICATION DIAGRAM VDD INT RST HOST PROCESSOR SCL SDA VDD KP/LOGIC1 OUTPUT/GPI/GPO KP/LOGIC1 INPUT/GPI/GPO SDA KP/LOGIC1 INPUT/GPI/GPO SCL RST VDD ADP5589 KP/LOGIC1 INPUT/GPI/GPO/PWM/CLK KP/RESET1 OUTPUT/GPI/GPO 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 OSCILLATOR R0 R1 KEY SCAN AND DECODE R2 R3 INT R4 GPI SCAN AND DECODE R5 R6 R7 LOGIC1 C10 C9 C8 C7 C6 C5 I/O CONFIG LOGIC2 REGISTERS CLK DIV PWM C4 C3 C2 C1 C0 RESET1 GEN RESET2 GEN GND Figure 31. Typical Configuration Rev. B | Page 48 of 52 09714-030 1 12 13 14 15 16 17 18 19 20 21 22 I2C INTERFACE UVLO POR Data Sheet ADP5589 OUTLINE DIMENSIONS 3.60 3.50 SQ 3.40 PIN 1 INDICATOR 0.25 0.20 0.15 PIN 1 INDICATOR 24 19 18 0.40 BSC 1 EXPOSED PAD 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE 7 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-13-2012-A 0.80 0.75 0.70 6 13 12 0.50 0.40 0.30 TOP VIEW 2.30 2.20 SQ 2.10 COMPLIANT TO JEDEC STANDARDS MO-220-WFFE. Figure 32. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3.5 mm × 3.5 mm Body, Very Very Thin Quad (CP-24-11) Dimensions shown in millimeters 2.030 1.990 SQ 1.950 5 4 3 2 1 A BALL A1 IDENTIFIER B 1.60 REF C D 0.40 REF TOP VIEW (BALL SIDE DOWN) 0.560 0.500 0.440 E BOTTOM VIEW (BALL SIDE UP) SIDE VIEW SEATING PLANE 0.300 0.260 0.220 0.230 0.200 0.170 11-02-2012-A COPLANARITY 0.05 Figure 33. 25-Ball Wafer Level Chip Scale Package [WLCSP] (CB-25-5) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5589ACPZ-00-R7 ADP5589ACPZ-01-R7 ADP5589ACPZ-02-R7 ADP5589ACBZ-00-R7 ADP5589ACBZ-01-R7 ADP5589ACBZ-02-R7 ADP5589CP-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package[LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package[LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package[LFCSP_WQ] 25-Ball Wafer Level Chip Scale Package[WLCSP] 25-Ball Wafer Level Chip Scale Package[WLCSP] 25-Ball Wafer Level Chip Scale Package[WLCSP] Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 49 of 52 Package Option CP-24-11 CP-24-11 CP-24-11 CB-25-5 CB-25-5 CB-25-5 ADP5589 Data Sheet NOTES Rev. B | Page 50 of 52 Data Sheet ADP5589 NOTES Rev. B | Page 51 of 52 ADP5589 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09714-0-1/13(B) Rev. B | Page 52 of 52