950 MHz to 1575 MHz Quadrature Modulator with Integrated Fractional-N PLL and VCO ADRF6750 FEATURES GENERAL DESCRIPTION I/Q modulator with integrated fractional-N PLL and VCO Gain control span: 47 dB in 1 dB steps Output frequency range: 950 MHz to 1575 MHz Output 1 dB compression: 8.5 dBm Output IP3: 23 dBm Noise floor: −162 dBm/Hz Baseband modulation bandwidth: 250 MHz (1 dB) Output frequency resolution: 1 Hz Functions with external VCO for extended frequency range SPI and I2C-compatible serial interfaces Power supply: 5 V/310 mA The ADRF6750 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. The device covers an operating frequency range from 950 MHz to 1575 MHz for use in satellite, cellular and broadband communications. The ADRF6750 modulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and a 47 dB digitally controlled output attenuator with 1 dB steps. Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 4.75 V to 5.25 V. FUNCTIONAL BLOCK DIAGRAM VCC1 REGOUT VREG1 VREG2 VREG3 VREG4 VREG5 VREG6 LOMONP LOMONN VCC2 VCC3 VCC4 3.3V REGULATOR IBBP IBBN CCOMP1 CCOMP2 CCOMP3 47dB GAIN CONTROL RANGE 0°/90° OUTPUT STAGE VCO CORE RFOUT VTUNE TESTLO TESTLO TXDIS QBBP QBBN RSET REFERENCE REFIN ×2 DOUBLER 5-BIT DIVIDER ÷2 + PHASE FREQUENCY – DETECTOR REFIN CHARGE PUMP CURRENT SETTING N-COUNTER SDI/SDA CLK/SCL SDO CS SPI/ I2C INTERFACE THIRD-ORDER FRACTIONAL INTERPOLATOR FRACTIONAL REGISTER MODULUS 225 RFCP4 RFCP3 RFCP2 RFCP1 CP LF3 LF2 LDET INTEGER REGISTER AGND 08201-001 ADRF6750 DGND Figure 1. Rev. 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ADRF6750 TABLE OF CONTENTS Features .............................................................................................. 1 I2C Interface ................................................................................ 21 General Description ......................................................................... 1 SPI Interface ................................................................................ 23 Functional Block Diagram .............................................................. 1 Program Modes .......................................................................... 25 Revision History ............................................................................... 2 Register Map ................................................................................... 27 Specifications..................................................................................... 3 Register Map Summary ............................................................. 27 Timing Characteristics ................................................................ 5 Register Bit Descriptions ........................................................... 28 Absolute Maximum Ratings............................................................ 7 Suggested Power-Up Sequence ..................................................... 31 ESD Caution .................................................................................. 7 Initial Register Write Sequence ................................................ 31 Pin Configuration and Function Descriptions ............................. 8 Evaluation Board ............................................................................ 32 Typical Performance Characteristics ........................................... 10 General Description ................................................................... 32 Theory of Operation ...................................................................... 18 Hardware Description ............................................................... 32 Overview...................................................................................... 18 PCB Artwork............................................................................... 35 PLL Synthesizer and VCO ......................................................... 18 Bill of Materials ........................................................................... 38 Quadrature Modulator .............................................................. 20 Outline Dimensions ....................................................................... 39 Attenuator .................................................................................... 21 Ordering Guide .......................................................................... 39 Voltage Regulator ....................................................................... 21 EXTERNAL vco OPERATION ................................................ 21 REVISION HISTORY 4/10—Rev. 0 to Rev. A Changes to Table 5 ............................................................................ 9 Changes to LOMON Outputs Section ......................................... 33 Changes to Ordering Guide .......................................................... 39 1/10—Revision 0: Initial Version Rev. A | Page 2 of 40 ADRF6750 SPECIFICATIONS VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, REFIN = 10 MHz, PFD = 20 MHz, loop bandwidth = 50 kHz, and LOMONx is off, unless otherwise noted. Table 1. Parameter RF OUTPUT Operating Frequency Range Nominal Output Power Gain Flatness Output P1dB Output IP3 Output Return Loss LO Carrier Feedthrough 2× LO Carrier Feedthrough Sideband Suppression Noise Floor Harmonics REFERENCE CHARACTERISTICS Input Frequency Input Sensitivity Input Capacitance Input Current CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Value VCO Gain SYNTHESIZER SPECIFICATIONS Frequency Resolution Spurs Phase Noise 1 Integrated Phase Noise1 Frequency Settling1 Maximum Frequency Step for No Autocalibration Phase Detector Frequency Test Conditions/Comments RFOUT pin Min Typ 950 VIQ = 0.9 V p-p differential Any 40 MHz Unit 1575 MHz dBm dB dBm dBm dB dBc dBm dBc dBm/Hz dBc/Hz dBm/Hz dBc 300 165 VREG 10 ±100 MHz MHz V p-p pF μA −1.6 ±0.5 8.5 23 −12 −45 −45 −45 −162 −147 −170 −60 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −6 dBm per tone Attenuator setting = 0 dB Attenuator setting = 0 dB to 47 dB Attenuator setting = 0 dB to 47 dB I/Q inputs = 0 V p-p differential, Attenuator setting = 0 dB Attenuator setting = 0 dB to 21 dB, carrier offset = 15 MHz Attenuator setting = 21 dB to 47 dB, carrier offset = 15 MHz REFIN pin With R/2 divider enabled With R/2 divider disabled AC-coupled Max 10 10 0.4 Programmable With RSET = 4.7 kΩ 5 312.5 4.0 4.7 25 With RSET = 4.7 kΩ KVCO mA μA % kΩ MHz/V 1 Integer boundary < loop bandwidth >10 MHz offset from carrier Frequency = 950 MHz to 1575 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset >15 MHz offset 1 kHz to 8 MHz integration bandwidth Maximum frequency error = 100 Hz Frequency step with no autocalibration routine; Register CR24, Bit 0 = 1 −55 −85 −80 −88 −93 −107 −133 −152 0.4 170 10 Rev. A | Page 3 of 40 Hz dBc dBc 100 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms μs kHz 30 MHz ADRF6750 Parameter GAIN CONTROL Gain Range Step Size Relative Step Accuracy Absolute Step Accuracy 2 Output Settling Time OUTPUT DISABLE Off Isolation Turn-On Settling Time Turn-Off Settling Time MONITOR OUTPUT Nominal Output Power BASEBAND INPUTS I and Q Input Bias Level 1 dB Bandwidth LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLIES Voltage Range Supply Current Operating Temperature 1 2 Test Conditions/Comments Min Fixed frequency, adjacent steps All attenuation steps Over full frequency range, adjacent steps 47 dB attenuation step Any step; output power settled to ±0.2 dB TXDIS pin RF OUT, attenuator setting = 0 dB to 47 dB, TXDIS high LO, Attenuator setting = 0 dB to 47 dB, TXDIS high 2 x LO, Attenuator setting = 0 dB to 47 dB, TXDIS high TXDIS high to low (90% of envelope) TXDIS low to high (to −55 dBm) LOMONP, LOMONN pins Typ Max Unit 47 1 dB dB ±0.3 ±1.5 −2.0 10 dB dB dB μs −110 −90 −50 180 270 dBm dBm dBm ns ns −24 dBm 500 250 mV MHz IBBP, IBBN, QBBP, QBBN pins CS, TXDIS pins CS, TXDIS pins SDI/SDA, CLK/SCL pins SDI/SDA, CLK/SCL pins CS, TXDIS, SDI/SDA, CLK/SCL pins CS, TXDIS, SDI/SDA, CLK/SCL pins 1.4 Rev. A | Page 4 of 40 0.4 0.4 V V V 2.1 SDO, LDET pins; IOH = 500 μA 2.8 SDO, LDET pins; IOL = 500 μA SDA (SDI/SDA); IOL = 3 mA VCC1, VCC2, VCC3, VCC4, VREG1, VREG2, VREG3, VREG4, VREG5, VREG6, and REGOUT pins REGOUT normally connected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 VCC1, VCC2, VCC3, and VCC4 4.75 REGOUT, VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 VCC1, VCC2, VCC3, and VCC4 combined; REGOUT connected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 −40 LBW = 50 kHz at LO = 1200 MHz; ICP = 2.5 mA. All other attenuation steps have an absolute error of <±2.0 dB. 1.1 ±1 10 V V V V μA pF 0.6 5 3.3 310 5.25 340 V V mA +85 °C ADRF6750 TIMING CHARACTERISTICS I2C Interface Timing Table 2. Parameter 1 SCL Clock Frequency SCL Pulse Width High SCL Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Valid Time Data Valid Acknowledge Time Bus Free Time Limit 400 600 1300 600 600 100 300 600 900 900 1300 Unit kHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min tVD;DAT AND tVD;ACK (ACK SIGNAL ONLY) tBUF See Figure 2. tSU;DAT SDA tSU;STA tHD;STA tSU;STO tLOW SCL S START CONDITION 1/fSCL tHD;DAT S tHIGH P STOP CONDITION Figure 2. I2C Port Timing Diagram Rev. A | Page 5 of 40 S 08201-003 1 Symbol fSCL tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tSU;STO tVD;DAT tVD;ACK tBUF ADRF6750 SPI Interface Timing Table 3. Parameter 1 CLK Frequency CLK Pulse Width High CLK Pulse Width Low Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time SDO Access Time CS to SDO High Impedance Limit 20 15 15 5 10 5 5 15 25 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns max See Figure 3. t3 CS t1 CLK t6 t2 SDI t4 t5 SDO t7 Figure 3. SPI Port Timing Diagram Rev. A | Page 6 of 40 t8 08201-004 1 Symbol fCLK t1 t2 t3 t4 t5 t6 t7 t8 ADRF6750 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage VCC1, VCC2, VCC3, and VCC4 Supply Voltage VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 IBBP, IBBN, QBBP, and QBBN Digital I/O Analog I/O (Other Than IBBP, IBBN, QBBP, and QBBN) TESTLO, TESTLO Difference θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +6 V −0.3 V to +4 V 0 V to 2.5 V −0.3 V to +4 V −0.3 V to +4 V ESD CAUTION 1.5 V 26°C/W 120°C −65°C to +150°C Rev. A | Page 7 of 40 ADRF6750 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VCC2 VCC2 AGND AGND AGND AGND AGND AGND RFOUT AGND AGND TXDIS LDET MUXOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR ADRF6750 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VCC3 VCC3 AGND AGND VTUNE AGND VREG6 CCOMP3 CCOMP2 CCOMP1 DGND VREG5 CLK/SCL SDI/SDA NOTES 1. CONNECT EXPOSED PAD TO GROUND PLANE VIA A LOW IMPEDANCE PATH. 08201-005 VREG3 VREG4 REFIN REFIN AGND AGND AGND TESTLO TESTLO AGND LOMONP LOMONN CS SDO 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC4 IBBP IBBN QBBN QBBP AGND RSET LF3 CP LF2 VCC1 REGOUT VREG1 VREG2 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 11, 55, 56, 41, 42, 1 Mnemonic VCC1 to VCC4 12 13, 14, 15, 16, 31, 36 6, 19, 20, 21, 24, 37, 39, 40, 46, 47, 49, 50, 51, 52, 53, 54 32 2, 3 REGOUT VREG1 to VREG6 AGND DGND IBBP, IBBN 4, 5 QBBN, QBBP 33, 34, 35 38 CCOMP1 to CCOMP3 VTUNE 7 RSET 9 CP Description Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same 5 V power supply. 3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6. Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT (3.3 V) and decouple them separately. Analog Ground. Connect to a low impedance ground plane. Digital Ground. Connect to the same low impedance ground plane as the AGND pins. Differential In-Phase Baseband Inputs. These high impedance inputs must be dc-biased to approximately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are not self-biased and must be externally biased. Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to approximately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are not self-biased and must be externally biased. Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor. Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is as follows: 23.5 ICPmax = RSET where RSET = 4.7 kΩ and ICP max = 5 mA. Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter, which, in turn, drives the internal VCO. Rev. A | Page 8 of 40 ADRF6750 Pin No. 27 Mnemonic CS 29 SDI/SDA 30 CLK/SCL 28 17 18 48 SDO REFIN REFIN RFOUT 45 TXDIS 25, 26 LOMONP, LOMONN 22, 23 TESTLO, TESTLO 10, 8 44 LF2, LF3 LDET 43 MUXOUT Exposed Paddle EP Description Chip Select, CMOS Input. When CS is high, the data stored in the shift registers is loaded into one of 31 latches. In I2C mode, when CS is high, the slave address of the device is 0x60, and when CS is low, the slave address is 0x40. Serial Data Input for SPI Port/Serial Data Input/Output for I2C Port. In SPI mode, this pin is a high impedance CMOS data input, and data is loaded in an 8-bit word. In I2C mode, this pin is a bidirectional port. Serial Clock Input for SPI/I2C Port. This serial clock is used to clock in the serial data to the registers. This input is a high impedance CMOS input. Serial Data Output for SPI Port. Register states can be read back on the SDO data output line. Reference Input. This high impedance CMOS input should be ac-coupled. Reference Input Bar. This pin should be either grounded or ac-coupled to ground. RF Output. Single-ended, 50 Ω, internally biased RF output. This pin must be ac-coupled to the load. Nominal output power is −1.6 dBm for a single sideband baseband drive of 0.9 V p-p differential on the I and Q inputs (attenuation = minimum). Output Disable. This pin can be used to disable the RF output. Connect to high logic level to disable the output. Connect to low logic level for normal operation. Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to REGOUT. These outputs can be disabled through serial port programming and should be tied to REGOUT if not used. Differential Test Inputs. These inputs provide an option for an external 2× LO to drive the modulator. This option can be selected by serial port programming. These inputs must be externally dc-biased and should be grounded if not used. No connect pins. Lock Detect. This output pin indicates the state of the PLL: a high level indicates a locked condition, whereas a low level indicates a loss of lock condition. Muxout. This output is a test output for diagnostic use only. It should be left unconnected by the customer. Exposed Paddle. Connect to ground plane via a low impedance path. Rev. A | Page 9 of 40 ADRF6750 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, REFIN = 10 MHz, PFD = 20 MHz, baseband frequency = 1 MHz, LOMONx is off, unless otherwise noted. A nominal condition is defined as 25°C, 5.00 V, and worst-case frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency. 2 0 +25°C; 5.00V SIDEBAND SUPPRESSION (dBc) LO FREQUENCY (MHz) 950 LO FREQUENCY (MHz) Figure 5. Output Power vs. LO Frequency, Supply, and Temperature 08201-108 –60 08201-105 1550 1575 1450 1350 1250 1150 1050 950 –5 –50 1550 1575 +70°C; 5.25V 1500 0°C; 4.75V 1450 +70°C; 4.75V +85°C; 5.25V 1400 0°C; 5.25V -40°C; 5.25V 1350 -40°C; 4.75V +85°C; 4.75V 1300 +25°C; 5.00V 1250 –4 –40 1150 –3 –30 1200 –2 –40°C; 4.75V –40°C; 5.25V –20 1100 –1 +85°C; 5.25V 1050 0 +85°C; 4.75V –10 1000 OUTPUT POWER (dBm) 1 Figure 8. Sideband Suppression vs. LO Frequency, Supply, and Temperature 40 35 NOMINAL 35 WORST CASE 30 25 OCCURRENCE (%) OCCURRENCE (%) NOMINAL WORST CASE 30 25 20 15 20 15 10 10 5 5 08201-109 –32.5 –35.0 –37.5 –40.0 –42.5 –45.0 –47.5 –50.0 –52.5 –55.0 SIDEBAND SUPPRESSION (dBc) Figure 6. Output Power Distribution at Nominal and Worst-Case Conditions Figure 9. Sideband Suppression Distribution at Nominal and Worst-Case Conditions 1 –40 –45 CARRIER FEEDTHROUGH (dBc) 0 –1 –2 –3 –4 –50 –55 –60 –65 –70 LO FREQUENCY (MHz) –80 1550 1575 2000 1450 1750 1350 1500 1250 1250 1150 1000 1050 750 950 –5 500 LO FREQUENCY (MHz) Figure 10. LO Carrier Feedthrough vs. Attenuation, LO Frequency, Supply, and Temperature Figure 7. Output Power vs. LO Frequency for External VCO Mode at Nominal Conditions Rev. A | Page 10 of 40 08201-110 –75 08201-107 OUTPUT POWER (dBm) –57.5 –62.5 08201-106 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2.2 –2.4 –2.6 –2.8 –3.0 –3.2 OUTPUT POWER (dBm) –60.0 0 0 ADRF6750 60 50 NOMINAL WORST-CASE 45 NOMINAL WORST-CASE 50 40 35 OCCURENCE (%) OCCURENCE (%) 40 30 20 30 25 20 15 10 10 –35 –30 LO CARRIER FEEDTHROUGH (dBc) 0 6.8 –50 10.0 –60 9.5 OUTPUT P1dB (dBm) –70 –80 –90 ATTENUATION = 0dB ATTENUATION = 12dB ATTENUATION = 21dB ATTENUATION = 33dB ATTENUATION = 47dB 8.4 8.6 8.8 9.0 9.2 8.5 8.0 7.5 –20 –2.0 –25 –2.5 10 08201-116 1550 1575 1500 1450 1400 1350 1300 1250 15 10 5 0 OUTPUT IP3 (dBm) Figure 13. Output P1dB Compression Point at Worst-Case LO Frequency vs. Supply and Temperature Rev. A | Page 11 of 40 Figure 16. Output IP3 Distribution at Nominal and Worst-Case Conditions 08201-115 –1.5 24.00 –15 20 23.75 –1.0 23.50 –10 25 23.25 –0.5 23.00 –5 30 22.75 0 WORST-CASE 35 22.50 1dB COMPRESSION POINT NOMINAL 40 22.25 0.5 45 OCCURENCE (%) 5 Figure 15. Output P1dB Compression Point vs. LO Frequency at Nominal Conditions IDEAL OUTPUT POWER – OUTPUT POWER (dBm) 1.0 1200 LO FREQUENCY (MHz) 08201-113 10 1150 950 08201-112 1550 1575 1450 1350 1250 1150 1050 950 8.2 6.0 Figure 12. 2 × LO Carrier Feedthrough vs. Attenuation, LO Frequency, Supply, and Temperature OUTPUT POWER (dBm) 8.0 6.5 LO FREQUENCY (MHz) 1 DIFFERENTIAL INPUT VOLTAGE (V p-p) 7.8 7.0 –120 0.1 7.6 9.0 21.00 2 × LO CARRIER FEEDTHROUGH (dBm) 10.5 0 7.4 Figure 14. Output P1dB Compression Point Distribution at Nominal and Worst-Case Conditions –40 –110 7.2 OUTPUT P1dB (dBm) Figure 11. LO Carrier Feedthrough Distribution at Nominal and Worst-Case Conditions and Attenuation Setting –100 7.0 22.00 –40 1100 –45 21.75 –50 1050 –55 21.50 –60 1000 –65 21.25 –70 08201-111 –75 08201-114 5 0 –80 ADRF6750 30 –40 29 –50 UPPER THIRD HARMONIC (fLO + 3 × fBB) –60 OUTPUT POWER (dBc) –90 08201-128 LOWER THIRD HARMONIC (fLO – 3 × fBB) 950 08201-119 1550 1575 1500 1450 1400 1350 1300 1250 1150 1050 1200 –120 1100 20 1000 –110 950 21 OUTPUT IP3 INTERCEPT POINT (dBm) LO FREQUENCY (MHz) Figure 17. Output IP3 vs. LO Frequency at Nominal Conditions Figure 20. Second-Order and Third-Order Harmonic Distortion vs. LO Frequency, Supply, and Temperature –60 100 –70 90 ATTENUATION = 47dB (dBm/Hz) ATTENUATION = 21dB (dBc/Hz) 80 –80 LO OFF ISOLATION (dBm) LOWER SECOND HARMONIC (fLO – 2 × fBB) –100 22 1550 1575 23 –80 1450 24 1350 25 UPPER SECOND HARMONIC (fLO + 2 × fBB) –70 1250 26 1150 27 1050 LO FREQUENCY (MHz) 28 ATTENUATION = 0dB OCCURENCE (%) 70 –90 –100 ATTENUATION = 21dB –110 ATTENUATION = 21dB (dBm/Hz) 60 50 ATTENUATION = 0dB (dBc/Hz) 40 30 –120 20 –130 ATTENUATION = 47dB 08201-117 1550 1575 1500 1450 1400 1350 1300 1250 1200 1150 1100 1050 1000 950 LO FREQUENCY (MHz) 0 –180 –176 –172 –168 –164 –160 –156 –152 –148 –144 –140 (dBm/Hz) NOISE FLOOR AT 15MHz OFFSET FREQUENCY (dBc/Hz) 08201-121 10 –140 Figure 21. Noise Floor at 15 MHz Offset Frequency Distribution at Worst-Case Conditions and Different Attenuation Settings Figure 18. LO Off Isolation vs. Attenuation, LO Frequency, Supply, and Temperature –20 –140 –40 –145 ATTENUATION = 0dB NOISE FLOOR (dBm/Hz) 2 × LO OFF ISOLATION (dBm) –30 –50 ATTENUATION = 21dB –60 –70 –80 –90 ATTENUATION = 47dB –150 –155 –160 –100 –165 1550 1575 1500 1450 08201-118 LO FREQUENCY (MHz) 1400 1350 1300 1250 1150 1200 1100 1050 1000 950 –120 Figure 19. 2 × LO Off Isolation vs. Attenuation, LO Frequency, Supply, and Temperature Rev. A | Page 12 of 40 –170 –25 –20 –15 –10 –5 0 5 OUTPUT POWER (dBm) Figure 22. Noise Floor at 0 dB Attenuation vs. Output Power at Nominal Conditions 10 08201-120 –110 ADRF6750 0 LOWER SIDEBAND –10 0 –20 RF OUTPUT (dBm) NORMALIZED OUTPUT POWER (dB) 1 –1 –2 –3 –30 CARRIER FEEDTHROUGH –40 SUPPRESSED SIDEBAND –50 –60 THIRD HARMONIC –70 LOWER AND UPPER SECOND HARMONICS –4 1 10M 100M 1G I AND Q BASEBAND INPUT FREQUENCY (Hz) –90 1150 08201-141 –5 1170 1190 1210 1230 08201-123 –80 1250 LO FREQUENCY (MHz) Figure 23. Normalized I and Q Input Bandwidth Figure 26. RF Output Spectral Plot over a 100 MHz Span 0 0 LOWER SIDEBAND –10 –5 –20 ATTENUATION = 0dB POWER (dBm) S22 (dB) –10 –15 3 × LO HARMONIC –30 –40 2 × LO HARMONIC 4 × LO HARMONIC 5 × LO HARMONIC 8 × LO HARMONIC –50 –20 ATTENUATION = 21dB AND 47dB –60 –25 750 1000 1250 1500 OUTPUT FREQUENCY (MHz) 1750 2000 –80 08201-150 –30 500 0 Figure 24. Output Return Loss at Worst-Case Attenuation vs. LO Frequency, Supply, and Temperature 7 8 9 10 –80 SUPPRESSED SIDEBAND 50 THIRD HARMONIC SECOND HARMONIC –90 –100 –110 –120 –130 70 –140 80 –150 90 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 –160 100 LO FREQUENCY (MHz) Figure 25. RF Output Spectral Plot over a 10 MHz Span 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 100M Figure 28. Phase Noise Performance vs. LO Frequency, Supply, and Temperature Rev. A | Page 13 of 40 08201-129 PHASE NOISE (dBc/Hz) CARRIER FEEDTHROUGH 08201-122 RF OUTPUT (dBm) 6 4 5 FREQUENCY (MHz) –70 30 60 3 –60 LOWER SIDEBAND 20 40 2 Figure 27. RF Output Spectral Plot over a Wide Span 0 10 1 08201-124 –70 ADRF6750 –60 SPURS > 10MHz OFFSET FREQUENCY (dBc) –60 –70 –90 –100 –110 –120 –130 –140 –150 –70 –80 –90 –100 –110 1600 1625 LO FREQUENCY (MHz) Figure 32. Spurs > 10 MHz from Carrier vs. LO Frequency, Supply, and Temperature Figure 29. Phase Noise Performance Distribution at Worst-Case Conditions 0.50 –40 +25°C; 5.00V 0.45 +85°C; 4.75V –45 0.40 +85°C; 5.25V –40°C; 4.75V –50 RMS JITTER (Degrees) INTEGER BOUNDARY SPUR (dBc) 08201-127 1500 1400 1300 1200 100M 1100 10M 10k 100k 1M OFFSET FREQUENCY (Hz) 1000 1k 08201-130 –120 –160 100 900 PHASE NOISE (dBc/Hz) –80 PFD SPURS AT 20MHz OFFSET REFERENCE SPURS AT 10MHz OFFSET –40°C; 5.25V –55 –60 –65 0.35 0.30 0.25 0.20 0.15 0.10 –70 0.05 LO FREQUENCY (MHz) Figure 30. Integer Boundary Spur Performance vs. LO Frequency, Supply, and Temperature 08201-131 1550 1575 1500 1450 1400 1350 1300 1250 1200 1150 1100 1050 1000 950 1550 1575 LO FREQUENCY (MHz) 08201-125 1450 1350 1250 1150 1050 950 0 Figure 33. Integrated Phase Noise vs. LO Frequency at Nominal Conditions 80 60 NOMINAL WORST CASE 70 50 NOMINAL WORST CASE OCCURENCE (%) 50 40 30 40 30 20 20 0 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 INTEGER BOUNDARY SPURS (dBc) Figure 31. Integer Boundary Spur Distribution at Nominal and Worst-Case Conditions 0 0.275 0.300 0.325 0.350 0.375 0.400 0.425 0.450 0.475 0.500 RMS JITTER (Degrees) Figure 34. Integrated Phase Noise at Nominal and Worst-Case Conditions Rev. A | Page 14 of 40 08201-137 10 10 08201-126 OCCURENCE (%) 60 ADRF6750 100M 45 10M 40 1M 35 OCCURENCE (%) 50 100k ACQUISITION TO 100Hz 10k START OF ACQUISITION ON CR0 WRITE 1k 30 25 20 10 50 –5 45 –10 40 –15 35 ATTENUATOR RELATIVE STEP ACCURACY (dB) 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 2.25 08201-140 2.00 1.75 0.5 0.3 0.1 –0.1 –0.3 –0.5 –0.7 –0.9 –1.1 –1.3 Figure 37. Attenuator Relative Step Accuracy over all Attenuation Steps vs. LO Frequency, Nominal Conditions 2000 1900 1800 1700 08201-136 LO FREQUENCY (MHz) 1600 1500 1400 1300 1200 1100 500 –1.5 08201-134 1550 1575 1500 1450 1400 1350 1300 1250 1150 1200 1100 –1.0 1050 1.50 Figure 39. Attenuator Relative Step Accuracy Across Full Output Frequency Range Distribution at Nominal and Worst-Case Conditions 1.0 1000 1.25 ATTENUATOR RELATIVE STEP ACCURACY ACROSS FULL OUTPUT FREQUENCY RANGE (dB) Figure 36. Attenuator Gain vs. LO Frequency by Gain Code, All Attenuator Code Steps 950 1.00 –2.25 08201-133 1550 1575 1500 1450 1400 1350 1250 1300 1200 1100 0 1150 5 –50 1050 –45 1000 10 950 15 –40 0.75 20 –35 LO FREQUENCY (MHz) 08201-135 25 0.50 –30 30 0 –25 0.25 –20 NOMINAL WORST CASE –0.25 OCCURENCE (%) 0 LO FREQUENCY (MHz) 1.0 Figure 38. Attenuator Relative Step Accuracy Distribution at Nominal and Worst-Case Conditions –0.50 Figure 35. PLL Frequency Settling Time at Worst-Case Low Frequency with Lock Detect Shown –0.75 TIME (µs) 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 ATTENUATOR RELATIVE STEP ACCURACY (dB) –1.00 100 125 150 175 200 225 250 1000 75 –1.25 50 900 25 –1.50 0 800 0.1 –50 –25 5 –1.75 CR23[3] = 0 700 LDET –2.00 CR23[3] = 1 08201-132 LDET 1 OUPTUT POWER (dBm) WORST CASE 15 100 10 ATTENUATOR RELATIVE STEP ACCURACY (dB) NOMINAL 600 FREQUENCY ERROR (Hz) 1G Figure 40. Attenuator Relative Step Accuracy over all Attenuation Steps vs. LO Frequency for External VCO Mode, Nominal Conditions Rev. A | Page 15 of 40 0.5 1.0 0.8 GAIN FLATNESS IN ANY 40MHz (dB) 0 –0.5 –1.0 –1.5 –2.0 –2.5 0.4 0.2 0 –0.2 –0.4 –0.6 LO FREQUENCY (MHz) 1550 1575 08201-149 1500 1450 1400 1350 1300 1250 1150 1200 1100 1050 950 08201-139 1550 1575 1500 1450 1400 1350 1300 1250 1150 1200 1100 1050 1000 1000 1.0 LO FREQUENCY (MHz) Figure 44. Gain Flatness in any 40 MHz for all Attenuation Steps vs. LO Frequency at Nominal Conditions Figure 41. Attenuator Absolute Step Accuracy over all Attenuation Steps vs. LO Frequency, Nominal Conditions 5.0 70 NOMINAL WORST CASE 60 4.5 4.0 SETTLING TIME (µs) 50 OCCURENCE (%) 0.6 –0.8 –3.0 950 ATTENUATOR ABSOLUTE STEP ACCURACY (dB) ADRF6750 40 30 20 SETTLING TIME TO 0.2dB SETTLING TIME TO 0.5dB 3.5 3.0 INCREASING STEP SIZE 2.5 2.0 1.5 1.0 10 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2.2 –2.4 –2.6 –2.8 –3.0 –3.2 –3.4 ATTENUATOR ABSOLUTE STEP ACCURACY (dB) 08201-138 0 0 Figure 45. Attenuator Settling Time to 0.2 dB and 0.5 dB for Small Steps (1 dB to 6 dB) at Nominal Conditions 20 1.5 18 1.0 SETTLING TIME TO 0.2dB SETTLING TIME TO 0.5dB 16 SETTLING TIME (µs) 0.5 0 –0.5 –1.0 –1.5 14 12 INCREASING STEP SIZE 10 8 6 4 –2.0 0 2000 1900 1800 1700 7dB TO 47dB ATTENUATOR STEP SIZES 08201-142 LO FREQUENCY (MHz) 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 –2.5 Figure 43. Attenuator Absolute Step Accuracy over all Attenuation Steps vs. LO Frequency for External VCO Mode, Nominal Conditions 08201-144 2 500 ATTENUATOR ABSOLUTE STEP ACCURACY (dB) Figure 42. Attenuator Absolute Step Accuracy Distribution at Nominal and Worst-Case Conditions 1dB TO 6dB ATTENUATOR STEP SIZES 08201-143 0.5 Figure 46. Attenuator Settling Time to 0.2 dB and 0.5 dB for Large Steps (7 dB to 47 dB) at Nominal Conditions Rev. A | Page 16 of 40 ADRF6750 100 80 NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.5dB WORST-CASE SETTLING TIME TO 0.2dB WORST-CASE SETTLING TIME TO 0.5dB 90 80 70 NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.5dB WORST-CASE SETTLING TIME TO 0.2dB WORST-CASE SETTLING TIME TO 0.5dB 60 OCCURENCE (%) OCCURENCE (%) 70 60 50 40 50 40 30 30 20 20 10 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ATTENUATOR SETTLING TIME (µs) Figure 47. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Typical Small Step 0 3 6 9 12 15 18 21 24 27 30 ATTENUATOR SETTLING TIME (µs) 08201-148 0 08201-146 0 0 Figure 50. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Worst-Case Large Step (47 dB to 0 dB) 100 0 90 –10 OUTPUT POWER (dBm) 80 OCCURENCE (%) 70 60 NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.5dB WORST-CASE SETTLING TIME TO 0.2dB WORST-CASE SETTLING TIME TO 0.5dB 50 40 30 –20 TURN-ON = 180ns –30 TURN-OFF = 270ns –40 –50 20 –60 10 2 4 6 8 10 12 14 16 ATTENUATOR SETTLING TIME (µs) 18 20 08201-145 0 –70 0 100 90 80 NOMINAL SETTLING TIME TO 0.2dB NOMINAL SETTLING TIME TO 0.5dB WORST-CASE SETTLING TIME TO 0.2dB WORST-CASE SETTLING TIME TO 0.5dB OCCURENCE (%) 60 50 40 30 20 0 2 4 6 8 10 12 14 16 ATTENUATOR SETTLING TIME (µs) 18 20 08201-147 10 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TXDIS SETTLING TIME (µs) Figure 48. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Worst-Case Small Step (36 dB to 42 dB) 70 0.5 Figure 49. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at Nominal and Worst-Case Conditions for Typical Large Step (0 dB to 47 dB) Rev. A | Page 17 of 40 Figure 51. TXDIA Turn-On Settling Time at Worst-Case Supply and Temperature 08201-151 TXDIS 0 ADRF6750 OVERVIEW The ADRF6750 device can be divided into the following basic building blocks: TO PFD ÷2 Figure 53. Reference Input Path fPFD = fREFIN × [(1 + D)/(R × (1 + T))] (2) where: fREFIN is the reference input frequency. D is the doubler bit. R is the programmed divide ratio of the binary 5-bit programmable reference divider (1 to 32). T is the divide-by-2 bit (0 or 1). Each of these building blocks is described in detail in the sections that follow. PLL SYNTHESIZER AND VCO RF Fractional-N Divider Overview The phase-locked loop (PLL) consists of a fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing a frequency resolution of less than 1 Hz over the entire frequency range. It also has an integrated voltage-controlled oscillator (VCO) with a fundamental output frequency ranging from 1900 MHz to 3150 MHz. This allows the PLL to generate a stable frequency at 2× LO, which is then divided down to provide a local oscillator (LO) frequency ranging from 950 MHz to 1575 MHz to the quadrature modulator. Reference Input Section The reference input stage is shown in Figure 52. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are open. This ensures that there is no loading of the REFIN pin at power-down. POWER-DOWN CONTROL 100kΩ TO R-DIVIDER SW2 REFIN NC 5-BIT R-DIVIDER The PFD frequency equation is PLL synthesizer and VCO Quadrature modulator Attenuator Voltage regulator I2C/SPI interface NC ×2 DOUBLER The RF fractional-N divider allows a division ratio in the PLL feedback path that can range from 23 to 4095. The relationship between the fractional-N divider and the LO frequency is described in the following section. INT and FRAC Relationship The integer (INT) and fractional (FRAC) values make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD) frequency. See the Example—Changing the LO Frequency section for more information. The LO frequency equation is LO = fPFD × (INT + (FRAC/225)) where: LO is the local oscillator frequency. fPFD is the PFD frequency. INT is the integer component of the required division factor and is controlled by the CR6 and CR7 registers. FRAC is the fractional component of the required division factor and is controlled by the CR0 to CR3 registers. BUFFER RF N-DIVIDER NC 08201-006 SW1 SW3 (1) FROM VCO OUTPUT DIVIDERS N = INT + FRAC/225 TO PFD N-COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR Figure 52. Reference Input Stage Reference Input Path The on-chip reference frequency doubler allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves the in-band phase noise performance by 3 dBc/Hz. The 5-bit R-divider allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed. An additional divide-by-2 function in the reference input path allows for a greater division range. INT REG FRAC VALUE 08201-007 • • • • • FROM REFIN PIN 08201-008 THEORY OF OPERATION Figure 54. RF Fractional-N Divider Phase Frequency Detector (PFD) and Charge Pump The PFD takes inputs from the R-divider and the N-counter and produces an output proportional to the phase and frequency difference between them (see Figure 55 for a simplified schematic). The PFD includes a fixed delay element that sets the width of the antibacklash pulse, ensuring that there is no dead zone in the PFD transfer function. Rev. A | Page 18 of 40 ADRF6750 HI D1 Q1 UP The autocalibration time is set to 50 μs. During this time, the VCO VTUNE is disconnected from the output of the loop filter and is connected to an internal reference voltage. A typical frequency acquisition is shown in Figure 57. U1 +IN CLR1 DELAY CHARGE PUMP U3 1G CP CLR2 DOWN D2 Q2 08201-009 U2 –IN Figure 55. PFD Simplified Schematic Lock Detect (LDET) LDET (Pin 44) signals when the PLL has achieved lock to an error frequency of less than 100 Hz. On a write to Register CR0, a new PLL acquisition cycle starts, and the LDET signal goes low. When lock has been achieved, this signal returns high. 10M 1M AUTOCAL TIME (µs) 100k 10k ACQUISITION TO 100Hz 1k 100 10 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 TIME (µs) 08201-158 HI FREQUENCY ERROR (Hz) 100M Figure 57. PLL Acquisition Voltage-Controlled Oscillator (VCO) The VCO core in the ADRF6750 consists of two separate VCOs, each with 16 overlapping bands. Figure 56 shows an acquisition plot demonstrating both the VCO overlap at roughly 1260 MHz and the multiple overlapping bands within each VCO. The choice of two 16-band VCOs allows a wide frequency range to be covered without a large VCO sensitivity (KVCO) and resultant poor phase noise and spurious performance. Note that the VCO range is larger than the 2× LO frequency range of the part to ensure that the device has enough margin to cover the full frequency range over all conditions. After autocalibration, normal PLL action resumes and the correct frequency is acquired to within a frequency error of 100 Hz in 170 μs typically. For a maximum cumulative step of 100 kHz, autocalibration can be turned off by Register CR24, Bit 0. This enables cumulative PLL acquisitions of 100 kHz or less to occur without the autocalibration procedure, which improves acquisition times significantly (see Figure 58). 100k 2.5 FREQUENCY ERROR (Hz) 2.3 2.1 VTUNE (V) 1.9 1.7 1.5 1.3 10k 1k ACQUISITION TO 100Hz 100 1.1 0.5 800 10 08201-057 0.7 900 1000 1100 1200 1300 1400 1500 1600 0 50 100 TIME (µs) 1700 150 200 08201-159 0.9 Figure 58. PLL Acquisition Without Autocalibration for 100 kHz Step LO FREQUENCY (MHz) Figure 56. VTUNE vs. LO Frequency The correct VCO and band are chosen automatically by the VCO and band select circuitry when Register CR0 is updated. This is referred to as autocalibration. The VCO displays a variation of KVCO as VTUNE varies within the band and from band to band. Figure 59 shows how the KVCO varies across the full LO frequency range. Also shown is the average value for each of the frequency bands. Figure 59 is useful when calculating the loop filter bandwidth and individual loop filter components. Rev. A | Page 19 of 40 ADRF6750 40 CURRENT OUTPUT DAC (EXAMPLE: AD9779) ADRF6750 35 IBBP 50Ω 25 50Ω OUT1_N IBBN 20 OUT2_N 15 QBBN 50Ω 10 5 08201-013 50Ω OUT2_P QBBP Figure 61. Establishing DC Bias Level on Baseband Inputs LO FREQUENCY (MHz) 08201-160 1550 1575 1450 1350 1250 1150 1050 950 0 Figure 59. KVCO vs. LO Frequency QUADRATURE MODULATOR Overview A basic block diagram of the ADRF6750 quadrature modulator circuit is shown in Figure 60. The VCO generates a signal at the 2× LO frequency, which is then divided down to give a signal at the LO frequency. This signal is then split into in-phase and quadrature components to provide the LO signals that drive the mixers. The differential baseband inputs (QBBP, QBBN, IBBN, and IBBP) consist of the bases of PNP transistors, which present a high impedance of about 30 kΩ in parallel with roughly 2 pF of capacitance. The impedance looks like 30 kΩ below 1 MHz and starts to roll off at higher frequency. A 100 Ω differential termination is recommended at the baseband inputs, and this dominates the input impedance as seen by the input baseband signal. This ensures that the input impedance, as seen by the input circuit, remains flat across the baseband bandwidth. See Figure 62 for a typical configuration. CURRENT OUTPUT DAC (EXAMPLE: AD9779) V-TO-I IBBP IBBN ADRF6750 OUT1_P IBBP 50Ω VCO 50Ω LOWPASS FILTER 100Ω OUT1_N RFOUT TO ATTENUATOR BALUN QUAD PHASE SPLITTER IBBN ÷2 OUT2_N QBBN 50Ω V-TO-I 08201-012 QBBP QBBN 50Ω OUT2_P LOWPASS FILTER 100Ω QBBP 08201-014 VCO SENSITIVITY (MHz/V) OUT1_P 30 Figure 60. Block Diagram of the Quadrature Modulator Figure 62. Typical Baseband Input Configuration The I and Q baseband input signals are converted to currents by the V-to-I stages, which then drive the two mixers. The outputs of these mixers combine to feed the output balun, which provides a single-ended output. This single-ended output is then fed to the attenuator and, finally, to the external RFOUT signal pin. The swing of the AD9779 output currents ranges from 0 mA to 20 mA. The ac voltage swing is 1 V p-p single-ended or 2 V p-p differential with the 50 Ω resistors in place. The 100 Ω differential termination resistors at the baseband inputs have the effect of limiting this swing without changing the dc bias condition of 500 mV. The low-pass filter is used to filter the DAC outputs and remove images when driving a modulator. Baseband Inputs The baseband inputs, QBBP, QBBN, IBBP, and IBBN, must be driven from a differential source. The nominal drive level of 0.9 V p-p differential (450 mV p-p on each pin) should be biased to a common-mode level of 500 mV dc. To set the dc bias level at the baseband inputs, refer to Figure 61. The average output current on each of the AD9779 outputs is 10 mA. A current of 10 mA flowing through each of the 50 Ω resistors to ground produces the desired dc bias of 500 mV at each of the baseband inputs. Another consideration is that the baseband inputs actually source a current of 240 μA out of each of the four inputs. This current must be taken into account when setting up the dc bias of 500 mV. In the initial example based on Figure 61, an error of 12 mV occurs due to the 240 μA current flowing through the 50 Ω resistor. Analog Devices, Inc., recommends that the accuracy of the dc bias should be 500 mV ±25 mV. It is also important that this 240 μA current have a dc path to ground. Rev. A | Page 20 of 40 ADRF6750 Optimization The carrier feedthrough and the sideband suppression performance of the ADRF6750 can be improved over the numbers specified in Table 1 by using the following optimization techniques. Carrier Feedthrough Nulling Carrier feedthrough results from dc offsets that occur between the P and N inputs of each of the differential baseband inputs. Normally these inputs are set to a dc bias of approximately 500 mV. However, if a dc offset is introduced between the P and N inputs of either or both I and Q inputs, the carrier feedthrough is affected in either a positive or a negative fashion. Note that the dc bias level remains at 500 mV (average P and N level). The I channel offset is often held constant while the Q channel offset is varied until a minimum carrier feedthrough level is obtained. Then, while retaining the new Q channel offset, the I channel offset is adjusted until a new minimum is reached. This is usually performed at a single frequency and, thus, is not optimized over the complete frequency range. Multiple optimizations at different frequencies must be performed to ensure optimum carrier feedthrough across the full frequency range. Sideband Suppression Nulling Sideband suppression results from relative gain and relative phase offsets between the I channel and Q channel and can be optimized through adjustments to those two parameters. Adjusting only one parameter improves the sideband suppression only to a point. For optimum sideband suppression, an iterative adjustment between phase and amplitude is required. ATTENUATOR The digital attenuator consists of six attenuation blocks: 1 dB, 2 dB, 4 dB, 8 dB, and two 16 dB blocks; each is separately controlled. Each attenuation block consists of field effect transistor (FET) switches and resistors that form either a pishaped or a T-shaped attenuator. By controlling the states of the FET switches through the control lines, each attenuation block can be set to the pass state (0 dB) or the attenuation state (n dB). The various combinations of the six blocks provide the attenuation states from 0 dB to 47 dB in 1 dB increments. VOLTAGE REGULATOR The voltage regulator is powered from a 5 V supply that is provided by VCC1 (Pin 11) and produces a 3.3 V nominal regulated output voltage, REGOUT, on Pin 12. This pin must be connected (external to the IC) to the VREG1 through VREG6 package pins. The regulator output (REGOUT) should be decoupled by a parallel combination of 10 pF and 220 μF capacitors. The 220 μF capacitor, which is recommended for best performance, decouples broadband noise, leading to better phase noise. Each VREGx pin should have the following decoupling capacitors: 100 nF multilayer ceramic with an additional 10 pF in parallel, both placed as close as possible to the DUT power supply pins. X7R or X5R capacitors are recommended. See the Evaluation Board section for more information. EXTERNAL VCO OPERATION The ADRF6750 can be operated with an external VCO. This can be useful if the user wants to improve the phase noise performance or extend the frequency range. Note that the external VCO needs to operate at a frequency of 2× LO. To operate the ADRF6750 with an external VCO, follow these steps: 1. Connect the charge pump output (Pin 9) to the loop filter and onward to the external VCO input. The KVCO of the external VCO needs to be taken into account when calculating the loop bandwidth and loop filter components. Note that a 50 kHz loop bandwidth is recommended when using the internal VCO. This takes into account the phase noise performance of the internal VCO. It is possible for an external VCO to provide better phase noise performance and a 50 kHz loop bandwidth may not be optimal in that case. When selecting a loop bandwidth, consider rms jitter, phase noise performance, and acquisition time. ADISimPLL™ can be used to optimize the loop bandwidth with a variety of external VCOs. 2. Connect the output of the external VCO to the TESTLO and TESTLO input pins. It is likely that a low-pass filter will be needed to filter the output of the external VCO. This is very important if the external VCO has poor second harmonic performance. Second harmonic performance directly impacts sideband suppression performance. For example, −30 dBc second harmonic performance leads to −30 dBc sideband suppression. Both TESTLO and TESTLO need to be dc biased. A dc bias of 1.7 V to 3.3 V is recommended. The REGOUT output provides a 3.3 V output voltage. 3. Select external VCO operation by setting the following bits: • Set Register CR27[3] = 1. This bit multiplexes the TESTLO and TESTLO through to the quadrature modulator. • Set Register CR28[5] = 1. This bit powers down the internal VCO and connects the external VCO to the PLL. 4. Set the correct polarity for the PFD based on the slope of the KVCO. The default is for positive polarity. This bit is accessed by Register CR12[3]. When selecting an external VCO, at times it is difficult to select one with an appropriate frequency range and KVCO. One solution may be the ADF4350, which can function as VCO only with a range of 137.5 MHz to 4.4 GHz. Note that the ADF4350 requires an autocalibration time of 100 μs which directly impacts acquisition time. I2C INTERFACE The ADRF6750 supports a 2-wire, I2C-compatible serial bus that drives multiple peripherals. The serial data (SDA) and serial Rev. A | Page 21 of 40 ADRF6750 first byte indicates that the master writes information to the peripheral. Logic 1 on the LSB of the first byte indicates that the master reads information from the peripheral. clock (SCL) inputs carry information between any devices that are connected to the bus. Each slave device is recognized by a unique address. The ADRF6750 has two possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address is set to 1. Bit 5 of the slave address is set by the CS pin (Pin 27). Bits[4:0] of the slave address are set to all 0s. The slave address consists of the seven MSBs of an 8-bit word. The LSB of the word sets either a read or a write operation (see Figure 63). Logic 1 corresponds to a read operation, whereas Logic 0 corresponds to a write operation. The ADRF6750 acts as a standard slave device on the bus. The data on the SDA pin (Pin 29) is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADRF6750 has 34 subaddresses to enable the user-accessible internal registers. Therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. Autoincrement mode is supported, which allows data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. To control the device on the bus, the following protocol must be followed. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices then withdraw from the bus and maintain an idle condition. During the idle condition, the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. If an invalid subaddress is issued by the user, the ADRF6750 does not issue an acknowledge and returns to the idle condition. In a no acknowledge condition, the SDA line is not pulled low on the ninth pulse. See Figure 64 and Figure 65 for sample write and read data transfers, Figure 66 for the timing protocol, and Figure 2 for a more detailed timing diagram. R/W CTRL SLAVE ADDRESS[6:0] A5 SET BY PIN 27 (CS) 0 0 0 0 0 X 0 = WR 1 = RD 08201-016 1 MSB = 1 Figure 63. Slave Address Configuration SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR A(S) DATA A(S) DATA A(S) P 08201-017 S S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT Figure 64. I2C Write Data Transfer SLAVE ADDR, LSB = 0 (WR) A(S) SUBADDR A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = NO ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER 08201-018 S S = START BIT A(S) = ACKNOWLEDGE BY SLAVE Figure 65. I2C Read Data Transfer START BIT SDA SLAVE ADDRESS A6 SUBADDRESS A5 A7 STOP BIT DATA A0 D7 D0 S WR SLAVE ADDR[4:0] ACK ACK SUBADDR[6:1] Figure 66. I2C Data Transfer Timing Rev. A | Page 22 of 40 ACK DATA[6:1] P 08201-002 SCL ADRF6750 SPI INTERFACE SPI Serial Interface Functionality The ADRF6750 also supports the SPI protocol. The part powers up in I2C mode but is not locked in this mode. To stay in I2C mode, it is recommended that the user tie the CS line to either 3.3 V or GND, thus disabling SPI mode. It is not possible to lock the I2C mode, but it is possible to select and lock the SPI mode. The SPI serial interface of the ADRF6750 consists of the CS, SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to select the device when more than one device is connected to the serial clock and data lines. CLK is used to clock data in and out of the part. The SDI pin is used to write to the registers. The SDO pin is a dedicated output for the read mode. The part operates in slave mode and requires an externally applied serial clock to the CLK pin. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. To select and lock the SPI mode, three pulses must be sent to the CS pin, as shown in Figure 67. When the SPI protocol is locked in, it cannot be unlocked while the device is still powered up. To reset the serial interface, the part must be powered down and powered up again. Figure 68 shows an example of a write operation to the ADRF6750. Data is clocked into the registers on the rising edge of CLK using a 24-bit write command. The first eight bits represent the write command 0xD4, the next eight bits are the register address, and the final eight bits are the data to be written to the specific register. Figure 69 shows an example of a read operation. In this example, a shortened 16-bit write command is first used to select the appropriate register for a read operation, the first eight bits representing the write command 0xD4 and the final eight bits representing the specific register. Then the CS line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command 0xD5 and the final eight bits representing the contents of the register being read. Figure 3 shows the timing for both SPI read and SPI write operations. Serial Interface Selection The CS pin controls selection of the I2C or SPI interface. Figure 67 shows the selection process that is required to lock the SPI mode. To communicate with the part using the SPI protocol, three pulses must be sent to the CS pin. On the third rising edge, the part selects and locks the SPI protocol. Consistent with most SPI standards, the CS pin must be held low during all SPI communication to the part and held high at all other times. A B C CS (STARTING HIGH) SPI LOCKED ON THIRD RISING EDGE A B C SPI LOCKED ON THIRD RISING EDGE Figure 67. Selecting the SPI Protocol Rev. A | Page 23 of 40 SPI FRAMING EDGE 08201-019 CS (STARTING LOW) SPI FRAMING EDGE ADRF6750 ••• CS ••• CLK D7 D6 D5 START D4 D3 D2 D1 D0 D7 D6 D5 D4 WRITE COMMAND [0xD4] D3 D2 D1 D0 D2 D1 D0 ••• REGISTER ADDRESS CS (CONTINUED) • • • CLK (CONTINUED) • • • SDI (CONTINUED) • • • D7 D6 D5 D4 D3 08201-020 SDI STOP DATA BYTE Figure 68. SPI Byte Write Example ••• CS ••• CLK SDI D7 D6 D5 START D4 D3 D2 D1 D0 D7 D6 D5 D4 WRITE COMMAND [0xD4] D3 D2 D1 D0 ••• REGISTER ADDRESS CS SDI D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X SDO X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 START READ COMMAND [0xD5] DATA BYTE Figure 69. SPI Byte Read Example Rev. A | Page 24 of 40 STOP 08201-021 CLK ADRF6750 PROGRAM MODES Charge Pump Current The ADRF6750 has 34 8-bit registers to allow program control of a number of functions. Either an SPI or an I2C interface can be used to program the register set. For details about the interfaces and timing, see Figure 63 to Figure 69. The registers are documented in Table 6 to Table 24. Register CR9, Bits[7:4], specify the charge pump current setting. With an RSET value of 4.7 kΩ, the maximum charge pump current is 5 mA. The following equation applies: Several settings in the ADRF6750 are double-buffered. These settings include the FRAC value, the INT value, the 5-bit R-divider value, the reference frequency doubler, the R/2 divider, and the charge pump current setting. This means that two events must occur before the part uses a new value for any of the double-buffered settings. First, the new value is latched into the device by writing to the appropriate register. Next, a new write must be performed on Register CR0. When Register CR0 is written, a new PLL acquisition takes place. For example, updating the fractional value involves a write to Register CR3, Register CR2, Register CR1, and Register CR0. Register CR3 should be written to first, followed by Register CR2 and Register CR1 and, finally, Register CR0. The new acquisition begins after the write to Register CR0. Double buffering ensures that the bits written to do not take effect until after the write to Register CR0. 12-Bit Integer Value Register CR7 and Register CR6 program the integer value (INT) of the feedback division factor. The INT value is a 12-bit number whose MSBs are programmed through Register CR7, Bits[3:0]. The LSBs are programmed through Register CR6, Bits[7:0]. The INT value is used in Equation 1 to set the LO frequency. Note that these registers are double-buffered. ICPmax = 23.5/RSET The charge pump current has 16 settings from 312.5 μA to 5 mA. For the loop filter that is specified in the application solution, a charge pump current of 2.5 mA (Register CR9[7:4] = 7) gives a loop bandwidth of 50 kHz, which is the recommended loop bandwidth setting. Transmit Disable Control (TXDIS) The transmit disable control (TXDIS) is used to disable the RF output. TXDIS is normally held low. When asserted (brought high), it disables the RF output. Register CR14 is used to control which circuit blocks are powered down when TXDIS is asserted. To meet both the off isolation power specifications and the turn-on/ turn-off settling time specifications, a value of 0x1B should be loaded into Register CR14. This effectively ensures that the attenuator is always enabled when TXDIS is asserted, even if other circuitry is disabled. Power-Down/Power-Up Control Bits The three programmable power-up and power-down control bits are as follows: • • 25-Bit Fractional Value Register CR3 to Register CR0 program the fractional value (FRAC) of the feedback division factor. The FRAC value is a 25-bit number whose MSB is programmed through Register CR3, Bit 0. The LSB is programmed through Register CR0, Bit 0. The FRAC value is used in Equation 1 to set the LO frequency. Note that these registers are double-buffered. Reference Input Path The reference input path consists of a reference frequency doubler, a 5-bit reference divider, and a divide-by-2 function (see Figure 53). The doubler is programmed through Register CR10, Bit 5. The 5-bit divider is enabled by programming Register CR5, Bit 4, and the division ratio is programmed through Register CR10, Bits[4:0]. The R/2 divider is programmed through Register CR10, Bit 6. Note that these registers are double-buffered. When using a 10 MHz reference input frequency, enable the doubler and disable the 5-bit divider and divide-by-2 to ensure a PFD frequency of 20 MHz. As mentioned in the Reference Input Path section, making the PFD frequency higher improves the system noise performance. • Register CR12, Bit 2. Master power control bit for the PLL, including the VCO. This bit is normally set to a default value of 0 to power up the PLL. Register CR27, Bit 2. Controls the LO monitor outputs, LOMONP and LOMONN. The default is 0 when the monitor outputs are powered down. Setting this bit to 1 powers up the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm, or −24 dBm, as controlled by Register CR27, Bits[1:0]. Register CR29, Bit 0. Controls the quadrature modulator power. The default is 0, which powers down the modulator. Write a 1 to this bit to power up the modulator. Lock Detect (LDET) Lock detect is enabled by setting Register CR23, Bit 4, to 1. Register CR23, Bit 3 sets the number of up/down pulses generated by the PFD before lock detect is declared. The default is 3072 pulses, which is selected when Bit 3 is set to 0. A more aggressive setting of 2048 is selected when Bit 3 is set to 1. This improves the lock detect time by 50 μs. Note, however, that it does not affect the acquisition time to 100 Hz. Register CR23, Bit 2 should be set to 0 for best operation. This bit sets up the PFD up/down pulses to a coarse or low precision setting. Rev. A | Page 25 of 40 ADRF6750 VCO Autocalibration The VCO uses an autocalibration technique to select the correct VCO and band, as explained in the Voltage-Controlled Oscillator (VCO) section. Register CR24, Bit 0, controls whether the autocalibration is enabled. For normal operation, autocalibration needs to be enabled. However, if using cumulative frequency steps of 100 kHz or less, autocalibration can be disabled by setting this bit to 1 and then a new acquisition is initiated by writing to Register CR0. Attenuator The attenuator can be programmed from 0 dB to 47 dB in steps of 1 dB. Control is through Register CR30, Bits[5:0]. Revision Readback The revision of the silicon die can be read back via Register CR33. Rev. A | Page 26 of 40 ADRF6750 REGISTER MAP REGISTER MAP SUMMARY Table 6. Register Map Summary Register Address (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Register Name CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Rev. A | Page 27 of 40 Description Fractional Word 4 Fractional Word 3 Fractional Word 2 Fractional Word 1 Reserved 5-bit reference divider enable Integer Word 2 Integer Word 1 and muxout control Reserved Charge pump current setting Reference frequency control Reserved PLL power-up Reserved TXDIS control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Lock detector control Autocalibration Reserved Reserved LO monitor output and External VCO control Internal VCO power-down Modulator Attenuator Reserved Reserved Revision code ADRF6750 REGISTER BIT DESCRIPTIONS Table 11. Register CR5 (Address 0x05), 5-Bit Reference Divider Enable Table 7. Register CR0 (Address 0x00), Fractional Word 4 Bit 7 6 5 4 3 2 1 0 1 1 Description Fractional Word F7 Fractional Word F6 Fractional Word F5 Fractional Word F4 Fractional Word F3 Fractional Word F2 Fractional Word F1 Fractional Word F0 (LSB) Bit 7 6 5 4 3 2 1 0 Double-buffered. Loaded on the write to Register CR0. Table 8. Register CR1 (Address 0x01), Fractional Word 3 Bit 7 6 5 4 3 2 1 0 1 Description1 Fractional Word F15 Fractional Word F14 Fractional Word F13 Fractional Word F12 Fractional Word F11 Fractional Word F10 Fractional Word F9 Fractional Word F8 1 Bit 7 6 5 4 3 2 1 0 Table 9. Register CR2 (Address 0x02), Fractional Word 2 1 Description1 Fractional Word F23 Fractional Word F22 Fractional Word F21 Fractional Word F20 Fractional Word F19 Fractional Word F18 Fractional Word F17 Fractional Word F16 1 Double-buffered. Loaded on the write to Register CR0. Bit [7:4] Double-buffered. Loaded on the write to Register CR0. Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Fractional Word F24 (MSB)1 Description1 Integer Word N7 Integer Word N6 Integer Word N5 Integer Word N4 Integer Word N3 Integer Word N2 Integer Word N1 Integer Word N0 Table 13. Register CR7 (Address 0x07), Integer Word 1 and Muxout Control Table 10. Register CR3 (Address 0x03), Fractional Word 1 1 Double-buffered. Loaded on the write to Register CR0. Table 12. Register CR6 (Address 0x06), Integer Word 2 Double-buffered. Loaded on the write to Register CR0. Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved 5-bit R-divider enable1 0 = disable 5-bit R-divider (default) 1 = enable 5-bit R-divider Reserved Reserved Reserved Reserved 3 2 1 0 1 Description Muxout control 0000 = tristate 0001 = logic high 0010 = logic low 1101 = RCLK/2 1110 = NCLK/2 Integer Word N111 Integer Word N101 Integer Word N91 Integer Word N81 Double-buffered. Loaded on the write to Register CR0. Double-buffered. Loaded on the write to Register CR0. Rev. A | Page 28 of 40 ADRF6750 Table 14. Register CR9 (Address 0x09), Charge Pump Current Setting Bit [7:4] 3 2 1 0 1 Description Charge pump current1 0000 = 0.31 mA (default) 0001 = 0.63 mA 0010 = 0.94 mA 0011 = 1.25 mA 0100 = 1.57 mA 0101 = 1.88 mA 0110 = 2.19 mA 0111 = 2.50 mA 1000 = 2.81 mA 1001 = 3.13 mA 1010 = 3.44 mA 1011 = 3.75 mA 1100 = 4.06 mA 1101 = 4.38 mA 1110 = 4.69 mA 1111 = 5.00 mA Reserved Reserved Reserved Reserved Table 16. Register CR12 (Address 0x0C), PLL Power-Up Bit 7 6 5 4 3 2 1 0 Table 17. Register CR14 (Address 0x0E), TXDIS Control Bit 7 6 5 4 3 Double-buffered. Loaded on the write to Register CR0. Table 15. Register CR10 (Address 0x0A), Reference Frequency Control 2 1 Bit 7 6 0 5 [4:0] 1 Description Reserved1 R/2 divider enable1 0 = bypass R/2 divider (default) 1 = enable R/2 divider R-doubler enable1 0 = disable doubler (default) 1 = enable doubler 5-bit R-divider setting1 00000 = divide by 32 (default) 00001 = divide by 1 00010 = divide by 2 … 11110 = divide by 30 11111 = divide by 31 Description Reserved Reserved Reserved Reserved Reserved Power down PLL 0 = power up PLL (default) 1 = power down PLL Reserved Reserved Description Reserved Reserved TxDis_attenuator 0 = attenuator always enabled (default) 1 = disable attenuator when TXDIS = 1 TxDis_LOBuf 0 = LOBuf always enabled (default) 1 = disable LOBuf when TXDIS = 1 TxDis_QuadDiv 0 = QuadDiv always enabled (default) 1 = disable QuadDiv when TXDIS = 1 Reserved TxDis_LOX2 0 = LOX2 always enabled (default) 1 = Disable LOX2 when TXDIS = 1 TxDis_RFMON 0 = RFMON always enabled (default) 1 = Disable RFMON when TXDIS = 1 Table 18. Register CR23 (Address 0x17), Lock Detector Control Bit 7 6 5 4 3 Double-buffered. Loaded on the write to Register CR0. 2 1 0 Rev. A | Page 29 of 40 Description Reserved Reserved Reserved Lock detector enable 0 = lock detector disabled (default) 1 = lock detector enabled Lock detector up/down count 0 = 3072 up/down pulses 1 = 2048 up/down pulses Lock detector precision 0 = low, coarse (16 ns) 1 = high, fine (6 ns) Reserved Reserved ADRF6750 Table 19. Register CR24 (Address 0x18), Autocalibration Table 22. Register CR29 (Address 0x1D), Modulator Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Disable autocalibration 0 = enable autocalibration (default) 1 = disable autocalibration Table 20. Register CR27 (Address 0x1B), LO Monitor Output and External VCO Control Bit 7 6 5 4 3 2 [1:0] Description Reserved Reserved Reserved Reserved External VCO control 0 = internal VCO selected 1 = external VCO selected Power up LO monitor output 0 = power down (default) 1 = power up Monitor output power into 50 Ω 00 = −24 dBm (default) 01 = −18 dBm 10 = −12 dBm 11 = −6 dBm Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power up modulator 0 = power down (default) 1 = power up Table 23. Register CR30 (Address 0x1E), Attenuator Bit 7 6 [5:0] Description Reserved Reserved Attenuator A5 to Attenuator A0 000000 = 0 dB 000001 = 1 dB 000010 = 2 dB … 011111 = 31 dB 110000 = 32 dB 110001 = 33 dB … 111101 = 45 dB 111110 = 46 dB 111111 = 47 dB Table 24. Register CR33 (Address 0x21), Revision Code1 Table 21. Register CR28 (Address 0x1C), Internal VCO Power-Down Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Internal VCO power-down 0 = power up (default) 1 = power down Reserved Reserved Reserved Reserved Reserved Bit 7 6 5 4 3 2 1 0 1 Description Revision code Revision code Revision code Revision code Revision code Revision code Revision code Revision code Read-only register. Rev. A | Page 30 of 40 ADRF6750 SUGGESTED POWER-UP SEQUENCE INITIAL REGISTER WRITE SEQUENCE After applying power to the part, perform the initial register write sequence that follows. Note that Register CR33, Register CR32, and Register CR31 are read-only registers. Also note that all writable registers should be written to on power-up. Refer to the Register Map section for more details on all registers. 1. Write Register CR30: 0x00. Set attenuator to 0 dB gain. 2. Write Register CR29: 0x00. Modulator is powered down. The modulator is powered down by default to ensure that no spurious signals can occur on the RF output when the PLL is carrying out its first acquisition. The modulator should be powered up only when the PLL is locked. 25. Write Register CR6: 0xXX. Set according to Equation 1 in the Theory of Operation section. 26. Write Register CR5: 0x00. Disable the 5-bit reference divider. 27. Write Register CR4: 0x01. Reserved register. 28. Write Register CR3: 0x0X. Set according to Equation 1 in the Theory of Operation section. 29. Write Register CR2: 0xXX. Set according to Equation 1 in the Theory of Operation section. 30. Write Register CR1: 0xXX. Set according to Equation 1 in the Theory of Operation section. 31. Write Register CR0: 0xXX. Set according to Equation 1 in the Theory of Operation section. Register CR0 must be the last register written for all the double-buffered bit writes to take effect. 3. Write Register CR28: 0x01. Power up the internal VCO. Write 0x21 if using an external VCO. 4. Write Register CR27: 0x00. Power down the LO monitor and select the internal VCO. Write 0x08 to select an external VCO. 5. Write Register CR26: 0x00. Reserved register. 6. Write Register CR25: 0x32. Reserved register. 33. Write Register CR29: 0x01. Power up modulator. The write to Register CR29 does not need to be followed by a write to Register CR0 because this register is not double-buffered. 7. Write Register CR24: 0x18. Enable autocalibration. Example—Changing the LO Frequency 8. Write Register CR23: 0x70. Enable lock detector and choose the recommended lock detect timing. 9. Write Register CR22: 0x00. Reserved register. Following is an example of how to change the LO frequency after the initialization sequence. Using an example in which the PLL is locked to 1200 MHz, the following conditions apply: 32. Monitor the LDET output or wait 170 μs to ensure that the PLL is locked. • • 10. Write Register CR21: 0x00. Reserved register. 11. Write Register CR20: 0x00. Reserved register. fPFD = 20 MHz (assumed) Divide ratio N = 60, so INT = 60 decimal and FRAC = 0 The INT registers contain the following values: Register CR7 = 0x00 and Register CR6 = 0x3C 12. Write Register CR19: 0x00. Reserved register. 13. Write Register CR18: 0x00. Reserved register. The FRAC registers contain the following values: Register CR3 = 0x00, Register CR2 = 0x00, Register CR1 = 0x00, and Register CR0 = 0x00 14. Write Register CR17: 0x00. Reserved register. 15. Write Register CR16: 0x00. Reserved register. 16. Write Register CR15: 0x00. Reserved register. To change the LO frequency to 1230 MHz, the divide ratio N must be set to 61.5. Therefore, INT must be set to 61 decimal and FRAC must be set to 16777216 by writing to the following registers: 17. Write Register CR14: 0x1B. The attenuator is always enabled, even when TXDIS is asserted. 18. Write Register CR13: 0x18. Reserved register. 19. Write Register CR12: 0x08. PLL powered up. 20. Write Register CR11: 0x00. Reserved register. 1. Set the INT registers as follows: Register CR7 = 0x00, Register CR6 = 0x3D 2. Set the FRAC registers as follows: Register CR3 = 0x01, Register CR2 = 0x00, Register CR1 = 0x00, Register CR0 = 0x00 21. Write Register CR10: 0x21. The reference frequency doubler is enabled, and the 5-bit divider and R/2 divider are bypassed. 22. Write Register CR9: 0x70. With the recommended loop filter component values and RSET = 4.7 kΩ, as shown in Figure 71, the charge pump current is set to 2.5 mA for a loop bandwidth of 50 kHz. Note that Register CR0 should be the last write in this sequence. Writing to Register CR0 causes all double-buffered registers to be updated, including the INT and FRAC registers, and starts a new PLL acquisition. 23. Write Register CR8: 0x00. Reserved register. If the cumulative frequency step is 100 kHz or less, the user can turn off autocalibration. This process involves an additional write of 0x19 to Register CR24, resulting in a smoother frequency step and shorter acquisition time. 24. Write Register CR7: 0x0X. Set according to Equation 1 in the Theory of Operation section. Also sets the MUXOUT pin to tristate. Rev. A | Page 31 of 40 ADRF6750 EVALUATION BOARD GENERAL DESCRIPTION Recommended Decoupling for Supplies This board is designed to allow the user to evaluate the performance of the ADRF6750. It contains the following: The external 5 V supply is decoupled initially by a 10 μF capacitor and then further by a parallel combination of 100 nF and 10 pF capacitors that are placed as close to the DUT as possible for good local decoupling. The regulator output should be decoupled by a parallel combination of 10 pF and 220 μF capacitors. The 220 μF capacitor decouples broadband noise, which leads to better phase noise and is recommended for best performance. Case Size C 220 μF capacitors are used to minimize area. A parallel combination of 100 nF and 10 pF capacitors should be placed on each VREGx pin. Again, these capacitors are placed as close to the pins as possible. The impedance of all these capacitors should be low and constant across a broad frequency range. Surface-mount multilayered ceramic chip (MLCC) Class II capacitors provide very low ESL and ESR, which assist in decoupling supply noise effectively. They also provide good temperature stability and good aging characteristics. Capacitance also changes vs. applied bias voltage. Larger case sizes have less capacitance change vs. applied bias voltage and also lower ESR but higher ESL. The 0603 size capacitors provide a good compromise. X5R and X7R capacitors are examples of these types of capacitors and are recommended for decoupling. • • I/Q modulator with integrated fractional-N PLL and VCO SPI and I2C interface connectors DC biasing and filter circuitry for the baseband inputs Low-pass loop filter circuitry 10 MHz reference clock Circuitry to support differential signaling to the TESTLO inputs, including dc biasing circuitry Circuitry to monitor the LOMON outputs SMA connectors for power supplies and the RF output The evaluation board comes with associated software to allow easy programming of the ADRF6750. HARDWARE DESCRIPTION For more information, refer to the circuit diagram in Figure 71. Power Supplies An external 5 V supply (DUT +5 V) drives both an on-chip 3.3 V regulator and the quadrature modulator. The regulator feeds the VREG1 through VREG6 pins on the chip with 3.3 V. These pins power the PLL circuitry. SPI and I2C Interface The SPI interface connector is a 9-way, D-type connector that can be connected to the printer port of a PC. Figure 70 shows the PC cable diagram that must be used with the provided software. The external reference clock generator can be driven by a 3 V supply or by a 5 V supply. These supplies can be connected via an SMA connector, VCO +V. 1 6 7 8 2 3 There is also an option to use the I2C interface by using the I2C receptacle connector. This is a standard I2C connector. Pull-up resistors are required on the signal lines. The CS pin can be used to set the slave address of the ADRF6750. CS high sets the slave address to 0x60, and CS low sets the slave address to 0x40. CLK 1 2 14 DATA 3 15 LE 4 16 4 9 5 17 18 6 5 9-WAY FEMALE D-TYPE GND 7 PC 19 20 8 21 9 10 22 23 11 24 12 13 25 25-WAY MALE D-TYPE TO PC PRINTER PORT Figure 70. SPI PC Cable Diagram Rev. A | Page 32 of 40 08201-022 • • • • • • ADRF6750 Baseband Inputs The pair of I and Q baseband inputs are served by SMA inputs so that they can be driven directly from an external generator, which can also provide the dc bias required. An option is provided to supply this dc bias through Connector J1, as well. There is also an option to filter the baseband inputs, although filtering may not be required, depending on the quality of the baseband source. These inputs also require a dc bias; the following two options are provided: • • Loop Filter A fourth-order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the Σ-Δ modulator used in the N-divider. With the charge pump current set to a midscale value of 2.5 mA and using the on-chip VCO, the loop bandwidth is approximately 60 kHz, and the phase margin is 55°. C0G capacitors are recommended for use in the loop filter because they have low dielectric absorption, which is required for fast and accurate settling time. The use of non-C0G capacitors may result in a long tail being introduced into the settling time transient. Reference Input The reference input can be supplied by a 10 MHz Taitien clock generator or by an external clock through the use of Connector J7. The frequency range of the reference input is from 10 MHz to 20 MHz; if the lower frequency clock is used, the on-chip reference frequency doubler should be used to set the PFD frequency to 20 MHz to optimize phase noise performance. TESTLO Inputs These pins are differential test inputs that allow a variety of debug options. On this board, the capability is provided to drive these pins with an external 2× LO signal that is then applied to an Anaren balun to provide a differential input signal. When driving the TESTLO pins, the PLL can be bypassed, and the modulator can be driven directly by this external 2× LO signal. A dc bias point of 3.3 V through a series inductor path. A resistor in parallel is provided to de-Q any resonance. A dc bias point, which can be varied from 0 V to 3.3 V through a resistor divider network. Note that these resistors should be large in value to ensure that the current drawn is small and that the resistors have little effect on the input resistance. If these pins are not used, ground them by inserting 0 Ω resistors in R47 and R54. LOMON Outputs These pins are differential LO monitor outputs that provide a replica of the internal LO frequency at 1× LO. The single-ended power in a 50 Ω load can be programmed to −24 dBm, −18 dBm, −12 dBm, or −6 dBm. These open-collector outputs must be terminated to 3.3 V. Because both outputs must be terminated to 50 Ω, options are provided to terminate to 3.3 V using onboard 50 Ω resistors or by series inductors (or a ferrite bead), in which case the 50 Ω termination is provided by the measuring instrument. If not used, these outputs should be tied to REGOUT. CCOMPx Pins The CCOMPx pins are internal compensation nodes that must be decoupled to ground with a 100 nF capacitor. MUXOUT MUXOUT is a test output that allows different internal nodes to be monitored. It is a CMOS output stage that requires no termination. Lock Detect (LDET) Lock detect is a CMOS output that indicates the state of the PLL. A high level indicates a locked condition, and a low level indicates a loss of lock condition. TXDIS This input disables the RF output. It can be driven from an external stimulus or simply connected high or low by Jumper J18. RF Output (RFOUT) RFOUT is the RF output of the ADRF6750. RFOUT MOD should be grounded in the user application. Rev. A | Page 33 of 40 ADRF6750 USER-DEFINED VALUE 08201-072 Figure 71. Applications Circuit Schematic Rev. A | Page 34 of 40 ADRF6750 PCB ARTWORK 08201-073 Component Placement 08201-074 Figure 72. Evaluation Board, Top Side Component Placement Figure 73. Evaluation Board, Bottom Side Component Placement Rev. A | Page 35 of 40 ADRF6750 08201-075 PCB Layer Information 08201-076 Figure 74. Evaluation Board, Top Side—Layer 1 Figure 75. Evaluation Board, Bottom Side—Layer 4 Rev. A | Page 36 of 40 08201-077 ADRF6750 08201-078 Figure 76. Evaluation Board, Ground—Layer 2 Figure 77. Evaluation Board Power—Layer 3 Rev. A | Page 37 of 40 ADRF6750 BILL OF MATERIALS Table 25. Bill of Materials Qty 1 1 1 1 2 13 Description ADRF6750 LFCSP, 56-lead 8 mm × 8 mm VCO, 10 MHz Connector, 9-pin, D-sub plug, SDEX9PNTD Connector, I2C, SEMCONN receptacle Capacitor, 10 μF, 25 V, tantalum, TAJ-C Capacitor, 10 pF, 50 V, ceramic, C0G, 0402 Manufacturer Analog Devices Jauch ITW McMurdo Molex AVX Murata Part Number ADRF6750ACPZ O 10.0-VX3Y-T1 FEC 150750 15830064 FEC 197518 FEC 8819564 Capacitor, 100 nF, 25 V, X7R, ceramic, 0603 AVX FEC 317287 Capacitor, 220 μF, 6.3 V, tantalum, Case Size C Capacitor spacing, 0402 (do not install) Capacitor, 1 nF, 50 V, XR7, ceramic, 0603 Capacitor, 47 nF, 50 V, Xr7, ceramic, 1206 Capacitor, 680 pF, 50 V, NPO, ceramic, 0603 Capacitor, 1 nF, 50 V, C0G, ceramic, 0402 Capacitor, 100 pF, 50 V, C0G, ceramic, 0402 SMA end launch connector AVX FEC 197087 Murata Murata Murata Murata Murata Johnson/Emerson FEC 722170 FEC 1740542 FEC 430997 FEC 8819556 FEC 8819572 142-0701-851 3 Reference Designator DUT Y2 SPI CONN C1, C21 C2, C4, C6, C8, C10, C12, C14, C16, C18, C19, C48, C53, C55 C3, C5, C7, C9, C11, C13, C15, C17, C22, C47, C49 to C52, C54 C20 C30 to C33 C26 C24 C23, C25 C38, C39 C40, C44, C46, C57 J1 to J5, J7, J10 to J12, J14, J15, TXDIS J18, J20, J21 Jumper, 3-pin + shunt Harwin 4 4 4 5 2 1 2 2 1 2 3 4 3 L1, L2 L3, L4 R2 to R5 R6 to R9, R36 R10, R11 R13 R14, R39 R12, R16 R15 R17, R18 R35, R44, R45 R48 to R51 R59 to R61 Inductor, 20 nH, 0402, LQW series Inductor, 10 μH, 0805, LQM series Resistor spacing, 0603 (user-defined values) Resistor, 0 Ω, 1/16 W, 1%, 0402 Resistor, 0402, spacing (do not install) Resistor, 4.7 kΩ, 1/10 W, 1%, 0603 Resistor, 1.2 kΩ, 1/10 W, 5%, 0603 Resistor, 270 Ω, 1/16 W, 1%, 0603 Resistor, 300 Ω, 1/16 W, 1%, 0603 Resistor, 0603, spacing (do not install) Resistor, 51 Ω, 1/16 W, 5%, 0402 Resistor, 330 Ω, 1/10 W, 5%, 0805 Resistor, 100 Ω, 1/10 W, 5%, 0805 Murata Murata FEC 148533 and FEC 150411 LQW15AN20N LQM21FN1N100M Vishay Draloric FEC 1158241 Bourns Yageo Multicomp Multicomp CR0603-FX-472 FEC 9233393 FEC 9330917 FEC 93330968 Bourns Bourns Bourns CR0402-JW-510 CR0805-JW-331 CR0805-JW-101 15 1 4 1 1 2 4 4 12 Rev. A | Page 38 of 40 ADRF6750 OUTLINE DIMENSIONS 8.00 BSC SQ 0.30 0.23 0.18 0.60 MAX 0.60 MAX 56 43 42 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.95 4.80 SQ 4.65 EXPOSED PAD (BOTTOM VIEW) 7.75 BSC SQ 0.50 0.40 0.30 14 29 28 15 0.30 MIN 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 0.50 BSC 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 041807-B 1.00 0.85 0.80 6.50 REF Figure 78. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6750ACPZ-R7 ADRF6750-EVALZ 1 Temperature Range −40°C to +85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 39 of 40 Package Option CP-56-3 ADRF6750 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08201-0-4/10(0) Rev. A | Page 40 of 40